NEURICAM
S.p.A.
Via S. Maria Maddalena, 12 - 38100 Trento - Italy
Tel. +
39 0461 260552
Fax. +
39 0461 260617
email: info@neuricam.com - http:\\www.neuricam.com
VISoc Datasheet
Rel. 08/03
Authors
Filippo Cioni, Daniele Covi
ID Project Name
VISoc
Date
08 / 04 / 2003
Revision
Rel 08-03
Status
Official, Preliminary
Approved by
Alvise Sartori, Pietro Chiesa, Marco Galluppi
Number of Pages
128
Scope / Overview
Customer documentation of the VISoc chip. It includes a description from hardware and software
point of view. It contains a detailed description of the communication protocols and registers
accessible to the host controller. The functionalities of the RISC processor are described in the
software section. The TOTEM and digital camera functionalities are explained during their
corresponding register description in the hardware part
Rel.
Date
Pages
Description of changes
08-03 08 / 04 / 2003 128
Official Release
Record of revisions
Disclaimer
Information furnished by NeuriCam is believed to be accurate and reliable. However, no responsibility is assumed by
NeuriCam for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of NeuriCam.
NeuriCam does not assume any responsibility for use of any circuitry described, and NeuriCam reserves the right at any
time without notice to make corrections, modifications, enhancements, improvements, and other changes to the said
circuitry and specifications.
NeuriCam assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using NeuriCam components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
NeuriCam's products are not authorized for use as critical components in life support devices or systems without the
express written approval of NeuriCam. As used herein:
1.
Life support devices or systems are devices or systems which are intended for surgical implant into the body,
or support or sustain life, and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
ESD WARNING! ESD (Electrostatic discharge) sensitive device.
Electrostatic charges as high as 4000 V readily accumulate on the human
body and test equipment and can discharge without detection. Although
VISoc features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
VISoc Datasheet
NeuriCam
Rel 08-03
Preliminary
Page 3 / 128
Index
1
General Description ..................................................................................................................................................7
2
Key Features and Applications .................................................................................................................................9
3
Pin Configuration ...................................................................................................................................................10
3.1
Alphabetical Order Pin list ..................................................................................................................................10
3.2
Numerical Order Pin List ....................................................................................................................................13
3.3
Pinout and Floorplan ...........................................................................................................................................14
4
Detailed Block Description.....................................................................................................................................15
4.1
Power on Reset Block .........................................................................................................................................17
4.2
Loader .................................................................................................................................................................18
4.3
VISoc Digital Camera .........................................................................................................................................19
4.4
Camera Controller (DMA channel).....................................................................................................................21
4.5
SSRAM and FLASH Controller..........................................................................................................................24
4.5.1
Synchronous Access .....................................................................................................................................25
4.5.2
Asynchronous Access...................................................................................................................................25
4.6
Neural DSP: TOTEM and Interpolating LUTs ...................................................................................................26
4.6.1
TOTEM Core Architecture...........................................................................................................................28
4.6.2
Barrel Shifter ................................................................................................................................................30
4.6.3
Interpolating Look-Up Tables ......................................................................................................................31
4.6.4
The Reactive Tabu Search Training Algorithm............................................................................................33
4.7
RISC Processor ...................................................................................................................................................34
4.7.1
Introduction to Programmers........................................................................................................................34
4.7.1.1
Core Register Set ...................................................................................................................................34
4.7.1.2
Auxiliary Register Set............................................................................................................................35
4.7.1.3
RISC Memory Map ...............................................................................................................................35
4.7.1.4
Instruction Set Summary........................................................................................................................36
4.7.2
Data Organization And Addressing Mode....................................................................................................37
4.7.3
Instruction Format ........................................................................................................................................39
4.7.4
Interrupts.......................................................................................................................................................40
4.7.4.1
ILINK Register ......................................................................................................................................40
4.7.4.2
Interrupt Vectors....................................................................................................................................40
4.7.4.3
Interrupt Enables....................................................................................................................................40
4.7.4.4
Returning From Interrupts .....................................................................................................................41
4.7.4.5
Hardware Interrupt Generators ..............................................................................................................41
4.7.4.5.1
Reset .................................................................................................................................................41
4.7.4.5.2
Memory Error ...................................................................................................................................41
4.7.4.5.3
Instruction Error ...............................................................................................................................41
4.7.4.6
Interrupt Times ......................................................................................................................................41
4.7.5
Condition Code Field....................................................................................................................................42
4.7.5.1
Condition Code Register........................................................................................................................42
4.7.5.2
Condition Codes ....................................................................................................................................42
4.7.6
Instruction Set Details ..................................................................................................................................43
4.7.6.1
Arithmetic and Logical Operations........................................................................................................43
4.7.6.2
Single Operand Instructions...................................................................................................................44
4.7.6.2.1
The Breakpoint Instruction ...............................................................................................................45
4.7.6.2.2
The Sleep Instruction........................................................................................................................46
4.7.6.3
Jump, Branch and Loop Operations......................................................................................................46
4.7.6.4
Load and Store Operations.....................................................................................................................47
4.7.6.5
Multiple Shift Operations ......................................................................................................................48
4.7.6.6
AVER Instruction ..................................................................................................................................48
4.7.7
The Zero Overhead Mechanism ...................................................................................................................50
4.7.7.1
Single Instruction Loops........................................................................................................................51
4.7.7.2
Loop Count register ...............................................................................................................................51
4.7.7.3
Branch And Jumps In Loops..................................................................................................................52
4.7.7.4
Instructions With Long Immediate Data In Loops ................................................................................52
4.7.8
Instruction Pipelining ...................................................................................................................................54
4.7.8.1
Long Immediate Operands.....................................................................................................................55
4.7.8.2
Conditional Instruction Timing..............................................................................................................55
4.7.8.3
Jump and Branch Timings .....................................................................................................................56
4.7.9
The I-Cache Structure and Organization ......................................................................................................58
VISoc Datasheet
NeuriCam
Rel 08-03
Preliminary
Page 4 / 128
4.8
SPI Interface........................................................................................................................................................59
4.8.1
SPI Connections ...........................................................................................................................................59
4.8.2
SPI Description.............................................................................................................................................59
4.8.2.1
The Trasmitter .......................................................................................................................................60
4.8.2.2
The Receiver..........................................................................................................................................60
4.8.3
SPI Timing....................................................................................................................................................61
4.9
Dedicated Parallel Port........................................................................................................................................62
4.9.1
PC_SEL General Purpose Output.................................................................................................................62
4.9.2
Dedicated Parallel Port Protocol...................................................................................................................62
4.9.2.1
Address/Control register ........................................................................................................................63
4.9.2.2
Read Transaction ...................................................................................................................................64
4.9.2.3
Write Transaction ..................................................................................................................................65
5
Register Set.............................................................................................................................................................66
5.1
Core Register Set Details ....................................................................................................................................66
5.1.1
Basecase Core Registers...............................................................................................................................66
5.1.2
ILINK1 ILINK2 and BLINK - Link Registers .............................................................................................66
5.1.3
LP_COUNT - Loop Count Register .............................................................................................................66
5.1.4
Immediate Data Indicators............................................................................................................................66
5.1.5
Not implemented registers............................................................................................................................66
5.2
Auxiliary Register Set Details .............................................................................................................................67
5.2.1
STATUS Register.........................................................................................................................................67
5.2.2
SEMAPHORE Register................................................................................................................................68
5.2.3
LP_START and LP_END - Loop Control Registers....................................................................................68
5.2.4
IDENTITY Register .....................................................................................................................................68
5.2.5
DEBUG Register ..........................................................................................................................................69
5.2.6
AUX_IVIC and AUX_CHE_MODE - Cache Control Registers .................................................................69
5.2.7
AUX_SRAM_SEQ Register ........................................................................................................................71
5.2.8
AUX_PC_PORT ..........................................................................................................................................71
5.2.9
AUX_AVERN..............................................................................................................................................71
5.2.10
Build Configuration and Not Implemented Registers ...............................................................................71
5.3
Memory Map Details...........................................................................................................................................72
5.3.1
SRAM - Sram Memory ................................................................................................................................74
5.3.2
WEIGHT_WR - Write Weight Memories....................................................................................................74
5.3.3
CL_ACC - Clear Accumulators....................................................................................................................74
5.3.4
LD_ADDR_MEM Set Weight Memories Address ...................................................................................74
5.3.5
EN_ADDR_INCR - Post Increment.............................................................................................................74
5.3.6
CALC Calculation .....................................................................................................................................75
5.3.7
LD_OUT_REG - Load Output Registers .....................................................................................................75
5.3.8
LD_ADDR_OUT - Select Neuron for Output..............................................................................................75
5.3.9
BARREL - Barrel shift Factor......................................................................................................................75
5.3.10
INT_BYP_ADDR - Bypass Mode for Interpolator Address.....................................................................75
5.3.11
INT_SEL - Interpolation Select ................................................................................................................76
5.3.12
INT_BASE - Interpolator Base Memory ..................................................................................................76
5.3.13
INT_SLOPE - Interpolator Slope Memory ...............................................................................................77
5.3.14
INT_READ - Interpolator Output Read ....................................................................................................77
5.3.15
TOTEM_PRESC - Prescaler Setting.........................................................................................................77
5.3.16
V_CTRL - Camera Control Register.........................................................................................................78
5.3.17
DEST_ADDR - Data Destination Address ...............................................................................................78
5.3.18
START_ADDR - AOI Corner Setting ......................................................................................................78
5.3.19
STOP_ADDR - AOI Corner Setting .........................................................................................................78
5.3.20
V_DMA - DMA Start ...............................................................................................................................79
5.3.21
SPI_RX_REG - SPI Rx Register...............................................................................................................79
5.3.22
SPI_RX_STAT - SPI Rx Status ................................................................................................................79
5.3.23
SPI_TX_REG - SPI Tx Register...............................................................................................................79
5.3.24
SPI_TX_STAT - SPI Tx Status.................................................................................................................79
5.3.25
DVREF - V
REF
Setting ..............................................................................................................................79
5.3.26
DVGAP - V
GAP
Setting .............................................................................................................................80
5.3.27
DVCM - V
CM
Setting ................................................................................................................................80
5.3.28
OUT_PORT - Output Port Register ..........................................................................................................80
5.3.29
FLASH - Flash Memory ...........................................................................................................................80
6
General Device Specifications................................................................................................................................81
VISoc Datasheet
NeuriCam
Rel 08-03
Preliminary
Page 5 / 128
6.1
Absolute maximum ratings..................................................................................................................................81
6.2
Operating Ratings................................................................................................................................................81
6.3
Logic Level Specifications..................................................................................................................................82
6.4
AC Parameters.....................................................................................................................................................83
6.4.1
Clock ............................................................................................................................................................83
6.4.2
Reset .............................................................................................................................................................83
6.4.3
SPI ................................................................................................................................................................83
6.4.4
PC Port .........................................................................................................................................................83
6.4.5
Memory Interface .........................................................................................................................................83
6.4.5.1
Write Cycle............................................................................................................................................83
6.4.5.2
Read Cycle.............................................................................................................................................83
6.5
Elettro-Optical Charachteristic of the Digital Camera ........................................................................................84
6.6
Optical Characteristics of the Glasslid ................................................................................................................85
6.7
Outline Dimensions and Mechanical Tolerances ................................................................................................86
7
Typical Electrical Schematic ..................................................................................................................................87
8
RISC Software Description ....................................................................................................................................89
8.1
Hardware/Software Interface...............................................................................................................................89
9
Instruction Set.........................................................................................................................................................90
9.1
ADC Addition with carry.................................................................................................................................90
9.2
ADD Addition ..................................................................................................................................................91
9.3
AND Logical bitwise and.................................................................................................................................92
9.4
ASL/LSL Arithmetic shift left Single shift ...................................................................................................93
9.5
ASL Arithmetic shift left Multiple shift ........................................................................................................94
9.6
ASR Arithmetic shift right Single shift .........................................................................................................95
9.7
ASR Arithmetic shift right Multiple shift......................................................................................................96
9.8
ASUB Absolute subtraction .............................................................................................................................97
9.9
AVER Average.................................................................................................................................................98
9.10
BIC Logical bitwise and with invert ............................................................................................................99
9.11
Bcc Branch conditionally............................................................................................................................100
9.12
BLcc Branch and link conditionally ...........................................................................................................101
9.13
BRK Breakpoint..........................................................................................................................................102
9.14
EXT Zero extend.........................................................................................................................................103
9.15
FLAG Set flags ...........................................................................................................................................104
9.16
Jcc Jump conditionally................................................................................................................................105
9.17
JLcc Jump and link conditionally ...............................................................................................................106
9.18
LD Delayed load from memory ..................................................................................................................107
9.19
LPcc Loop set up .......................................................................................................................................108
9.20
LR Load from auxiliary registers................................................................................................................109
9.21
LSL Logical shift left..................................................................................................................................110
9.22
LSR Logical shift right Single shift .........................................................................................................111
9.23
LSR Logical shift right Multiple shift......................................................................................................112
9.24
MOV Move contents...................................................................................................................................113
9.25
NOP No operation.......................................................................................................................................114
9.26
OR Logical bitwise or.................................................................................................................................115
9.27
RLC Rotate left through carry ....................................................................................................................116
9.28
ROR Rotate right Single step...................................................................................................................117
9.29
ROR Rotate right Multiple step ...............................................................................................................118
9.30
RRC Rotate right through carry ..................................................................................................................119
9.31
SBC Subtract with carry ............................................................................................................................120
9.32
SEX Sign extend .........................................................................................................................................121
9.33
SLEEP Enter sleep mode ............................................................................................................................122
9.34
SR Store to auxiliary register......................................................................................................................123
9.35
ST Store to memory....................................................................................................................................124
9.36
SUB Subtract ..............................................................................................................................................126
9.37
XOR Logical bitwise exclusive or ..............................................................................................................127
10
Program Examples in Assembly code ..................................................................................................................128
10.1
SRAM and FLASH access.............................................................................................................................128
10.2
TOTEM Neural Network usage.....................................................................................................................128
10.2.1
Weight Memories Filling ........................................................................................................................128
10.2.2
Weight memory read procedure ..............................................................................................................128
10.2.3
Intepolator Memories Filling ..................................................................................................................128
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