NL81480A 1K X 64
NL82480A 2K X 64
Content Addressable Memory
( NCAM )
Revision 1.0
1
Features
1K or 2K x 64 CAM architecture with 16-bit I/O
interface
Dual configuration registers for rapid context switching
Readable Device ID
Fast operating mode with no wait states after a no-match
Shiftable Comparand and Mask Register to assist in
mask operations
Validity bits for each location that are reflected in the
Status Register after a read or move from memory
Single cycle reset for the Segment Control Register
Flexible CAM/RAM partitioning on 16 bit boundaries
External /MA and /MM output flags enhance system
performance
External Reset pin works in parallel to internal Power
On Reset circuitry
44-pin PLCC package
5V CMOS technology
Comparand Register
Mask Register 1 &
Mask Register 2
Vali
d
i
t
y
B
i
t
s
P
r
i
o
ri
ty
E
n
c
o
de
r
Data 64
Source &
Destination
Segment
Counters
MUX
DEMUX
802.3/802.5
Translator
Commands
& Status
16
16
16
I/O15 - 0
16
/ MA
CAM Array
1K x 64
2K x 64
Control Register
Status Register
&
Address Decoder
Me
mor
y Con
t
r
ol, M
a
t
c
h
&
Flag L
ogi
c
/ W
/ E
/ CM
/ EC
/ RESET
/ FF
/ FI
/ MF
/ MI
I/O Buffers
/ MM
Figure 1. Block Diagram
Description
The NL81480A and NL82480A are 1K x 64 and 2K x 64
Content Addressable Memories (CAMs) that have been
designed for use in LAN address filtering applications. The
NL8X480A CAMs are pin compatible with MUSIC
Semiconductors' MU9CX480A devices.
Content Addressable Memories (CAMs) operate very
similarly to SRAMs or DRAMs, where memory reads and
writes are executed by specifying unique addresses. In
addition to these operations, data can be presented to the
CAM and compared with the contents of the memory. The
CAM then searches the entire contents in one cycle, and if a
NL81480A 1K X 64
NL82480A 2K X 64
Content Addressable Memory
( NCAM )
Revision 1.0
2
match is detected the device will then output a Match Flag
and the Address of the location where the data resides in the
CAM memory.
The NL8X480A's 64-bit wide CAM array can be configured
into dedicated CAM and RAM partitions on 16-bit
boundaries. When the NL8X480A's 64-bit wide array is
configured into a CAM and RAM partition, only the CAM
portion of the 64-bit wide array will participate in a search.
Upon detection of a match, the device will output the match
flag, the address of the location where the match occurred,
the associated data from the RAM portion of the 64-bit word
can be read and the validity condition. The NL8X480A
devices also have two mask registers which can be
configured to mask the 64-bit wide CAM array on a per bit
basis. Corresponding to each 64-bit wide CAM/RAM word
are 2-bits that store four possible validity conditions: Valid,
Empty, Skip and Random Access. Refer to Table 1. for all
possible validity conditions.
Dedicated Match and Multiple-Match Flags enhance and
simplify hardware control. Multiple NL8X480As can be
cascaded in depth by daisy chaining with no external logic.
The NL8X480A has an internal 64-bit data path and a 16-bit
command and status path, the external interface is through a
16-bit I/O bus which conveys commands, data and status
information to and from the device. A comprehensive
instruction set provides control and programming flexibility.
Skip Bit
Empty Bit
Entry Type
0
0
Valid
0
1
Empty
1
0
Skip
1
1
RAM
Table 1: Validity States
PIN DESCRIPTIONS
/RESET ( Reset, ( Input ))
Driving the /RESET pin Low resets the device. The hardware
reset and the internal Power-on-reset circuitry, initializes the
device to the same conditions. For compatibility with the
MU9C1480, the /RESET pin has an internal pull-up resistor
and may be left unconnected.
/E
(Chip Enable, ( Input ))
The /E input enables the device when it is in the logical Low
state. The falling edge registers the state of the control signals
/W, /CM and /EC. The rising edge locks the Match flag daisy
chain, tri-states the I/O bus, and clocks the Source and
Destination Segment counters. The four possible I/O cycles
are illustrated in Table 2.
/CM
( Data / Command Select, ( Input ))
The logical state of /CM will select either a Data or a
Command operation. When /CM is in its logical High state
then a Data operation is selected and if /CM is in its logical
Low state then a Command operation is selected.
/W
( Write Enable, ( Input ))
The logical state of the /W input determines either a write or
a read operation. When the /W input is in its logical High
state a Read operation is selected and when it is in its logical
Low state a Write operation is selected.
/EC
( Enable Daisy Chain, ( Input ))
The /EC input enables the /MF flag to output the result of a
comparison. If /EC is Low at the falling edge of /E for a
given cycle, the /MF output is enabled Otherwise, the /MF
output is held High. The /EC input enables the /MF -/MI
daisy-chain also, which serves to select the device having the
highest-priority match when the NL8X480As are cascaded in
depth. /EC must be High during initialization.
I/O15-I/O0
( I/O Bus, ( Input and Output ))
The I/O bus conveys data, commands and status information
to and from the NL8X480A. The transactions that can be
accomplished are controlled by the logical state of /W and
/CM. When /E is in the logical High state, I/O15-I/O0 are tri-
stated.
/W
/CM
Operation
Low
Low
Command Write
Low
High
Data Write
High
Low
Command Read
High
High
Data Read
Table 2: I/O Cycles
/MF
( Match Flag, ( Output ))
The /MF output is driven Low when one or more valid
matches occur during a compare cycle. /MF becomes valid
after /E goes High on the cycle that enables the daisy chain.
In a daisy-chain valid matches from the higher priority
devices are passed from the /MI input to /MF.
/MA
( Internal Match Flag, ( Output ))
The /MA output is Low when one or more valid matches
occur. The /MA output is not qualified by /EC or /MI, and
reflects the internal match flag of that device. Whenever the
active register set is changed /MA will be reset .
/MM
( Multiple Match Flag, ( Output ))
The /MM output is Low when one or more valid matches
occur. The /MM output is not qualified by /EC or /MI, and
reflects the internal multiple match flag of that device.
Whenever the active register set is changed /MM will be
reset.
NL81480A 1K X 64
NL82480A 2K X 64
Content Addressable Memory
( NCAM )
Revision 1.0
3
/FF
( Full Flag, ( Output ))
The /FF output goes Low indicating that all the memory
locations have valid data. The System Full Flag is the /FF pin
of the last device in the daisy chain.
/FI
( Full Input, ( Input ))
The /FI input generates a CAM-Memory-System-Full
indication in depth cascaded systems. The /FI pin on the
highest priority device in the daisy chain must be tied Low.
The /FI pin of the lower priority device is connected to the
/FF output of the Next Higher Priority device in the daisy
chain.
VCC, GND
( Power and Ground, ( Inputs ))
VCC pins must be connected to a + 5V power supply and
GND pins must be connected to the ground plane. Pins 1 and
23 are connected to the chip ground and may be left
unconnected for compatibility with existing MU9C1480
layouts; however it is recommended that they be connected to
the system ground plane.
NC
I/O3
I/O2
I/O1
I/O0
/MA
GN
D
/E
C
/CM
/FI
/FF
/M
M
/MI
/MF
GND
/RST
VCC
VCC
NC
/E
/W
NC
NC
I/O15
I/O14
I/O13
I/O12
GN
D
I/O11
I/O10
I/O9
I/O8
NC
NC
I/O7
I/O6
GND
GND
NC
VCC
NC
I/O5
I/O4
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 PIN PLCC
TOP VIEW
Figure 2. Pinout Diagram
FUNCTIONAL DESCRIPTION
The interface to the NL8X480A is through a 16-bit I/O bus
which multiplexes instructions and data. This 16-bit I/O bus
is demultiplexed onto a 64-bit bus which interfaces to the
Comparand register, the two Mask registers and the memory
array. Data is written into the active Comparand Register in
16-bit segments and when the active Segment Control
register reaches its terminal count, the contents of the
Comparand register are automatically compared with the
CAM portion of all the Valid entries in the array. The
Comparand register values may be shifted left or right on a
bit by bit basis to perform data manipulation operations.
There are two sets of configuration registers which allow for
context switching between foreground and background
activities. Each configuration set contains Control, Segment
Control, Address, Mask Register 1, and the Persistent Source
and Destination registers. The current active Configuration
Register set controls, Writes, Reads, Moves and Compare
operations.
NL81480A 1K X 64
NL82480A 2K X 64
Content Addressable Memory
( NCAM )
Revision 1.0
4
At any one time there are two active Mask registers, which
can be selected to mask data write or compare operations.
Mask Register 1 has a foreground and a background mode to
support fast context switching. Mask Register 2 does not
have the foreground or the background mode, but it can be
shifted left or right one bit. If a bit is High in the Mask
register and if the write operation is being performed using
the mask register, then the corresponding bit of the
destination is unchanged during the write cycle.
The Status register is updated after a Compare operation to
include the address of the highest priority matching location,
its Page Address, and internal Match, Multiple Match and
Full flags. A command read operation causes the device with
the highest priority match to output the System Match
Address on the I/O bus, Match flag /MA and Multiple Match
flag /MM. The /MF and /FF outputs are also available and
depend on the /MF and /FF flags of previous devices in the
cascade. These two flags also provide System Match and Full
flags in depth cascaded NL8X480A arrays. If there are no
matches in a depth cascade system during a comparison, read
access to the CAMs ( except the Next Free Address register)
is blocked to avoid bus contention.
The Status register will also be updated with the current state
of the validity bits of the location in memory, after a Read or
a Move operation.
Every word in the CAM array has a Match line which is fed
into a Priority encoder that determines the address of the
highest priority matching location (the match address which
is closest to physical address zero).
Individual devices as well as all devices in a depth cascade
may be accessed with the help of Page Address and Device
Select Registers. A Page Address register in each device
allows a user to program a unique number which simplifies
depth expansion. The contents of the Page Address register
serve as the higher order ( TAG ) bits in the cascaded array.
The page Address Register value when concatenated with the
match address enables a user to identify which device in the
cascade has a matching entry. Loading the contents of the
Page Address Register into the Device Select register enables
a particular device to be selected in a depth cascaded array.
One may address all the devices in a daisy at the same time
( Broadcast Operation ) by setting the device Select value to
FFFFH.
The Next Free Address Register is a 16-bit register which
contains the address of the "next free address" in the CAM.
For the 2K x 64 device bits b10-b0 contain the next free
address and bits b15-b11 contain the lower 5-bits of the Page
Address Register. For the 1K x 64 device bits b9-b0 contain
the next free address and bits b15-b10 contain all "0". This is
illustrated in Table 4.
DEPTH CASCADING
The NL8X480A can be depth cascaded to increase the CAM
size. Multiple NL8X480As can be daisy chained to create a
system that responds as a single large CAM. All CAMs in the
daisy chain execute the commands simultaneously; however,
particular operations ( e.g., Next Free address or the Highest-
priority Match address ) will only be performed by the device
in the chain that has, for example, the first empty location or
the first matching location. The last device's Full flag and
Match flag in a daisy chain represent the System Full Flag
and the System Match Flag. Individual devices in a daisy
chain can be addressed by loading the same values in Page
Address and Device Select registers. Flags connected in the
daisy chain under go a ripple delay as they propagate from
one device to another. It is therefore necessary to extend the
/E High time until the logic in all devices has been resolved
and is in steady state. The /E High time must be greater than
or equal to a number determined by the following equation:
t
EHMFV
+ (n-1) * t
MIVMFV.,,
where "n" is the total number of
CAMs in the cascade.
I/O
/E
/W
/CM
/EC
/MI
/FI
/FF
/MF
I/O
/E
/W
/CM
/EC
/MI
/FI
/FF
/MF
1/O
/E
/W
/CM
/EC
/MI
/FI
/FF
/MF
Vcc
Gnd
System Full
System Match
I/O
/E
/W
/CM
/EC
NL8x48x
NL8x48x
NL8x48x
Figure 3: Depth Cascaded NCAMs
NL81480A 1K X 64
NL82480A 2K X 64
Content Addressable Memory
( NCAM )
Revision 1.0
5
CAM Status
After Hardware Reset or Power On
Reset
After Software Reset
Operating Mode
1480
1480
CAM / RAM Partitioning
64 bits CAM, 0 bits RAM
64 bits CAM, 0 bits RAM
Control register after reset
Contains 0008H
Contains 0008H
Persistent Source and Destination for Data Reads and
Writes
Comparand register
Comparand register
Persistent Source for Command Reads
Status register
Status register
Persistent Destination for Command Writes
Instruction decoder
Instruction decoder
Page Address and Device Select registers
Contain all `0's
Unchanged
Source and Destination Segment Counters Count
Ranges
00B to 11B; loaded with 00B
00B to 11B; loaded with
00B
Address register and Next Free Address register
Contains all `0's
Contains all `0's
Address register auto-increment or decrement
Disabled
Disabled
Validity bits at all memory locations
Skip = 0, Empty = 1
Skip = 0, Empty = 1
Match and Full Flag outputs
Enabled
Enabled
IEEE 802.3 - 802.5 Input Translation
Not Translated
Not Translated
Comparison Masking
Disabled
Disabled
Table 3: Device Control State after Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
/FL
/ MM
Skip
Empty
0
Page Address Bits, PA15 - PA5
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA4- PA0
Match Address, AM9 - AM0
/ MA
Table 4a: Status Register Bit Assignments for NL81480A
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
/FL
/ MM
Skip
Empty
Page Address Bits, PA15 - PA4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA3 - PA0
Match Address, AM10 - AM0
/ MA
Table 4b: Status Register Bit Assignments for NL82480A
b15 b10
b9 b0
Lower 6 bits of the Page Address Register
Next Free Address
Table 4c: Next Free Address Register Bit Assignment for the NL81480A
b15 b11
b10 b0
Lower 5-bits of the Page Address Register
Next Free Address
Table 4d: Next Free Address Register Bit Assignment for the NL82480A
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