FEATURES
WIDE OPERATING FREQUENCY RANGE:
f = 8 to 14 GHz (T
A
= 25
C)
LOW PHASE NOISE
GUARANTEED OPERATING TEMPERATURE RANGE
(T
A
= -25
C to +75
C)
INPUT POWER vs. INPUT FREQUENCY
14 GHz DIVIDE-BY-8
DYNAMIC PRESCALER
10
0
Input Frequency, f (GHz)
Input Power, P
IN
(dBm)
0
-10
2
4
6
8
10
12
14
16
18
T
A
=-25C
to +75C
T
A
=+25C
Recommended
Operating
Region
T
A
= -25C
T
A
= +25C
T
A
= +75C
V
DD
= 3.8V
V
SS1
=0V
V
SS2
=-2.2V
DESCRIPTION
The UPG506B is a GaAs divide-by-8 prescaler capable of
operating up to 14 GHz. It is designed for use in frequency
synthesizers of microwave communication systems and
measurement equipment. The UPG506B is a dynamic fre-
quency divider and employs BFL (Buffered FET Logic) cir-
cuits. The UPG506B is available in a hermetic 8-lead ceramic
flat package.
PART NUMBER
UPG506B
PACKAGE OUTLINE
BF08
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
I
DD
Supply Current
mA
70
105
140
I
SS1
Sink Current
1
I
SS1
= I
DD
- I
SS2
mA
35
I
SS2
Sink Current
1
mA
44
70
96
f
IN(U)
Upper Limit of Input Frequency at P
IN
= +6 dBm
GHz
14
f
IN(L)
Lower Limit of Input Frequency at P
IN
= +6 dBm
GHz
8
P
IN
Input Power at f = 9 to 13 GHz
dBm
2.0
10.0
P
OUT
Output Power at f
IN
= 14 GHz
dBm
0
2.0
R
TH(CH-C)
Thermal Resistance (Channel to Case)
C/W
10.0
ELECTRICAL CHARACTERISTICS
(T
A
= 25
C, V
DD
= +3.8 V, V
SS1
= 0 V, V
SS2
= -2.2 V)
UPG506B
Note:
1. Current is positive into the I
DD
pin and returns through the I
SS1
and I
SS2
pins
.
California Eastern Laboratories
UPG506B
SSB Phase Noise (dBc/Hz)
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
C)
SYMBOLS
PARAMETERS
UNITS
RATINGS
V
DD -
V
SS1
Supply Voltage
V
5
V
SS2
- V
SS1
Supply Current
mA
-5
P
T
Total Power Dissipation
2
W
1.5
P
IN
Input Power Level
dBm
13
T
C
CaseTemperature
C
-65 to +125
T
STG
Storage Temperature
C
-65 to +175
Notes:
1. Operation in excess of any one of these conditions may result in
permanent damage.
2. T
C
125C.
POWER DERATING CURVES
Case Temperature, T
C
(
C)
Total Power Dissipation, P
T
(W)
TYPICAL PERFORMANCE CURVES
(T
A
= 25
C)
10 100 1K 10K 100K 1M
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
Offset from Carrier (Hz)
+75
C
+25
C
SSB PHASE NOISE vs. OFFSET FROM CARRIER
f
IN
= 12.7 GHz
2.5
2.0
1.5
1.0
0.5
0
0
2
4
8
12
18
Input Frequency, f (GHz)
Output Power, P
OUT
(dBm)
6
T
A
= -25C
T
A
= +25C
T
A
= +75C
10
14
16
P
IN
= +10dBm
OUTPUT POWER vs. INPUT FREQUENCY
2.5
2.0
1.5
1.0
0.5
0
0
50
100
150
200
250
110
ELECTRICAL CHARACTERISTICS
(T
A
= -25
C to +75
C, V
DD
= +3.8 V, V
SS1
= 0 V, V
SS2
= -2.2 V)
PART NUMBER
UPG506B
PACKAGE OUTLINE
BF08
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
I
DD
Supply Current
mA
105
I
SS1
Sink Current
1
I
SS1
= I
DD
- I
SS2
mA
35
I
SS2
Sink Current
1
mA
70
f
IN(U)
Upper Limit of Input Frequency at P
IN
= +6 dBm
GHz
13.2
f
IN(L)
Lower Limit of Input Frequency at P
IN
= +6 dBm
GHz
8.2
P
IN
Input Power at f = 9 to 13 GHz
dBm
2.0
10.0
P
OUT
Output Power at f
IN
= 14 GHz
dBm
-1.0
1.0
T
CASE
MAX = 125
C
Note:
1. Current is positive into the I
DD
pin and returns through the I
SS1
and I
SS2
pins
.
UPG506B
TEST CIRCUITS
Notes:
1. Because of the high internal gain and gain compression of the UPG506B, the device is prone to self-oscillation in the absence of an RF input
signal. This self-oscillation can be suppressed by either of the following means:
Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the self-
oscillation (see the test circuit schematic).
Apply a negative voltage through a 1000 ohm resistor to the normally open V
GG1
connection. Typically voltages between 0
and -9 volts will suppress the self-oscillation.
Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no
effect on the reliability or electrical characteristics of the device.
*
For V
SS1,
the bias voltage of -6.0 should be applied through a 2.2 V
Zener Diode (RD2.2FB or IN3394).
*
V
SS1
should be connected to GND through a 2.2 V Zener Diode
(RD2.2FB or IN3394).
V
DD
= 3.8 V
V
SS1
= 0 V (GND)
V
SS2
= 2.2 V
V
DD
= +6.0 V
V
SS2
= 0 V (GND)
C: 1000 - 5000 pF Chip Capacitor
CONFIGURATION 2
Single Positive Bias Supply
CONFIGURATION 3
Single Negative Bias Supply
C: 1000 - 5000 pF Chip Capacitor
V
DD
= 0 V (GND)
V
SS2
= 6 V
C: 1000 - 5000 pF Chip Capacitor
CONFIGURATION 1
2 Bias Supply
C
See Note 1
OPEN
OPEN
OPEN
IN
Zo = 50
10
F
C
10
F
V
SS2
(-6 V)
OUT
Zo = 50
5 IN
6 V
GG1
7 V
GG2
8 V
SS2
V
DD
4
NC 3
V
SS1
2
OUT 1
2.2 V
C
C
-6 V*
C
See Note 1
OPEN
OPEN
OPEN
IN
Zo = 50
GND (0 V) V
SS2
10
F
C
10
F
V
DD
(+6 V)
OUT
Zo = 50
5 IN
6 V
GG1
7 V
GG2
8 V
SS2
V
DD
4
NC 3
V
SS1
2
OUT 1
*
2.2 V
C
C
C
See Note 1
OPEN
OPEN
OPEN
IN
Zo = 50
V
SS2
(-2.2 V)
10
F
C
C
10
F
V
DD
(3.8 V)
V
SS1
(0 V) GND
OUT
Zo = 50
5 IN
6 V
GG1
7 V
GG2
8 V
SS2
V
DD
4
NC 3
V
SS1
2
OUT 1
C
OUTLINE DIMENSIONS
(Units in mm)
7.00.5
2.6
4.40.2
10.40.5
1.7 MAX
1.27
0.1
1.27
0.1
1.27
0.1
8
7
6
5
1
2
3
4
0.4
5.00.2
0.2
+0.05
-0.02
LEAD CONNECTIONS
1. OUTPUT
2. V
SS1
3. NC*
4. V
DD
* No Connection
UPG506B
PACKAGE OUTLINE BFO8
5. INPUT
6. V
GG1
7. V
GG2
8. V
SS2
UPG506B
EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS
CALIFORNIA EASTERN LABORATORIES Headquarters 4590 Patrick Henry Drive Santa Clara, CA 95054-1817 (408) 988-3500 Telex 34-6393 FAX (408) 988-0279
24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) Internet: http://WWW.CEL.COM
PRINTED IN USA ON RECYCLED PAPER -4/97
DATA SUBJECT TO CHANGE WITHOUT NOTICE
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