9 GHz DIVIDE-BY-4
DYNAMIC PRESCALER
FEATURES
WIDE OPERATING FREQUENCY RANGE:
f
IN
= 3.5 to 9.0 GHz (T
A
= 25
C)
DIVISION RATIO OF 4
GUARANTEED OPERATING TEMPERATURE RANGE:
-25
C to +75
C
INPUT POWER vs. INPUT FREQUENCY
ELECTRICAL CHARACTERISTICS
1
(T
A
= 25
C, V
DD
= 3.8 V, V
SS1
= 0 V, V
SS2
= -2.2 V)
UPG503B
Input Power, P
IN
(dBm)
Input Frequency, f (GHz)
T
A
= -25C
T
A
= +25C
T
A
= +75C
T
A
= -25C
to +75C
V
DD
= 3.8V
V
SS1
= 0V
V
SS2
= - 2.2 V
(V
GG1,2
OPEN)
0 1 2 3 4 5 6 7 8 9 10
+10
0
-10
Recommended
Operating
Region
DESCRIPTION
The UPG503B is a GaAs divide-by-4 prescaler that is capable
of operating up to 9 GHz. It is designed to be used in the
frequency synthesizers of microwave communication sys-
tems and measurement equipment. The UPG503B is a
dynamic divider. It employs buffered FET logic (BFL). The
UPG503B is available in a hermetic 8-lead ceramic flat
package.
PART NUMBER
UPG503B
PACKAGE OUTLINE
BF08
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
I
DD
Supply Current
mA
40
80
130
I
SS1
Sink Current
2
I
SS1
= I
DD
- I
SS2
mA
27
I
SS2
Sink Current
2
mA
21
53
93
f
IN(U)
Upper Limit of Input Frequency, P
IN
= +9 to +10 dBm
GHz
8.6
9.0
f
IN(L)
Lower Limit of Input Frequency, P
IN
= +9 to +10 dBm
GHz
3.5
3.7
P
IN
Input Power, f
IN
= 3.7 to 8.6 GHz
dBm
9.0
10.0
f
IN
= 5.0 to 7.4 GHz
dBm
3.0
10.0
P
OUT
Output Power,
f
IN
= 8.6 GHz, P
IN
= +10 dBm
dBm
0
3
f
IN
= 3.7 GHz, P
IN
= +10 dBm
dBm
0
3
R
TH
Thermal Resistance, Channel to Case
C/W
10
Note:
1.Device may exhibit low frequency spur typically below 150 Hz and -45 dBm.
2. Current is positive into the I
DD
pin and returns through the I
SS1
and I
SS2
pins.
California Eastern Laboratories
UPG503B
SYMBOLS
PARAMETERS
UNITS
RATINGS
V
DD-
V
SS1
Supply Voltage
V
5.0
V
SS2
-V
SS1
Supply Voltage
V
-5.0
P
IN
Input Power
dBm
13
P
T
Total Power Dissipation
2
W
1.5
T
STG
Storage Temperature
C
-65 to +175
T
C
Case Temperature
C
-65 to +125
Notes:
1. Operation in excess of any one of these conditions may result in
permanent damage.
2. T
C
125
C
2.5
2.0
1.5
1.0
0.5
0
0
50
100
150
200
250
110
POWER DERATING CURVE
Total Power Dissipation, P
T
(W)
T
CASE
MAX = 125
C
OUTPUT POWER vs. INPUT FREQUENCY
10
100
1K
10K
100K
Offset from Carrier (Hz)
SSB Phase Noise (dBc/Hz)
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
1M
0
1
2
4
5
6
Input Frequency, f
IN
(GHz)
Output Power, P
OUT
(dBm)
3
+10
7
0
-10
8
9
10
V
DD
= 3.8V
V
SS1
=0V
V
SS2
=-2.2V
(V
GG1,2
OPEN)
T
A
= -25C
T
A
= +25C
T
A
= +75C
SSB PHASE NOISE VS.
OFFSET FROM CARRIER
f
IN
= 6.82 GHz, T
A
= 25
C
TYPICAL PERFORMANCE CURVES
(T
A
= 25
)
Case Temperature, T
C
(
C)
PART NUMBER
UPG503B
PACKAGE OUTLINE
BF08
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP MAX
I
DD
Supply Current
mA
80
I
SS1
Sink Current
1
I
SS1
= I
DD
- I
SS2
mA
27
I
SS2
Sink Current
1
mA
53
f
IN(U)
Upper Limit of Input Frequency, P
IN
= +9 to +10 dBm
GHz
8.0
f
IN(L)
Lower Limit of Input Frequency, P
IN
= +9 to +10 dBm
GHz
4.0
P
IN
Input Power, f
IN
= 4.0 to 8.0 GHz
dBm
9.0
10.0
f
IN
= 5.0 to 7.0 GHz
dBm
4.0
10.0
P
OUT
Output Power f
IN
= 8.0 GHz, P
IN
= +10 dBm
dBm
-1.0
2.0
f
IN
= 4.0 GHz, P
IN
= +10 dBm
dBm
-1.0
2.0
ELECTRICAL CHARACTERISTICS
T
A
= 25
C to +75
C, V
DD
= 3.8 V, V
SS1
= 0 V, V
SS2
= -2.2 V)
Note:
1. Current is positive into the I
DD
pin and returns through the I
SS1
and I
SS2
pins.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
C)
*
V
SS1
should be connected to GND through a 2.2 V Zener Diode
(RD2.2FB or IN3394).
V
DD
= 3.8 V
V
SS1
= 0 V (GND)
V
SS2
= 2.2 V
V
DD
= +6.0 V
V
SS2
= 0 V (GND)
C: 1000 - 5000 pF Chip Capacitor
CONFIGURATION 2
Single Positive Bias Supply
CONFIGURATION 3
Single Negative Bias Supply
C: 1000 - 5000 pF Chip Capacitor
V
DD
= 0 V (GND)
V
SS2
= 6 V
C: 1000 - 5000 pF Chip Capacitor
CONFIGURATION 1
2 Bias Supply
*
For V
SS1,
the bias voltage of -6.0 should be applied through a 2.2 V
Zener Diode (RD2.2FB or IN3394).
POWER SUPPLY CONFIGURATIONS
(V
GG1
and V
GG2
are normally open)
Notes:
1. Because of the high internal gain and gain compression of the UPG503B, the device is prone to self-oscillation in the absence of an RF input
signal. This self-oscillation can be suppressed by either of the following means:
Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the self-
oscillation (see the test circuit schematic).
Apply a negative voltage through a 1000 ohm resistor to the normally open V
GG1
connection. Typically voltages between
0 and -9 volts will suppress the self-oscillation.
Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no
effect on the reliability or electrical characteristics of the device.
C
See Note 1
OPEN
OPEN
OPEN
IN
Zo = 50
10
F
C
10
F
V
SS2
(-6 V)
OUT
Zo = 50
5 IN
6 V
GG1
7 V
GG2
8 V
SS2
V
DD
4
NC 3
V
SS1
2
OUT 1
2.2 V
C
C
-6 V*
C
See Note 1
OPEN
OPEN
OPEN
IN
Zo = 50
GND (0 V) V
SS2
10
F
C
10
F
V
DD
(+6 V)
OUT
Zo = 50
5 IN
7 V
GG2
8 V
SS2
V
DD
4
NC 3
V
SS1
2
OUT 1
*
2.2 V
C
C
6 V
GG1
C
See Note 1
OPEN
OPEN
OPEN
IN
Zo = 50
V
SS2
(-2.2 V)
10
F
C
C
10
F
V
DD
(3.8 V)
V
SS1
(0 V) GND
OUT
Zo = 50
5 IN
6 V
GG1
7 V
GG2
8 V
SS2
V
DD
4
NC 3
V
SS1
2
OUT 1
C
UPG503B
7.00.5
2.6
4.40.2
10.40.5
1.7 MAX
1.27
0.1
1.27
0.1
1.27
0.1
8
7
6
5
1
2
3
4
0.4
5.00.2
0.2
+0.05
-0.02
1. OUTPUT
2. V
SS1
3. NC*
4. V
DD
5. INPUT
6. V
GG1
7. V
GG2
8. V
SS2
OUTLINE DIMENSIONS
(Units in mm)
UPG503B
PACKAGE OUTLINE BF08
* No Connection
LEAD CONNECTIONS:
EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS
CALIFORNIA EASTERN LABORATORIES Headquarters 4590 Patrick Henry Drive Santa Clara, CA 95054-1817 (408) 988-3500 Telex 34-6393 FAX (408) 988-0279
24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) Internet: http://WWW.CEL.COM
PRINTED IN USA ON RECYCLED PAPER -4/97
DATA SUBJECT TO CHANGE WITHOUT NOTICE
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