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Document No. S14242EJ1V0DS00 (1st edition)
Date Published July 1999 J CP(K)
Printed in Japan
1999
2.4G bps ATM SONET FRAMER
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD98414
The
PD98414 (NEASCOT-P70
TM
) is one of ATM LSIs and provides the functions of the TC sublayer of the
SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum.
Its main functions include a transmission function for mapping an ATM cell passed from a high-end ATM layer
device to the payload of a 2.4G SONET OC-48c/SDH STM-16 frame and transmitting the cell to a MUX device in the
circuit, and a reception function for separating the overhead and ATM cell from the data string received from a
DEMUX device and transmitting the ATM cell to the ATM layer device.
This LSI is ideal for systems that constitute the ATM network of a LAN or WAN, such as a transmission system,
ATM switch, and high-speed backbone switch.
Detailed descriptions of its functions, etc., are given in the following user's manual. Be sure to read it for
design purposes.
PD98414 User's Manual: S14166E
FEATURES
Supplies the functions of the TC (Transmission Convergence) sublayer recommended by the ATM Forum and
ITU-T.
Supports the concatenation frame of 2.4G bps SONET STS-48c/SDH STM-16c.
ATM layer interface
32-bit, 104-MHz LV-TTL FIFO interface
15-cell transmit/receive FIFO
Supports 52-byte/56-byte cell formats.
Prefixes one-word TAG area to receive cell.
Circuit side interface
16-bit P-ECL level I/O
Either of two modes can be selected for CPU interface
16-bit data bus
Intel-compatible mode [RD, WR, RDY-type]/Motorola-compatible mode [DS, R/W, ACK-type]
Supports two types of overhead interfaces (that can access all overhead areas).
Incorporates overhead byte insert/drop registers.
Incorporates dedicated overhead byte insert/extract interfaces.
Preliminary Data Sheet S14242EJ1V0DS00
2
PD98414
Many OAM functions
Fault: Detection of LOS, OOF, LOF, LOP, OCD, and LCD
Alarm: Detection and transmission of APS, Line AIS, Line RDI, Path AIS, and Path RDI
Receive APS signal and Signal Label (C2 byte) monitoring functions
Bit error rate monitoring function
Transmit/receive message buffer for J0/J1 trace messages (16 bytes or 64 bytes long)
Supports loopback function.
Remote: Two modes (ATM layer loopback and circuit side loopback)
Supports an error generation pseudo frame transmission function for testing.
Three general-purpose input and five general-purpose output ports
Supports JTAG boundary scan test (IEEE1149.1).
0.35-
m CMOS process
+3.3 V single power source
ORDERING INFORMATION
Part Number
Package
PD98414F2-RN1
352-pin plastic BGA (advanced) (35
35 mm)
P
r
el
i
m
i
nary D
a
ta S
heet S
14242E
J1V
0
D
S
00
4
P
D
98414
BLOCK DIAGRAM
Management Interface
JTAG
Serial
Parallel
Rx FIFO
(15 cells)
HEC Compare/Control
Cell Synchronization
Cell Descramble
Idle Cell Drop
Cell Processor Block
Rx Framer Block
Rx FIFO Control
Tx OAM Processor
Block
Tx FIFO
(15 cells)
HEC Generation
Cell Mapping
Cell Scramble
Idle Cell insertion
Cell Processor Block
Li
n
e
I
nte
r
f
ac
e
POH Processor
Tx
Fr
a
m
er
Bl
oc
Frame Descramble
BIP verification
SOH Processor
Tx FIFO Control
Rx
A
T
M
L
a
y
e
r
Inter
f
a
c
e
T
x
A
T
M
L
a
y
e
r
Inter
f
a
c
e
Registers
POH Processor
Frame Scramble
Parallel
Serial
BIP Generation
SOH Processor
Overhead Insertion Block
Output & Input
Tx Framer Block
32
32
MADD
[8
]
MD[
16]
BMO
D
E
DS
_
B
A
C
K2S_
B
A
C
K3S_
B
RW
CS
_
B
PH
IN
T
_
B
R
ESET
_B
Connect to peripheral devices
Overhead Insert Interface
Overhead Extract Interface
A
T
M
La
y
e
r
De
vice
MUX/D
E
MUX Ch
ip
RXCLAV
RXSOC
RX PRTY
RXENB_B
RXCLK
RXCLK_O
RXSEL_B
RXDATA[32]
TXPLD[16]
TPCLK_N/P
(155M)
TCLK_N/P
(155M)
Processor
TL
A
I
S
TP
A
I
S
TL
R
D
I
T
P
RDI
Alarm Instruction
JC
K
JD
I
JM
S
JR
S
T
_
B
JD
O
TOH
T
S
O
H
CK (
25M)
TS
O
H
F
P
TS
O
H
D
[
4
]
TS
O
H
A
V
T
P
O
H
CK (
576
K)
TP
O
H
F
P
TP
O
H
D
TP
O
H
A
V
Rx OAM Processor Block
LO
SS
OO
FS
LO
F
S
LO
PS
LC
DS
LAI
S
S
PA
I
S
S
LR
DIS
PR
D
I
S
B1ER
S
B2ER
S
Overhead Extraction Block
RS
O
HCK
(2
5M)
RS
O
H
F
P
RS
O
HD[
4]
RS
O
H
A
V
RP
O
HCK
(5
76K
)
RP
O
H
F
P
RP
O
H
D
RP
O
H
A
V
POU
T
0
POU
T
1
POU
T
2
POU
T
3
POU
T
4
PIN
0
PIN
1
PIN
2
Alarm Detection
RC
S
(1
9M)
TXCLAV
TXSOC
TXPRTY
TXENB_B
TXCLK
TXCLK_O
TXSEL_B
TXDATA[32]
CD
RXPLD[16]
RCLK_N/P
(155M)
VREF[3]
POH
TOH
POH
T
C
S (
77M)
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