Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- SYSTEM CONFIGURATION EXAMPLE
- BLOCK DIAGRAM
- PIN CONFIGURATION
- PIN CONFIGURATION (TOP VIEW)
- PIN ALLOCATION
- PIN NAMES
- 1. PIN FUNCTIONS
- 1.1 PMD Interface
- 1.2 ATM layer interface
- 1.3 Management interface
- 1.4 JTAG boundary scan
- 1.5 Internal test pins
- 1.6 Power and ground
- 1.7 Recommended connection of unused pins
- 2. ELECTRICAL CHARACTERISTICS
- 3. PACKAGE DRAWINGS
- 4. RECOMMENDED SOLDERING CONDITIONS
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MOS INTEGRATED CIRCUIT
PD98404
ADVANCED ATM SONET FRAMER
Document No. S11822EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
1997, 1999
DESCRIPTION
The
PD98404 NEASCOT-P30
TM
is an LSI for ATM applications, which can be used in ATM adapter boards for
connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI
provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the
ATM Forum's UNI3.1 recommendations.
This product's main functions include transmission functions such as mapping of ATM cells sent from the ATM
layer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media
Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM
cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition,
this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and
a clock synthesis function that generates a clock for transmissions.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
PD98404 User's Manual: S11821E
FEATURES
On-chip clock recovery/clock synthesis functions
Provides TC sub-layer function for the ATM protocol's physical layer
Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1
Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)
Supports three UTOPIA interfaces:
Single PHY octet-level handshaking
Single PHY cell-level handshaking
Multi PHY mode
Selectable to drop/bypass unassigned cells
On-chip internal loopback functions for PMD layer loopback and ATM layer loopback
Supports two PMD interfaces: serial and parallel
155.52 Mbps serial interface
19.44 MHz parallel interface
Provides registers for writing/reading overhead information
SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte
LOH (line overhead)
:K1 byte, K2 byte
POH (path overhead)
:F2 byte, C2 byte, H4 byte
Provides pseudo error frame transmit function for various errors
Supports JTAG boundary scan test function (IEEE 1149.1)
CMOS technology
+3.3 V single power supply
Data Sheet S11822EJ4V0DS00
2
PD98404
Provides abundant OAM (Operation and Maintenance) functions
Transmit side
Transmission of various alarm data
* Source-triggered automatic loopback transmission
Line RDI, Path RDI
Line REI, Path REI
* Command-specified transmission
Line AIS, Path AIS
Pseudo error generation frame transmit functions
LOS generated frame
OOF, LOF generated frame
LOP generated frame
OCD, LCD generated frame
B1 error generated frame
B2 error generated frame
B3 error generated frame
Receive side
Detection of alarm and fault signals
LOS (Loss Of Signal)
OOF (Out Of Frame)
LOF (Loss Of Frame)
LOP (Loss Of Pointer)
OCD (Out of Cell Delineation)
LOC (Loss Of Cell delineation)
Line RDI, Path RDI
Line AIS, Path AIS
Detection and display of quality loss sources
B1 error, B2 error, B3 error,
Line REI, Path-REI
On-chip error counters
B1 byte error counter (16-bit)
B2 byte error counter (20-bit)
B3 byte error counter (16-bit)
Line REI error counter (20-bit)
Path REI error counter (16-bit)
Rx Frequency justification processing counter (12-bit)
HEC error drop cell counter (20-bit)
FIFO overflow drop cell counter (20-bit)
Idle cell counter (20-bit)
ORDERING INFORMATION
Part number
Package
PD98404GJ-KEU
144-pin plastic QFP (fine pitch) (20
20 mm)
Data Sheet S11822EJ4V0DS00
3
PD98404
SYSTEM CONFIGURATION EXAMPLE
The following is an example of a system configuration using the
PD98404.
ATM adapter card application
Control
memory
SAR chip
PD98401A
NEASCOT-S15
TM
PHY chip
PD98404
NEASCOT-P30
Optical fiber
transceiver
/receiver
Oscillator
Bus bridge
Microprocessor
Hub (terminal side) application
Switch device
PD98412
NEASCOT-X15
TM
PD98404
NEASCOT-P30
Optical fiber
transceiver
/receiver
Oscillator
PD98404
NEASCOT-P30
Optical fiber
transceiver
/receiver
UTOPIA Level2
19.44 MHz
D
a
ta S
heet S
11822E
J4V
0
D
S
00
4
P
D
98404
BLOCK DIAGRAM
Clock recovery
& clock synthesizer
& PMD layer interface
Serial to
parallel
Parallel to
serial
Frame
synchro-
nization
(A1, A2)
Pointer processor
Descrambler
Cell
synchronization
HEC verification
HEC correction
+
Scrambler
+
Cell
scrambler
Cell
descrambler
HEC
generator
Rx FIFO,
7 cells
Tx FIFO,
7 cells
ATM layer interface
BIP generator
(transmit side)
Transmission overhead
processor
(A1, A2, K2, Z2,
G1, H1, H2, H3)
Reception overhead
processor
(K2, Z2, G1, H1, H2, H3)
Transmission
overhead registers
(J0, Z0, C2, K2,etc.)
BIP generator
(receive side)
Transmission
timing generator
OAM controller
(performance register, etc.)
Reception
overhead registers
(J0, Z0, C2, K2, etc.)
Interrupt source
register
Mode register
UTOPIA interface signal
Controller interface
Management interface signal
PMD interface signal
Data Sheet S11822EJ4V0DS00
5
PD98404
PIN CONFIGURATION
RDIT, RDIC
RCIT, RCIC
TDOT, TDOC
TCOT, TCOC
TFKT, TFKC
AIN1
REFCLK
PSEL0, PSEL1
Test interface
TEST0 - TEST2
Serial
RPD0 - RPD7
RPC
TPD0 - TPD7
TPC
TFC
PMDALM
PHYALM0 - PHYALM2
RxFP
TxFP
TFSS
RCL
TCL
PMD interface
2
3
8
8
Parallel
VDD, VDD-TPE, VDD-RPE
VDD-SP, VDD-CS, VDD-CR
GND, GND-TPE, GND-RPE
GND-SP, GND-CS, GND-CR
Power
supply, GND
8
5
8
5
7
8
RDO0 - RDO7
RCLK
RSOC
RENBL_B
EMPTY_B/RCLAV
RADD0-RADD4
TDI0 - TDI7
TCLK
TSOC
TENBL_B
FULL_B/TCLAV
TADD0 - TADD4
UMPSEL
MSEL
MADD0 - MADD6
MD0 - MD7
CS_B
DS_B/RD_B
R/W_B/WR_B
ACK_B/RDY_B
PHINT_B
RESET_B
ATM
layer interface
Management
interface
JRST_B
JMS
JCK
JDO
JDI
JTAG boundary scan interface
Remark
Active low pins are indicated with the suffix "_B" in this document.
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