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Электронный компонент: UPD9611

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MOS INTEGRATED CIRCUIT
PD9611
The information in this document is subject to change without notice.
Document No. S11018EJ2V0DS00 (2nd edition)
Date Published October 1996 P
Printed in Japan
The
PD9611 incorporates 4-channel A-law/
-law PCM CODECs compliant with ITU-T Recommendation G.711/
G.714 and is suitable for applications such as PBX analog subscriber line circuits.
Its gain setting circuit allows transmit/receive gain to be set for 4 channels independently by externally inputting
digital signals.
FEATURES
Single-chip CMOS monolithic LSI
ITU-T Recommendation G.711/G.714 compliant
Four-channel PCM CODECs integrated on a single chip
Compatible with A-law and
-law
Digital gain setting for each channel
Transmit : +7.5 to 8.0 dB (0.5 dB step)
Receive : 0 to 15.5 dB (0.5 dB step)
Data transfer system: Transmit/receive synchronization
Data rate: 2048 kHz
+5 V single power supply
Power down function for each channel
Low power consumption
ORDERING INFORMATION
Part Number
Package
PD9611GT
48-pin shrink SOP (375 mil)
FOUR-CHANNEL PCM CODEC
1996
PRELIMINARY DATA SHEET
PD9611
2
PIN CONFIGURATION (Top View)
48-pin shrink SOP (375 mil)
ACOM
IN
1-ACOM
IN
4
: Analog common voltage in
ACOM
OUT
1-ACOM
OUT
4 : Analog common voltage out
AGND1-AGND4
: Analog ground
A
IN
1-A
IN
4
: Analog signal in
A
OUT
1-A
OUT
4
: Analog signal out
AV
DD
1-AV
DD
4
: Analog power supply
DCLK
: Data clock in
DGND
: Digital ground
D
R
: Receive PCM data in
DV
DD
: Digital power supply
D
X
: Transmit PCM data out
FSC
: Frame synchronous clock in
LAW
: A-law/
-law control in
NC
: No connection
PD1-PD4 : Power down control
RST
: Reset in
SP
CLK
: Serial port data clock in
SP
DATA
: Serial port data in
SP
SYNC
: Serial port synchronous clock in
SUBGND : Sub ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
IN
1
A
OUT
1
NC
A
IN
2
A
OUT
2
NC
ACOM
IN
1
ACOM
OUT
1
ACOM
IN
2
ACOM
OUT
2
AV
DD
1
AV
DD
2
AV
DD
3
AV
DD
4
DV
DD
NC
PD1
PD2
PD3
PD4
FSC
DCLK
D
X
D
R
A
IN
4
A
OUT
4
NC
A
IN
3
A
OUT
3
NC
ACOM
IN
3
ACOM
OUT
3
ACOM
IN
4
ACOM
OUT
4
AGND1
AGND2
AGND3
AGND4
SUBGND
DGND
NC
NC
NC
RST
LAW
SP
DATA
SP
SYNC
SP
CLK
PD9611GT
PD9611
3
BLOCK DIAGRAM
AV
DD
1
AV
DD
2
AV
DD
3
AV
DD
4
DV
DD
A
IN
1
A
OUT
1
A
IN
2
A
OUT
2
A
IN
3
A
OUT
3
A
IN
4
A
OUT
4
ACOM
IN
1
ACOM
IN
2
AGND1
CH3
CH4
FSC
DCLK
I/O
Linear
A,
DGS
MUX, DEMUX
Clock
Generator
Voltage
Reference
APD1
APD2
D
X
D
R
RST
SP
SYNC
SP
CLK
SP
DATA
LAW
PD1
PD2
PD3
PD4
DSP
Channel FiIter
CH2
ACOM
IN
3
APD3
ACOM
IN
4
APD4
APD1
APD2
APD3
APD4
ACOM
IN
1
ACOM
OUT
1
ACOM
IN
2
ACOM
OUT
2
ACOM
IN
3
ACOM
OUT
3
ACOM
IN
4
ACOM
OUT
4
AGND2
AGND3
AGND4
DGND
SUBGND
CH1
A/D
D/A
PD9611
4
1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Name and Function
1
A
IN
1
I
Transmit analog input pin for channel 1
When not used, connect to ACOM
OUT
1 pin.
2
A
OUT
1
O
Receive analog output pin for channel 1
3
NC
Leave this pin open.
4
A
IN
2
I
Receive analog input pin for channel 2
When not used, connect to ACOM
OUT
1 pin.
5
A
OUT
2
O
Transmit analog output pin for channel 2
6
NC
Leave this pin open.
7
ACOM
IN
1
I
Signal reference voltage input for channel 1
8
ACOM
OUT
1
O
Signal reference voltage output for channel 1
9
ACOM
IN
2
I
Signal reference voltage input for channel 2
10
ACOM
OUT
2
O
Signal reference voltage output for channel 2
11
AV
DD
1
Analog power supply pin for channel 1
+5
0.25 V
12
AV
DD
2
Analog power supply pin for channel 2
+5
0.25 V
13
AV
DD
3
Analog power supply pin for channel 3
+5
0.25 V
14
AV
DD
4
Analog power supply pin for channel 4
+5
0.25 V
15
DV
DD
Digital power supply pin
+5
0.25 V
16
NC
Leave this pin open.
17
PD1
I
Power-down control input pin for channel 1
Channel 1 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 1 becomes high-impedance and A
OUT
1 becomes
signal reference voltage in the power-down mode.
18
PD2
I
Power-down control input pin for channel 2
Channel 2 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 2 becomes high-impedance and A
OUT
2 becomes
signal reference voltage in the power-down mode.
19
PD3
I
Power-down control input pin for channel 3
Channel 3 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 3 becomes high-impedance and A
OUT
3 becomes
signal reference voltage in the power-down mode.
20
PD4
I
Power-down control input pin for channel 4
Channel 4 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 4 becomes high-impedance and A
OUT
4 becomes
signal reference voltage in the power-down mode.
21
FSC
I
Frame synchronous clock input pin (8 kHz)
22
DCLK
I
Data clock input pin (2048 kHz)
23
D
X
O
Transmit PCM data output pin
This pin outputs PCM data for channel 1 to 4 in synchronization with rising edges
of DCLK after rising edges of FSC. It becomes high-impedance for other timings.
24
D
R
I
Receive PCM data input pin
This pin inputs PCM data for channel 1 to 4 in synchronization with falling edges of
DCLK after rising edges of FSC.
25
SP
CLK
I
Setting data clock input pin
26
SP
SYNC
I
Setting synchronous clock input pin
27
SP
DATA
I
Setting data input pin
PD9611
5
Pin No.
Symbol
I/O
Name and Function
28
LAW
I
A-law/
-law select pin in common to four channels
L: A-law, H:
-law
29
RST
Reset input, power-on reset pin
H: normal operation
L : internal registers are in the default status.
30-32
NC
Leave this pin open.
33
DGND
Digital ground pin
34
SUBGND
Substrate ground pin
35
AGND4
Analog ground pin for channel 4
36
AGND3
Analog ground pin for channel 3
37
AGND2
Analog ground pin for channel 2
38
AGND1
Analog ground pin for channel 1
39
ACOM
OUT
4
O
Signal reference voltage output for channel 4
40
ACOM
IN
4
I
Signal reference voltage input for channel 4
41
ACOM
OUT
3
O
Signal reference voltage output for channel 3
42
ACOM
IN
3
I
Signal reference voltage input for channel 3
43
NC
Leave this pin open.
44
A
OUT
3
O
Receive analog output pin for channel 3
45
A
IN
3
I
Transmit analog input pin for channel 3
When not used, connect to ACOM
OUT
1 pin.
46
NC
Leave this pin open.
47
A
OUT
4
O
Receive analog output pin for channel 4
48
A
IN
4
I
Transmit analog input pin for channel 4
When not used, connect to ACOM
OUT
1 pin.
PD9611
6
2. CAUTIONS ON USE
(1) Absolute maximum ratings
Application of voltage or current in excess of the absolute maximum ratings to the
PD9611 may result
in damage due to latch up, etc. Be especially cautions about power supply noise, etc.
(2) Wiring pattern
The design of the ground pattern is extremely important for operating the
PD9611 with high precision.
Connect the analog ground pins (AGND1 to AGND4), digital ground pin (DGND) and substrate ground
pin (SUBGND) close to the IC pins, and connect to a wide analog ground line on the board.
(3) Addition of bypass capacitors for power supply pins
Because the
PD9611 uses many internal high-frequency operational amplifiers, high power supply
impedance can cause instability (such as oscillation) in these internal operational amplifiers. To
suppress such instability and eliminate power supply noise, connect all power supply pins (AV
DD
1 to
AV
DD
4, DV
DD
) close to the IC pins, and put bypass capacitors (C
VDD
= approximately 0.1
F) having
superior high-frequency characteristics very close to the pins.
(4) Addition of bypass capacitors for ACOM pins
The
PD9611 incorporates references voltages for signal sources. Superposing of noise on these
reference voltages may have adverse effects on transmission characteristics, etc. Therefore, connect
the ACOM
OUT
pin and ACOM
IN
pin close to the IC pins, and put bypass capacitors (C
ACOM
= approximately
0.1
F) having superior high-frequency characteristics very close to the pins.
(5) Control or SP
DATA
pin on reset
When inputting the setting data from the SP
DATA
pin after the
PD9611 is reset, first input the following
patterns to reset to 0 the couter used to fetch data from the SP
DATA
pin.
16 clocks or more
1 clocks or more
RST
SP
CLK
SP
SYNC
SP
DATA
After ther RST pin has been set to the high level, input 1 clock or more to the SP
CLK
pin, set the SP
SYNC
pin to the high level and input 16 clocks more to the SP
CLK
pin.
During this operation, the SP
DATA
pin is held at the low level. Afterwards, input the setting data.
PD9611
7
3. GENERAL OPERATION
(1) PCM data transfer
In the transmit section, if FSC pin is set to the high level in synchronization with the rising edge (
) of
the data clock applied to the DCLK pin, the D
X
pin becomes active and sign bit data (MSB) of channel
1 is output. The following data of 7 bits is clocked out in synchronization with the rising edge (
) of each
data clock. Sign bit data (MSB) of channel 2 is output in synchronization with the rising edge (
) of the
9th data clock. In the same manner, each data up to channel 4 is output and the rising edge (
) of the
33rd data clock then sets the D
X
pin to high-impedance state.
Similarly, in the receive section, if the FSC pin is set to the high level in synchronization with the rising
edge (
) of the data clock applied to the DCLK pin, data of D
R
pin is latched by the falling edges (
) of
the data clock and consecutively clocked in.
(2) Power down control
The
PD9611 has the following two methods for power down control and is able to control power-down
independently for each channel.
Sets pins PD1 to PD4 to high or low level.
Inputs 8-bit setting data from SP
DATA
pin (see (5) Control of SP
DATA
pin).
Internal data is the logical sum of PD1 to PD4 pin state and 8-bit setting data input.
If the internal data is 0, the channel enters the power-down state. If the internal data is 1, the channel
enters the power-up state. In the power down state, PCM data in the channel goes to high-impedance
state and analog output becomes the signal reference voltage level.
8-Bit Setting Data
PD1 Pin
Internal Data
(Channel 1)
0
0
0
1
0
1
0
1
1
1
1
1
Remarks 1. 0: Power down, 1: Power up
2. The settings are the same for channel 2 to channel 4.
PD9611
8
(3) A-law/
-law control
The
PD9611 has the following two methods for A-law/
-law control.
Sets LAW pin to high or low level.
Inputs 8-bit setting data from SP
DATA
pin (see (5) Control of SP
DATA
pin).
Internal data is the logical sum of LAW pin state and 8-bit setting data input.
If the internal data is 0, the
PD9611 enters A-law mode. If the internal data is 1, the
PD9611 enters
-law mode.
8-Bit Setting Data
LAW Pin
Internal Data
0
0
0
1
0
1
0
1
1
1
1
1
Remark
0: A-law, 1:
-law
(4) Gain Setting control for transmit/receive
The
PD9611 can control gain settings independently for the transmit/receive by inputting 8-bit setting
data (see (5) Control of SP
DATA
pin) from the SP
DATA
pin for four channels. Gain can be set from +7.5
to 8.0 dB for the transmit and +0.0 dB t o 15.5 dB for the receive in 0.5 dB steps.
8-bit setting data input from SP
DATA
pin specifies the channel set in the first 8 bits, and performs selection
of transmit/receive and gain setting in the second 8 bits.
PD9611
9
(5) Control of SP
DATA
pin
If SP
SYNC
pin is set to the high level in synchronization with the rising edge (
) of the data clock applied
to the SP
CLK
pin, data of the SP
DATA
pin is latched by the falling edge (
) of the data clock and
consecutively fetched in.
After the 8-bit data has been fetched, the setting operation is performed according to the data.
This setting operation is performed during the 8 clocks after fetching the data and the next data is valid
at the 17th clock.
Therefore, when setting 1 word (8 bits) of data, input 17 clocks or more to the SP
CLK
pin.
Ensure that 17 clocks or more are input to the SP
CLK
pin between the rising of SP
SYNC
and the rising of
the next SP
SYNC
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SP
SYNC
SP
CLK
SP
DATA
Setting
completed
(The next
data is valid.)
Setting operation
Data fetch
Don't care
17 clocks or more
SP
SYNC
SP
CLK
PD9611
10
A/
-law, power down control
Notes 1.
Default setting is power down mode.
2.
Default setting is A-law mode.
Transmit/receive gain setting control (1st word)
D7
0
D6
1
D5
D4
D3
ch1
D2
ch2
D1
ch3
D0
ch4
0/1 Gain non-setting/setting for channel 4
0/1 Gain non-setting/setting for channel 3
0/1 Gain non-setting/setting for channel 2
0/1 Gain non-setting/setting for channel 1
Don
'
t care
Don
'
t care
1 Identification code
0 Identification code
Transmit/receive gain setting control (2nd word)
D7
1
D6
1
D5
X/R
D4
D3
D1
D0
0/1 Gain setting
0/1 Gain setting
0/1 Gain setting
0/1 Gain setting
0/1 Gain setting
0/1 Transmit/receive setting
1 Identification code
1 Identification code
D2
Setting data
D7
1
D6
0
D5
D4
A/
D3
PD1
D2
PD2
D1
PD3
D0
PD4
0/1 Power down/power up for channel 4
Note 1
0/1 Power down/power up for channel 3
Note 1
0/1 Power down/power up for channel 2
Note 1
0/1 Power down/power up for channel 1
Note 1
0/1 Setting of A-law/ -law
Note 2
Don
'
t care
0 Identification code
1 Identification code
PD9611
11
Table of Gain Setting Codes
(1/2)
Setting Item
Setting
1st Word
2nd Word
Level
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Gain setting for transmit
+7.5 dB
0
1
ch1 ch2 ch3 ch4
1
1
0
1
0
0
0
0
+7.0 dB
1
1
0
1
0
0
0
1
+6.5 dB
1
1
0
1
0
0
1
0
+6.0 dB
1
1
0
1
0
0
1
1
+5.5 dB
1
1
0
1
0
1
0
0
+5.0 dB
1
1
0
1
0
1
0
1
+4.5 dB
1
1
0
1
0
1
1
0
+4.0 dB
1
1
0
1
0
1
1
1
+3.5 dB
1
1
0
1
1
0
0
0
+3.0 dB
1
1
0
1
1
0
0
1
+2.5 dB
1
1
0
1
1
0
1
0
+2.0 dB
1
1
0
1
1
0
1
1
+1.5 dB
1
1
0
1
1
1
0
0
+1.0 dB
1
1
0
1
1
1
0
1
+0.5 dB
1
1
0
1
1
1
1
0
0.0 dB
Note
1
1
0
1
1
1
1
1
0.5 dB
1
1
0
0
0
0
0
0
1.0 dB
1
1
0
0
0
0
0
1
1.5 dB
1
1
0
0
0
0
1
0
2.0 dB
1
1
0
0
0
0
1
1
2.5 dB
1
1
0
0
0
1
0
0
3.0 dB
1
1
0
0
0
1
0
1
3.5 dB
1
1
0
0
0
1
1
0
4.0 dB
1
1
0
0
0
1
1
1
4.5 dB
1
1
0
0
1
0
0
0
5.0 dB
1
1
0
0
1
0
0
1
5.5 dB
1
1
0
0
1
0
1
0
6.0 dB
1
1
0
0
1
0
1
1
6.5 dB
1
1
0
0
1
1
0
0
7.0 dB
1
1
0
0
1
1
0
1
7.5 dB
1
1
0
0
1
1
1
0
8.0 dB
1
1
0
0
1
1
1
1
Note Default setting
PD9611
12
(2/2)
Setting Item
Setting
1st Word
2nd Word
Level
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Gain setting for receive
0.0 dB
Note
0
1
ch1 ch2 ch3 ch4
1
1
1
1
1
1
1
1
0.5 dB
1
1
1
1
1
1
1
0
1.0 dB
1
1
1
1
1
1
0
1
1.5 dB
1
1
1
1
1
1
0
0
2.0 dB
1
1
1
1
1
0
1
1
2.5 dB
1
1
1
1
1
0
1
0
3.0 dB
1
1
1
1
1
0
0
1
3.5 dB
1
1
1
1
1
0
0
0
4.0 dB
1
1
1
1
0
1
1
1
4.5 dB
1
1
1
1
0
1
1
0
5.0 dB
1
1
1
1
0
1
0
1
5.5 dB
1
1
1
1
0
1
0
0
6.0 dB
1
1
1
1
0
0
1
1
6.5 dB
1
1
1
1
0
0
1
0
7.0 dB
1
1
1
1
0
0
0
1
7.5 dB
1
1
1
1
0
0
0
0
8.0 dB
1
1
1
0
1
1
1
1
8.5 dB
1
1
1
0
1
1
1
0
9.0 dB
1
1
1
0
1
1
0
1
9.5 dB
1
1
1
0
1
1
0
0
10.0 dB
1
1
1
0
1
0
1
1
10.5 dB
1
1
1
0
1
0
1
0
11.0 dB
1
1
1
0
1
0
0
1
11.5 dB
1
1
1
0
1
0
0
0
12.0 dB
1
1
1
0
0
1
1
1
12.5 dB
1
1
1
0
0
1
1
0
13.0 dB
1
1
1
0
0
1
0
1
13.5 dB
1
1
1
0
0
1
0
0
14.0 dB
1
1
1
0
0
0
1
1
14.5 dB
1
1
1
0
0
0
1
0
15.0 dB
1
1
1
0
0
0
0
1
15.5 dB
1
1
1
0
0
0
0
0
Note
Default setting
PD9611
13
Gain setting control is set by inputting 8-bit data fo the 1st word first and inputting 8-bit data of the 2nd
word in synchronization with the next rising edge of SP
SYNC
. However, if data other than the identification
code of the 2nd word is input after the input of the 1st word, the contents of the 1st word are ignored.
(i)
When gain setting control is valid
Remark Because A/
-law, power down control is input after input of gain setting control (1st word),
gain setting control (1st word) becomes invalid and gain setting control (2nd word) also
becomes invalid.
(iii) When gain setting control is invalid 2
Remark Because gain setting control (2nd word) is input before gain setting control (1st word), gain
setting control (1st word) becomes invalid. Then, because A/
-law, power down control
is input even if gain setting control (1st word) is input, gain setting control (1st word)
becomes invalid.
(ii) When gain setting control is invalid 1
SP
CLK
SP
SYNC
SP
DATA
0 1 0 0 1 1 1 1
1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1
A/ -law, power down control
(valid)
Gain setting control (1st word)
(valid)
Gain setting control (2nd word)
(valid)
SP
CLK
SP
SYNC
SP
DATA
1 0 0 0 1 1 1 1
1 1 0 1 1 1 1 1
0 1 0 0 1 1 1 1
A/ -law, power down control
(valid)
Gain setting control (2nd word)
(invalid)
Gain setting control (1st word)
(invalid)
SP
CLK
SP
SYNC
SP
DATA
0 1 0 0 1 1 1 1
1 0 0 0 1 1 1 1
1 1 0 1 1 1 1 1
Gain setting control (1st word)
(invalid)
A/ -law, power down control
(valid)
Gain setting control (2nd word)
(invalid)
PD9611
14
4. ELECTRICAL SPECIFICATIONS (PRELIMINARY)
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
C)
Item
Symbol
Condition
Rating
Unit
Supply voltage
V
DD
AV
DD
1, AV
DD
2, AV
DD
3, AV
DD
4, DV
DD
0.3 to +7.0
V
Analog input voltage
V
AIN
A
IN
1, A
IN
2, A
IN
3, A
IN
4, ACOM
IN
1,
0.3 to V
DD
+0.3
ACOM
IN
2, ACOM
IN
3, ACOM
IN
4
Digital input voltage
V
DIN
D
R
, DCLR, FSC, LAW, PD1, PD2, PD3,
0.3 to V
DD
+0.3
PD4, SP
CLK
, SP
SYNC
, SP
DATA
, RST
Voltage applied to analog output
V
AOUT
A
OUT
1, A
OUT
2, A
OUT
3, A
OUT
4, ACOM
OUT
1,
0.3 to V
DD
+0.3
pin
ACOM
OUT
2, ACOM
OUT
3, ACOM
OUT
4
Voltage applied to digital output pin
V
DOUT
D
X
0.3 to V
DD
+0.3
Power dissipation
P
T
500
mW
Ambient operating temperature
T
A
20 to +85
C
Storage temperature
T
stg
65 to +150
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single
parameter or even momentarily. That is, the absolute maximum ratings are rated values at
which the product is on the verge of suffering physical damage, and therefore the product must
be used under conditions which ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATION CONDITIONS (T
A
= 20 to +85
C, V
DD
= 5 V
5 %, GND = 0 V, f
DCLK
= 2048 kHz)
(1) DC condition
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Ambient operating temperature
T
A
20
+25
+85
C
Supply voltage
V
DD
AV
DD
1, AV
DD
2, AV
DD
3, AV
DD
4, DV
DD
4.75
5.0
5.25
V
Analog input voltage
V
AI
A
IN
1, A
IN
2, A
IN
3, A
IN
4 (ACOM as reference)
1.0
+1.0
Analog output load resistance
R
LOAD
A
OUT
1, A
OUT
2, A
OUT
3, A
OUT
4
50
k
Analog output load capacitance
C
LOAD
50
pF
High level input voltage
V
IH1
D
R
, DCLK, FSC, LAW, PD1, PD2, PD3,
2.0
V
DD
V
PD4, SP
CLK
, SP
SYNC
, SP
DATA
V
IH2
RST
0.8
V
DD
V
DD
Low level input voltage
V
IL1
D
R
, DCLK, FSC, LAW, PD1, PD2, PD3,
0
0.8
PD4, SP
CLK
, SP
SYNC
, SP
DATA
V
IL2
RST
0
0.2
V
DD
PD9611
15
(2) AC condition
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Data clock frequency
f
CLK
(= 1/t
CY
)
50 ppm
2048
kHz
Data clock pulse width
t
CLK
200
ns
Frame synchronous clock frequency
fs
50 ppm
8.0
kHz
High level frame synchronous
t
WHS
200
ns
pulse width
Low level frame synchronous
t
WLS
8
s
pulse width
Clock rise time
t
R
50
ns
Clock fall time
t
F
50
ns
Float in synchronous timing
t
CSD1
100
ns
t
CSD2
40
ns
Frame synchronous clock and
t
WHSC
100
ns
data clock high level width
D
R
setup time
t
DSR
Note
65
ns
D
R
hold time
t
DHR
Note
120
ns
SP
DATA
clock frequency
f
SPCLK
2048
kHz
SP
DATA
setup time
t
GSR
Note
100
ns
SP
DATA
hold time
t
GHR
Note
100
ns
Float in SP synchronous timing
t
FSD
40
ns
Note
Set the rise time and fall time of the digital input waveform and clock signal used for measuring timings
to 5 ns.
PD9611
16
DC CHARACTERISTICS
(T
A
= 20 to +85
C, V
DD
= 5
0.25 V, GND = 0 V, f
DCLK
= 2048 kHz, and all output pins are unloaded.)
(1) Power consumption
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Circuit current
I
DD
All channels in normal operation
23
30
mA
Power-down circuit current
I
DDPD
All channels in power-down mode
5
6
(2) Digital interface
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Digital input current
I
ID
D
R
, DCLK, FSC, LAW, PD1, PD2, PD3,
10
+10
A
PD4, SP
CLK
, SP
SYNC
, SP
DATA
, RST
Each pin 0
V
DIN
V
DD
3-state leakage current
I
L
D
X
pin 0
V
DIN
V
DD
10
+10
High level output voltage
V
OH
D
X
pin I
OH
= 150
A
V
DD
0.3
V
Low level output voltage
V
OL
D
X
pin I
OL
= 0.8 mA
0.4
Digital output pin output capacitance
C
OD
f = 1 MHz, 0 V other than unmeasured pins
15
pF
Digital input pin input capacitance
C
ID
f = 1 MHz, 0 V other than unmeasured pins
10
(3) Transmit amplifier (A
IN
1, A
IN
2, A
IN
3, A
IN
4 pins)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input bias current
I
B
10
+10
A
Input resistance
R
IN
1
M
Input capacitance
C
IN
10
pF
(4) Receive power amplifier (A
OUT
1, A
OUT
2, A
OUT
3, A
OUT
4 pins)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Output offset voltage
V
OA
D
R
= +0 code
50
+50
mV
ACOM as reference
Maximum output voltage
V
OM
ACOM as reference
1.02
+1.02
V
Output resistance
R
OUT
1
(5) Signal reference voltage output (ACOM
OUT
1, ACOM
OUT
2, ACOM
OUT
3, ACOM
OUT
4 pins)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Output voltage
V
ACOM
2.35
2.4
2.45
V
PD9611
17
AC CHARACTERISTICS (T
A
= 20 to +85
C, V
DD
= 5
0.25 V, GND = 0 V, f
DCLK
= 2048 kHz)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Data enable delay time
t
DZX1
D
X
when FSC is behind DCLK
100
ns
t
DZX2
D
X
when FSC is ahead of DCLK
100
ns
Data delay time
t
DDX
D
X
pin
100
ns
Data hold time
t
HZX
D
X
pin
25
ns
PD9611
18
TIMING CHARTS
(1) Transmit timing
(a) When FSC is ahead of DCLK
FSC
DCLK
MSB
D
X
LSB
7th
2nd
Hi-Z
Hi-Z
1
2
8
t
R
t
WHS
t
F
t
WLS
t
WHSC
t
CSD2
t
CY
t
R
t
CLK
t
F
t
CLK
t
DZX2
t
DDX
t
HZX
(b) When FSC is behind DCLK
FSC
DCLK
MSB
D
X
LSB
7th
2nd
Hi-Z
Hi-Z
1
2
8
t
CSD1
t
DZX1
t
WHSC
PD9611
19
(2) Receive timing
(a) When FSC is ahead of DCLK
(b) When FSC is behind DCLK
FSC
DCLK
t
CSD1
t
WHSC
FSC
DCLK
MSB
D
R
7th
2nd
1
2
8
9
t
R
t
WHS
t
F
t
WLS
t
WHSC
t
CSD2
t
CY
t
R
t
CLK
t
F
t
DSR
t
DHR
Don
'
t
care
8th
Don
'
t
care
Don
'
t
care
t
R
, t
F
t
CLK
t
R
, t
F
PD9611
20
(3) Gain setting timing
Remark The relationship between SP
SYNC
and SP
CLK
is the same as in the receive timing.
D
X
output measuring circuit
Timing test waveform
D7
D6
D5
D1
Don
'
t
care
Don
'
t
care
Don
'
t
care
Don
'
t
care
Don
'
t
care
D0
Don
'
t care
1
2
3
8
9
SP
SYNC
SP
CLK
SP
DATA
t
GSR
t
FSD
t
GHR
(4) Transmit, receive PCM data input/output timing charts
2.0 V
0.8 V
2.0 V
0.8 V
Test
points
All inputs/outputs other than D
X
pin
2.4 V
0.4 V
2.4 V
0.4 V
Test
points
D
X
pin output
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
D4 D3 D2 D1 D0
D7 D6 D5 D4
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
D4 D3 D2 D1 D0
D7 D6 D5 D4
1
2
3
4
5
6
7
8
9 10 11 12 13
28 29 30 31 32 33
256 1
2
3
4
DCLK
(2.048 MHz)
FSC
(8.0 kHz)
D
X
D
R
MSB
MSB
MSB
MSB
SB
MSB
LSB
LSB
LSB
LSB
Channel 1 data
Channel 1 data
Channel 2 data
Channel 2 data
Channel 1 data
Channel 1 data
Channel 4 data
Channel 4 data
Hi-Z
Hi-Z
Don
'
t care
Don
'
t care
V
DD
2 k
Output
165 pF
D
X
PD9611
21
(5) Setting data input timing
SP
SYNC
SP
CLK
Don't care
Setting data
Don't care
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
SP
DATA
D7 D6 D5 D4
MSB
Setting data
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
1
2
3
4
PD9611
22
TRANSMISSION CHARACTERISTICS (T
A
= 20 to +85
C, V
DD
= 5
0.25 V, GND = 0 V, f
DCLK
= 2048 kHz)
Item
Symbol
Condition
Setting Value
Unit
Zero transmission level point (transmit)
OTLP
X
Referenced to 600
3.8
dBm
Zero transmission level point (receive)
OTLP
X
Referenced to 600
3.8
dBm
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Insertion loss
IL
A/D input signal
0.3
+0.3
dB
0 dBm0 1 kHz
D/A input signal
0.3
+0.3
0 dBm0 1 kHz
Transmission loss frequency
F
RX
A/D
60 Hz
24.0
dB
characteristics
Reference input signal
200 Hz
0
2.0
1015 Hz 0 dBm0
300 to 3000 Hz
0.15
+0.15
3200 Hz
0.15
+0.65
3400 Hz
0
0.8
3780 Hz
+6.5
F
RR
D/A
0 to 3000 Hz
0.15
+0.15
Reference input signal
3200 Hz
0.15
+0.65
1015 Hz 0 dBm0
3400 Hz
0
+0.8
3780 Hz
+6.5
Gain tracking (tone method)
GT
X
A/D
+3 to 40 dBm0
0.2
+0.2
dB
Reference input signal
50 dBm0
0.5
+0.5
10 dBm0
55 dBm0
1.0
+1.0
f = 700 to 1100 Hz
GT
R
D/A
+3 to 40 dBm0
0.2
+0.2
Reference input signal
50 dBm0
0.5
+0.5
10 dBm0
55 dBm0
1.0
+1.0
f = 700 to 1100 Hz
Transmit/receive channel
SD
X
A/D
+3 to 30 dBm0
36
dB
overall power distortion ratio
Input signal
40 dBm0
30
(tone method)
f = 700 to 1100 Hz
45 dBm0
25
SD
R
D/A
+3 to 30 dBm0
36
Input signal
40 dBm0
30
f = 700 to 1100 Hz
45 dBm0
25
Absolute delay characteristic
D
A
A/A
540
s
Input signal = 0 dBm0
Absolute delay distortion
D
O
A/A
500 Hz
1400
s
frequency characteristics
600 Hz
700
1000 to 2600 Hz
200
2800 Hz
1400
Idle channel noise
ICN
ADA
A/D A-law Psophometric weighted
72
dBm0p
ICN
DAA
D/A A-law Psophometric weighted
80
ICN
AD
A/D
-law C-message weighted
18
dBrnc0
ICN
DA
D/A
-law C-message weighted
10
PD9611
23
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Cross talk between channels
CT
A/A
70
dB
Input signal = 0 dBm0
Power supply rejection ratio
PSRR
AV
DD
1, AV
DD
2, AV
DD
3, AV
DD
4,
25
dB
DV
DD
= 5 V
100 mV
P-P
Coder offset
A/D
5
+5
Input signal 0 V
Mutual modulation (2 tones)
IMD
A/D
44.0
dB
Input signal:
f1, f2; 300 to 3400 Hz, 4 to 21 dBm0
Measuring signal: 2
f1 f2
level (2
f1 f2) vs level (f1, f2)
D/A
44.0
dB
Input signal:
f1, f2; 300 to 3400Hz, 4 to 21 dBm0
Measuring signal: 2
f1 f2
level (2
f1 f2) vs level (f1, f2)
Discrimination
A/D
27
dB
Input signal:
f; 4396 to 7796 Hz
0 dBm0
Measuring signal: 8000 fHz
Out-of-band spurious
D/A
27
dB
Input signal:
f; 204 to 3604 Hz
0 dBm0
Measuring signal: 8000 fHz
In-band spurious
A/D
45
dB
Input signal:
f; 700 to 1100 Hz
0 dBm0
Measuring signal: Any frequency
D/A
45
dB
Input signal:
f; 700 to 1100 Hz
0 dBm0
Measuring signal: Any frequency
Single frequency noise
N
SF
D/A
54
dBm0
Gain setting = 0 dB
Measuring signal: f = up to 256 kHz
Transmit gain setting
DGS
X
A/D difference from reference setting value
0.15
+0.15
dB
Receive gain setting
DGS
R
D/A difference from reference setting value
0.15
+0.15
PD9611
24
5. APPLICATION CIRCUIT EXAMPLE
AV
DD
1
AV
DD
2
AV
DD
3
AV
DD
4
DV
DD
A
IN
1
A
OUT
1
A
IN
2
A
OUT
2
A
IN
3
A
OUT
3
A
IN
4
A
OUT
4
ACOM
IN
1
ACOM
IN
2
AGND1
CH1
CH4
A/D
I/O
Linear
A,
DGS
MUX, DEMUX
APD1
APD2
D
X
D
R
RST
SP
SYNC
SP
CLK
SP
DATA
LAW
PD1
PD2
PD3
PD4
DSP
Channel FiIter
ACOM
IN
3
APD3
ACOM
IN
4
APD4
APD1
APD2
APD3
APD4
ACOM
IN
1
ACOM
OUT
1
ACOM
IN
2
ACOM
OUT
2
ACOM
IN
3
ACOM
OUT
3
ACOM
IN
4
ACOM
OUT
4
AGND2
AGND3
AGND4
DGND
SUBGND
V
DD
0.1 F
100 k
ACOM
OUT
1
CH3
D/A
PD1
PD2
PD3
PD4
LAW
SP
DATA
D
X
D
R
RST
FSC
DCLK
Clock
Generator
SP
SYNC
SP
CLK
FSC
DCLK
0.1 F
0.1 F
0.1 F
0.1 F
Voltage
Reference
V
DD
2 k
0.1 F
ACOM
OUT
1
ACOM
OUT
1
0.1 F
CH2
100 k
ACOM
IN
1
PD9611
25
6. PACKAGE DRAWINGS
48 PIN PLASTIC SHRINK SOP (375 mil)
C
B
D
E
F
G
A
1
24
48
25
L
I
H
J
K
detail of lead end
3
M
M
N
+7 3
P48GT-65-375B-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
16.21 MAX.
0.65 (T.P.)
2.0 MAX.
1.70.1
10.00.3
0.63 MAX.
0.639 MAX.
0.0050.003
0.079 MAX.
0.394
0.3150.008
0.025 MAX.
NOTE
L
M
0.50.2
0.15
1.00.2
8.00.2
0.004
0.020
+0.008
0.009
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
0.0670.004
0.026 (T.P.)
0.006
N
0.10
0.004
0.012
0.300.10
0.1250.075
+0.004
0.002
0.10
+0.10
0.05
+0.004
0.005
+0.012
0.013
0.039
+0.009
0.008
PD9611
26
7. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.
SURFACE MOUNT TYPE
PD9611GT: 48-pin shrink SOP (375 mil)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235
C
IR-35-103-2
Duration: 30 sec. max. (210
C or above)
Number of times: 2 max.
Time limit: 3 days
Note
(thereafter, 10-hour prebaking at 125
C required.)
<Cautions>
(1)
Wait for the device temperature to return to normal after the first reflow
before starting the second reflow.
(2)
Do not perform flux cleaning with water after the first reflow.
Pin heating
Pin temperature: 300
C max.
--
Duration: 3 sec. max. (per side of device)
Note
For the storage period after unpacking from the dry-pack, storage conditions are max. 25
C, 65 % RH.
PD9611
27
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD9611
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.