Document Outline
- Cover
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATIONS
- BLOCK DIAGRAM
- 1. PIN FUNCTIONS
- 1.1 Normal Operating Mode
- 1.2 PROM Programming Mode (RESET#= H, AVDD = L)
- 1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
- 2. DIFFERENCES BETWEEN uPD78P328 and uPD78328
- 3. PROM PROGRAMMING
- 3.1 Operation Mode
- 3.2 PROM Write Procedure
- 3.3 PROM Read Procedure
- 4. ERASURE CHARACTERISTICS (EPROM VERSION ONLY)
- 5. WINDOW SEAL (EPROM VERSION ONLY)
- 6. ONE-TIME PROM VERSION SCREENING
- 7. ELECTRICAL SPECIFICATIONS
- 8. PACKAGE DRAWINGS
- 9. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A. DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT
- APPENDIX B. TOOLS
- B.1 Development Tools
- B.2 Evaluation Tools
- B.3 Embedded Software
NEC Corporation 1990
DATA SHEET
MOS Integrated Circuit
16/8-BIT SINGLE-CHIP MICROCONTROLLER
Document No.
U10209EJ4V0DS00 (4th edition)
(Previous No.
IC-2486)
Date Published
October 1995 P
Printed in Japan
The
PD78P328 is a product provided by replacing the
PD75328's internal mask ROM with one-time
PROM or EPROM.
The one-time PROM version is programmable only once and is useful for small-lot production of many
different products and early development and time-to-market of application sets.
The EPROM version is reprogrammable, and suited for the evaluation of systems.
Functions are described in detail in the following user's manual. Be sure to read it before designing.
PD78328 User's Manual: IEU-1268
FEATURES
PD78328 compatible
For mass-production, the
PD78P328 can be replaced with the
PD78328 incorporating mask ROM
Internal PROM: 16,384 x 8 bits
Programmable once only (one-time PROM version without window)
Erasable with ultraviolet rays and electrically programmable (EPROM version with window)
PROM programming characteristics:
PD27C256A compatible
The
PD78P328 is a QTOP
TM
microcontroller.
Remark
QTOP microcontroller is a general term for microcontrollers which incorporates one-time PROM, and
are totally supported by NEC's programming service (from programming to marking, screening, and
verification).
ORDERING INFORMATION
Part Number
Package
Internal ROM
PD78P328CW
64-pin plastic shrink DIP (750 mils)
One-time PROM
PD78P328GF-3BE
64-pin plastic QFP (14 x 20 mm)
One-time PROM
PD78P328DW
64-pin ceramic shrink DIP (750 mils) (with window)
EPROM
Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document.
The information in this document is subject to change without notice.
The mark
*
shows revised points.
PD78P328
PD78P328
2
PIN CONFIGURATIONS
(1)
Normal operating mode
64-pin plastic shrink DIP (750 mils)
PD78P328CW
64-pin ceramic shrink DIP (750 mils) (with window)
PD78P328DW
Remark
These pins are compatible with the
PD78328CW pins.
P20/NM1
P21/INTP0
P22/INTP1
P30/TxD
P31/RxD
P32/SO/SB0
P33/SI/SB1
P34/SCK
P80/TO0
P81/TO1
P82/TO2
P83/TO3
P84/TO4
P85/TO5
P86/TO6/INTP2
P87/TO7/PWM
V
SS
X1
X2
RESET
P00/RTP0
P01/RTP1
P02/RTP2
P03/RTP3
P04/RTP4
P05/RTP5
P06/RTP6
P07/RTP7
EA
P93/TMD
P92/TAS
V
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
DD
AV
DD
AV
REF
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AV
SS
V
DD
P56/A14
P57/A15
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
ASTB
P90/RD
P91/WR
PD78P328
3
64-pin plastic QFP (14 x 20 mm)
PD78P328GF-3BE
Remark
These pins are compatible with the
PD78328GF pins.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P02/RTP2
P03/RTP3
P05/RTP5
P06/RTP6
P07/RTP7
P93/TMD
P92/TAS
V
SS
P91/WR
P90/RD
ASTB
P40/AD0
P41/AD1
P42/AD2
17
18
P04/RTP4
19
20 21 22 23 24 25 26 27 28 29 30 31 32
P33/SI/SB1
P34/SCK
P80/TO0
P81/TO1
P82/TO2
P83TO3
P84/TO4
P85/TO5
P86/TO6/INTP2
P87/TO7/PWM
V
SS
X1
X2
RESET
P00/RTP0
P01/RTP1
P70/ANI0
AV
SS
V
DD
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
64
6362 61 60 59 58 57 56 55 54 53 52
51
50
49
P32/SO/SB0
P31/RxD
P30/RxD
P22/INTP/TI
EA
P21/INTP0
P20/NMI
V
DD
AV
DD
AV
REF
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
PD78P328
4
P00-P07
: Port 0
SI
: Serial Input
P20-P22
: Port 2
SO
: Serial Output
P30-P34
: Port 3
SB0-SB1
: Serial Bus0-1
P40-P47
: Port 4
RD
: Read Strobe
P50-P57
: Port 5
WR
: Write Strobe
P70-P77
: Port 7
ASTB
: Address Strobe
P80-P87
: Port 8
EA
: External Access
P90-P93
: Port 9
RESET
: Reset
A8-A15
: Address8-15
SCK
: Serial Clock
AD0-AD7
: Address0-7/Data0-7
TAS
: Turbo Access Strobe
ANI0-ANI7
: Analog Input0-7
TMD
: Turbo Mode
TO0-TO7
: Timer Output0-7
X1, X2
: Crystal1, 2
NMI
: Nonmaskable Interrupt
AV
DD
: Analog V
DD
PWM
: Pulse Wide Modulation Output
AV
REF
: Analog Reference Voltage
INTP0-INTP2
: Interrupt From Peripherals0-2
AV
SS
: Analog V
SS
RTP0-RTP7
: Real-Time Port0-7
V
DD
: Power Supply
TxD
: Transmit Data
V
SS
: Ground
RxD
: Receive Data
PD78P328
5
(2)
PROM programming mode (RESET = H, AV
DD
= L)
64-pin plastic shrink DIP (750 mils)
PD78P328CW
64-pin ceramic shrink DIP (750 mils) (with window)
PD78P328DW
Caution The recommended connection of the unused pins in the PROM programming mode are indicated
in parentheses.
L
:
Connect each pin to V
SS
via a resistor.
G
:
Connect the pin to V
SS
.
Open :
Leave the pin unconnected.
A9
(G)
(L)
OE
CE
(L)
A8
A10
A11
A12
A13
A14
V
SS
(G)
(Open)
RESET
A0
A1
A2
A3
A4
A5
A6
A7
V
PP
V
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
DD
AV
DD
(G)
V
DD
D7
D6
D5
D4
D3
D2
D1
D0
(Open)
(L)
(L)
(L)
(L)
PD78P328
6
64-pin plastic QFP (14 x 20 mm)
PD78P328GF-3BE
Caution The recommended connection of the unused pins in the PROM programming mode are indicated
in parentheses.
L
:
Connect each pin to V
SS
via a resistor.
G
:
Connect the pin to V
SS
.
Open :
Leave the pin unconnected.
A0-A14
: Address0-14
AV
DD
: Analog V
DD
D0-D7
: Data0-7
V
DD
: Power Supply
CE
: Chip Enable
V
SS
: Ground
OE
: Output Enable
V
PP
: Programming Power Supply
RESET
: Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A2
A3
A5
A6
A7
(L)
V
SS
(Open)
D0
D1
D2
17
18
A4
19
20 21 22 23 24 25 26 27 28 29 30 31 32
CE
OE
(L)
(G)
A9
V
DD
AV
DD
(G)
(L)
A8
A10
A11
A12
A13
A14
(L)
V
SS
(G)
(Open)
RESET
A0
A1
V
DD
(L)
D7
D6
D5
D4
D3
64 63 62 61 60 59 58 57 56 55 54 53 52
51
50
49
V
PP
(G)
(L)
PD78P328
7
BLOCK DIAGRAM
Note During PROM programming mode
Programmable
Interrupt
Controller
Timer/Counter Unit
(Real-Time
Pulse Unit)
Serial Interface
(SBI)
(UART)
(P20) NMI
(P80) TO0
INTP0-INTP2
(P21, P22, P86)
(P83) TO3
(P81) TO1
(P82) TO2
(P85) TO5
(P84) TO4
(P86) TO6
(P87) TO7/PWM
(P22) TI/INTP1
(P34) SCK
(P32) SO/SB0
(P31) RxD
(P30) TxD
(P33) SI/SB1
General
Registers
128 x 8
&
Data
Memory
128 x 8
Micro Sequence
Control
Micro ROM
System
Control
&
Bus
Control
&
Prefetch
Control
PROM
16K x 8
&
Peripheral
RAM
256 X 8
ALU
Ports
WDT
A/D Converter
(10-bit)
V
DD
P00-P07
(Real-Time Port)
P20-P22
P30-P34
P40-P47
P50-P57
P70-P77
P80-P87
P90-P93
/
2
V
SS
/
2
AV
REF
AV
SS
AV
DD
INTP0
ANI0-ANI7
(P70-P77)
Main RAM
EXU
PROM/RAM
BCU
X1
X2
RESET
ASTB
RD (P90)
WR (P91)
TAS (P92)
TMD (P93)
A8-A15 (P50-P57)
AD0-AD7 (P40-P47)
A0-A14
D0-D7
CE
OE
EA/V
PP
Note
Note
PD78P328
8
CONTENTS
1.
PIN FUNCTIONS ... 9
1.1
Normal Operating Mode ... 9
1.2
PROM Programming Mode (RESET = H, AV
DD
= L) ... 11
1.3
Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 12
2.
DIFFERENCES BETWEEN
PD78P328 and
PD78328 ... 14
3.
PROM PROGRAMMING ... 15
3.1
Operation Mode ... 15
3.2
PROM Write Procedure ... 16
3.3
PROM Read Procedure ... 18
4.
ERASURE CHARACTERISTICS (EPROM VERSION ONLY) ... 19
5.
WINDOW SEAL (EPROM VERSION ONLY) ... 19
6.
ONE-TIME PROM VERSION SCREENING ... 19
7.
ELECTRICAL SPECIFICATIONS ... 20
8.
PACKAGE DRAWINGS ... 35
9.
RECOMMENDED SOLDERING CONDITIONS ... 37
APPENDIX A.
DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT... 38
APPENDIX B.
TOOLS ... 40
B.1
Development Tools ... 40
B.2
Evaluation Tools ... 43
B.3
Embedded Software ... 43
*
PD78P328
9
1.
PIN FUNCTIONS
1.1 Normal Operating Mode
(1)
Port Pins
Pin Name Input/Output
Function
Alternate
Function
P00-P07
Input/Output
PORT0
RTP0-RTP7
4-/8-bit input/output port
Input or output mode can be specified bit-wise.
The port can also operate as a real-time output port.
P20
Input
PORT 2
NMI
P21
3-bit input-only port
INTP0
P22
INTP1/TI
P30
Input/Output
PORT 3
TxD
P31
5-bit input/output port
RxD
P32
Input or output mode can be specified bit-wise.
SO/SB0
P33
SI/SB1
P34
SCK
P40-P47
Input/Output
PORT 4
AD0-AD7
8-bit input/output port
Input or output mode can be specified in 8-bit units.
P50-P57
Input/Output
PORT 5
A8-A15
8-bit input/output port
Input or output mode can be specified bit-wise.
P70-P77
Input
PORT 7
ANI0-ANI7
8-bit input-only port
P80
Input/Output
PORT 8
TO0
P81
8-bit input/output port
TO1
P82
Input or output mode can be specified bit-wise.
TO2
P83
TO3
P84
TO4
P85
TO5
P86
TO6/INTP2
P87
TO7/PWM
P90
Input/Output
PORT 9
RD
P91
4-bit input/output port
WR
P92
Input or output mode can be specified bit-wise.
TAS
P93
TMD
PD78P328
10
(2)
Non-Port Pins (1/2)
Pin Name
Input/Output
Function
Alternate
Function
RTP0-RTP7
Output
Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07
real-time pulse unit (RPU).
NMI
Input
Edge-detected nonmaskable interrupt request input.
P20
The rising or falling edge can be selected for the valid edge by setting the mode register.
INTP0
Input
Edge-detected external interrupt request input.
P21
INTP1
The valid edge can be specified in the mode register.
P22/T1
INTP2
P86/TO6
TI
Input
External count clock input pin to timer 1 (TM1).
S22/INTP1
RxD
Input
Serial data input pin to asynchronous serial interface (UART).
P30
TxD
Output
Serial data output pin from asynchronous serial interface (UART).
P31
SO
Output
Serial data output pin from clocked serial interface in 3-wire mode.
P32/SB0
SI
Input
Serial data input pin to clocked serial interface in 3-wire mode.
P33/SB1
SB0
Input/Output
Serial data input/output pins to/from clocked serial interface in SBI mode.
P32/SO
SB1
P33/SI
SCK
Input/Output
Serial clock input/output pin to/from clocked serial interface.
P34
AD0-AD7
Input/Output
Multiplexed address/data bus used when external memory is added.
P40-P47
A8-A15
Output
Address bus used when external memory is added.
P50-P57
TO0
Output
Pulse output from real-time pulse unit.
P80
TO1
P81
TO2
P82
TO3
P83
TO4
P84
TO5
P85
TO6
P86/INTP2
TO7
P87/PWM
PWM
Output
PWM signal output from real-time pulse unit.
P87/TO7
RD
Output
Strobe signal output for external memory read operation.
P90
WR
Strobe signal output for external memory write operation.
P91
TAS
Control signal output pins to access turbo access manager (
PD71P301).
Note
P92
TMD
P93
ASTB
Output
Timing signal output pin to externally latch an address information output to port 4 for
--
external memory access.
EA
Input
For
PD78P328, normally connect the EA pin to V
DD
. When the EA pin is connected to
--
V
SS
, the
PD78P328 enters the ROMless mode and external memory is accessed.
The EA pin level cannot be changed during operation.
Note
Turbo access manager (
PD71P301) is available for maintenance purposes only.
*
PD78P328
11
(2) Non-Port Pins (2/2)
Pin Name
Input/Output
Function
Alternate
Function
ANI0-ANI7
Input
Analog input to A/D converter.
P70-P77
AV
REF
Input
A/D converter reference voltage input.
--
AV
DD
--
A/D converter analog power supply.
--
AV
SS
--
A/D converter GND.
--
RESET
Input
System reset input.
--
X1
Input
Crystal connection pin for system clock generation. To supply external clock,
--
X2
--
input to the X1 and input reverse signal to the X2 pin (X2 pin can be unconnected.)
--
V
DD
--
Positive power supply pin.
--
V
SS
--
GND pin.
--
1.2 PROM Programming Mode (RESET = H, AV
DD
= L)
Pin Name Input/Output
Function
AV
DD
Input
PROM programming mode setting.
RESET
A0-A14
--
Address bus.
D0-D7
--
Data bus.
CE
Input
PROM enable to PROM.
OE
Input
Read strobe to PROM.
V
PP
--
Write power supply.
V
DD
Positive power supply.
V
SS
GND.
PD78P328
12
1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
Table 1-1 and Figure 1-1 show the pin input/output circuit schematically.
Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins
Pin
Input/Output
Recommended connection of unused pins
circuit type
P00P07/RTP0-RTP7
5
Input state: Independently connect to V
DD
or V
SS
via a resistor.
Output state: Leave Open.
P21/NMI
2
Connect to V
SS
.
P21/INTP0
P27/INTP6/TI
P30/TxD
5
Input state: Independently connect to V
DD
or V
SS
via a resistor.
P31/RxD
Output state: Leave Open.
P32/SO/SB0
8
P33/SI/SB1
P34/SCK
P40/AD0-P47/AD0-AD7
5
P50/P57/A8-A15
P70-P77/ANI0-ANI7
9
Connect to V
SS
.
P80-P85/TO0-TO5
5
Input state: Independently connect to V
DD
or V
SS
via a resistor.
P86/TO6/INTP2
6
Output state: Leave Open.
P87/TO7/PWM
5
P90/RD
5
P91/WR
P92/TAS
P93/TMD
ASTB
4
Leave Open.
EA
1
--
RESET
2
--
AV
REF
,
AV
SS
--
Connect to V
SS
.
V
DD
--
Connect to V
DD
.
PD78P328
13
Figure 1-1. Pin Input/Output Circuits
TYPE 1
TYPE 6
TYPE 2
IN
V
DD
V
DD
P-ch
N-ch
data
data
data input enable
control signal
output
disable
data
Comparator
output
disable
control input
enable
IN/OUT
P-ch
N-ch
IN
Schmitt-triggerred input with hysteresis characteristics
Push-pull output that can be placed in high impedance
(both P-ch and N-ch off).
TYPE 8
TYPE 4
TYPE 9
TYPE 5
P-ch
N-ch
IN
V
REF
(Threshold voltage)
+
input
enable
V
DD
IN/OUT
P-ch
N-ch
data
output
disable
V
DD
OUT
P-ch
N-ch
data
output
disable
input
disable
V
DD
IN/OUT
P-ch
N-ch
PD78P328
14
2.
DIFFERENCES BETWEEN
PD78P328 and
PD78328
The
PD78P328 is a product provided by replacing the
PD78328's on-chip mask ROM with one-time PROM
or EPROM. Thus, the
PD78P328 and
PD78328 are the same in function except for the ROM specifications such
as write or verify. Table 2-1 lists the differences between these two products.
This Data Sheet describes the PROM specification function. Refer to the
PD78328 documents for details of
other functions.
Table 2-1. Differences between
PD78P328 and
PD78328
Item
PD78P328
PD78328
Internal program memory
One-time PROM
EPROM
Mask ROM
(electrical program)
(programmable only once)
(reprogrammable)
(nonprogrammable)
PROM programming pin
Contained
Not contained
Package
64-pin plastic shrink DIP
64-pin ceramic shrink DIP
64-pin plastic shrink DIP
64-pin plastic QFP
(with window)
64-pin plastic QFP
Electrical specifications
Current dissipations are different.
Others
Noise immunity and noise radiation differ because circuit complexity and mask layout are
different.
Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To
replace the PROM version with the mask ROM version when shifting from experimental production
to mass production, evaluate your system by using the CS version (not ES version) of the mask
ROM version.
*
*
*
PD78P328
15
3.
PROM PROGRAMMING
The PROM incorporated in the
PD78P328 is a 16,384 x 8-bit electrically writable PROM. For programming,
set the PROM programming mode by using the RESET and AV
DD
pins.
The programming characteristics are compatible with the
PD27C256A programming characteristics.
Table 3-1. Pin Function in Programming Mode
Function
Normal Operating Mode
Programming Mode
Address input
P00-P07, P80, P20, P81-P85
A0-A14
Data input
P40-P47
D0-D7
Chip enable/program pulse
P33
CE
Output enable
P32
OE
Program voltage
EA
V
PP
Mode control
RESET, AV
DD
3.1 Operation Mode
To set the program write/verify mode, set RESET = H and AV
DD
= L. For the mode, the operation mode can be
selected by setting the CE and OE pins, as listed in Table 3-2.
To read the PROM contents, set the read mode.
Connect the unused pins exactly as indicated on Pin Configuration.
Table 3-2. PROM Programming Operation Mode
Mode
RESET
AV
DD
CE
OE
V
PP
V
DD
D0-D7
Program write
H
L
L
H
+12.5 V
+6 V
Data input
Program verify
H
L
Data output
Program inhibit
H
H
High impedance
Read
L
L
+5 V
+5 V
Data output
Output disable
L
H
High impedance
Standby
H
L/H
High impedance
Caution
When V
PP
is set to +12.5 V and V
DD
is set to +6V, setting both CE and OE to L is inhibited.
PD78P328
16
3.2 PROM Write Procedure
The write procedure into PROM is as follows: (See also Figure 3-2).
(1)
Fix RESET = H and AV
DD
= L. Connect other unused pins exactly as indicated in section "Pin Configuration."
(2)
Supply +6 V to the V
DD
and +12.5 V to the V
PP
pin.
(3)
Supply an initial address.
(4)
Supply write data.
(5)
Supply 1 ms program pulse (active low) to the CE pin.
(6)
Execute the verify mode. Check whether or not the write data is written normally.
When it is written normally: Proceed to step (8).
When it is not written normally: Repeat steps (4) to (6).
If the data is not written normally after 25 repetitions of the steps, proceed to step (7).
(7)
Assume the device to be defective. Stop write operation.
(8)
Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write).
(9)
Increment the address.
(10) Repeat steps (4) to (9) to the last address.
Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above.
Figure 3-1. PROM Write/Verify Timing
+12.5 V
V
PP
V
DD
+6 V
V
DD
V
DD
Data input
Data
output
Data input
Address input
Write
Hi-Z
Hi-Z
Hi-Z
Verify
Additional
data write
3 X ms
X-time repetition
D0-D7
CE (input)
OE (input)
A0-A14
PD78P328
17
Figure 3-2. Write Procedure Flowchart
(1)
(2)
(3)
(4)
(5)
(6)
Verify mode
Supply program pulse
Write OK
> end address
X: Number of write
repetitions
Write NG
(at the 25th repetition)
Write NG
(after 24
repetition or less)
Supply write data
Supply initial address
Supply power
WRITE START
Make additional write
(3X ms pulses)
Increment address
End address
WRITE END
Defective device
(8)
(9)
(10)
(7)
< end address
PD78P328
18
3.3 PROM Read Procedure
The read procedure of the PROM contents into the external data bus (D0-D7) is as follows.
(1)
Fix RESET = H and AV
DD
= L. Connect other unused pins exactly as indicated on Pin Configuration.
(2)
Supply +5 V to the V
DD
and V
PP
pins.
(3)
Input the address of the data to be read to the A0-A14 pins.
(4)
Execute the read mode.
(5)
The data is output to the D0-D7 pins.
Figure 3-3 shows the PROM read timing steps (2) to (5) above.
Figure 3-3. PROM Read Timing
Data output
Address input
Hi-Z
Hi-Z
D0-D7
CE (input)
OE (input)
A0-A14
PD78P328
19
4.
ERASURE CHARACTERISTICS (EPROM VERSION ONLY)
The data written into the
PD78P328DW program memory can be erased (FFH) and new data can be rewritten
into the memory.
To erase data, apply light with a wave length shorter than 400 nm to the window. Normally, apply ultraviolet rays
having the 254-nm wave length. The radiation amount required to completely erase data is as follows:
Ultraviolet strength x erasure time: 15 Ws/cm
2
or more
Erasure time:
15 to 20 minutes when a 12,000
W/cm
2
ultraviolet lamp is used. However, the time may be
prolonged due to ultraviolet lamp performance deterioration, dirty window, etc.
For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the
ultraviolet lamp, remove the filter before applying ultraviolet rays.
5.
WINDOW SEAL (EPROM VERSION ONLY)
If the
PD78P328DW window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may be
erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a protective
seal on the window.
A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at
shipment.
6.
ONE-TIME PROM VERSION SCREENING
The one-time PROM versions (
PD78P328CW, 78P328GF-3BE) cannot be completely tested by NEC for
shipment because of their structure. For screening, it is recommended to verify PROM after storing the necessary
data under the following conditions:
NEC provides chargeable services ranging from one-time PROM writing to marking, screening, and verification
for QTOP microcontroller products. For details, contact an NEC sales representative.
Storage temperature
Storage time
125C
24 hours
PD78P328
20
7.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25
C)
Parameter
Symbol
Test Conditions
Ratings
Unit
Power supply voltage
V
DD
0.5 to +7.0
V
V
DD
0.5 to V
DD
+0.5
V
V
PP
0.5 to +13.5
V
AV
SS
0.5 to +0.5
V
Input voltage
V
I1
Note 1
0.5 to V
DD
+0.5
V
V
I2
P20/NIM (A9) PIN
0.5 to +13.5
V
Output voltage
V
O
0.5 to V
DD
+0.5
V
Output current, low
I
OL
All output pins
4.0
mA
Total for all pins
90
mA
Output current, high
I
OH
All output pins
1.0
mA
Total for all pins
20
mA
Analog input voltage
V
IAN
Note 2
AV
DD
> V
DD
-0.5 to V
DD
+0.5
V
V
DD
AV
DD
-0.5 to AV
DD
+0.5
V
A/D converter reference
AV
REF
AV
DD
> V
DD
-0.5 to V
DD
+0.3
V
input voltage
V
DD
AV
DD
-0.5 to AV
DD
+0.3
V
Operating ambient temperature
T
A
10 to +70
C
Storage temperature
T
stg
65 to +150
C
Notes
1. Pins except for P20/NMI (A9), P70/ANI0-P77/ANI7
2. P70/ANI0-P77/ANI7
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,
even momentarily. In other words, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.
Recommended Operation Conditions
Oscillation frequency
T
A
V
DD
8 MHz
f
XX
16 MHz
10 to +70 C
+5.0 V
5%
Capacitance (T
A
= 25
C, V
SS
= V
DD
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
f = 1 MHz
10
pF
Output capacitance
C
O
Unmeasured pins returned to 0 V
20
pF
I/O capacitance
C
IO
20
pF
*
PD78P328
21
Resonator
Recommended Circuit
Parameter
MIN.
MAX.
Unit
Ceramic or crystal
Oscillation frequency (f
XX
)
8
16
MHz
resonator
External clock
X1 input frequency (f
X
)
8
16
MHz
X1 input rise, fall time (f
XR
, t
XF
)
0
20
ns
X1 input high, low level width
25
80
ns
(t
WXH
, t
WXL
)
Oscillator Characteristics (T
A
= 10 to +70
C, V
DD
= +5 V
5%, V
SS
= 0 V)
Caution When using the system clock oscillator, wire the portion enclosed in dotted line in the figure as
follows to avoid adverse influences on the wiring capacitance:
Keep the wiring length as short as possible.
Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high fluctuating current flows.
Always keep the ground point of the capacitor of the oscillator circuit at the same potential as
V
SS
. Do not connect the power source pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
Recommended Oscillator Constants
Ceramic resonator
Manufacturer Name
Part Number
Frequency
Recommended
[MHz]
Constants
C1 [pF]
C2 [pF]
MURATA
CSA8.00MT
8.0
30
30
CSA12.0MT
12.0
CSA16.00MX040
16.0
15
15
CST8.00MTW
8.0
Internal
Internal
CST12.00MTW
12.0
CST16.00MXW0C3
16.0
X1
X2
C1
C2
V
SS
X1
X2
HCMOS
Inverter
X1
X2
HCMOS
Inverter
Open
or
PD78P328
22
DC Characteristics (T
A
= 10 to +70
C, V
DD
= +5 V
5%, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, low
V
IL
0
0.8
V
Input voltage, high
V
IH1
Note 1
2.2
V
V
IH2
Note 2
0.8V
DD
Output voltage, low
V
OL
I
OL
= 2.0 mA
0.45
V
Output voltage, high
V
OH
I
OH
= 400
A
V
DD
1.0
V
Input leakage current
I
LI
0 V
V
I
V
DD
10
A
Output leakage current
I
LO
0 V
V
O
V
DD
10
A
V
DD
power supply current
I
DD1
Operation mode
45
75
mA
I
DD2
HALT mode
25
45
mA
Data retention voltage
V
DDDR
STOP mode
2.5
V
Data retention current
I
DDDR
STOP mode
V
DDDR
= 2.5 V
3
15
A
V
DDDR
= 5.0 V
5%
10
50
A
Notes 1. Pins except for RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0,
P33/SI/SB1, or P34/SCK.
2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0, P33/SI/SB1, or
P34/SCK pins.
PD78P328
23
AC Characteristics (T
A
= 10 to +70
C, V
DD
= +5 V
5%, V
SS
= 0 V)
Discontinuous read/write operation (when general-purpose memory is connected)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
System clock cycle time
t
CYK
125
250
ns
Address setup time (to ASTB
)
t
SAST
22
ns
Address hold time (from ASTB
)
t
HSTA
32
ns
Address
RD
delay time
t
DAR
85
ns
RD
address float time
t
FRA
8
ns
Address
data input time
t
DAID
222
ns
RD
data input time
t
DRID
112
ns
ASTB
RD
delay time
t
DSTR
42
ns
Data hold time (from RD
)
t
HRID
0
ns
RD
address active time
t
DRA
37
ns
RD low-level width
t
WRL
147
ns
ASTB high-level width
t
WSTH
37
ns
Address
WR
delay time
t
DAW
85
ns
ASTB
data output time
t
DSTOD
102
ns
WR
data output time
t
DWOD
40
ns
ASTB
WR
delay time
t
DSTW
42
ns
Data setup time (to WR
)
t
SODW
137
ns
Data hold time (from WR
)
t
HWOD
32
ns
WR
ASTB
delay time
t
DWST
42
ns
WR low-level width
t
WWL
147
ns
PD78P328
24
t
CYK
-Dependent Bus Timings
Parameter
Calculation expression
MIN./MAX.
Unit
t
SAST
0.5T 40
MIN.
ns
t
HSTA
0.5T 30
MIN.
ns
t
DAR
T 40
MIN.
ns
t
DAID
(2.5 + n) T 90
MAX.
ns
t
DRID
(1.5 + n) T 75
MAX.
ns
t
DSTR
0.5T 20
MIN.
ns
t
DRA
0.5T 25
MIN.
ns
t
WRL
(1.5 + n) T 40
MIN.
ns
t
WSTH
0.5T 25
MIN.
ns
t
DAW
T 40
MIN.
ns
t
DSTOD
0.5T + 40
MAX.
ns
t
DSTW
0.5T 20
MIN.
ns
t
SODW
1.5T 50
MIN.
ns
t
HWOD
0.5T 30
MIN.
ns
t
DWST
0.5T 20
MIN.
ns
t
WWL
(1.5 + n) T 40
MIN.
ns
Remarks 1. T = t
CYK
= 1/f
CLK
(f
CLK
is the internal system clock frequency and is provided by dividing f
XX
or f
X
by two).
2. n is the number of wait cycles defined by user software.
3. Only parameters listed in the table are dependent on t
CYK
.
PD78P328
25
Serial Operation (T
A
= 10 to +70
C, V
DD
= +5 V
5%, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Serial clock cycle time
t
CYSK
Input
External clock
1
s
Output
Internal divide by 8
8T
t
CYK
Internal divide by 32
32T
t
CYK
Serial clock high-level width
t
WSKL
Input
External clock
420
ns
Output
Internal divide by 8
4T80
ns
Internal divide by 32
16T100
ns
Serial clock high-level width
t
WSKH
Input
External clock
420
ns
Output
Internal divide by 8
4T80
ns
Internal divide by 32
16T100
ns
SI setup time (to SCK
)
t
SRXSK
80
ns
SI hold time (from SCK
)
t
HSKRX
80
ns
SO/SB0, SI/SB1
t
DSBSK1
CMOS push-pull output
0
210
ns
output delay time (from SCK
)
(3-wire serial I/O mode)
t
DSBSK2
Open drain output
0
600
ns
(SBI mode), RL = 1 k
SB0, SB1 high hold time (from SCK
) t
HSBSK
SBI mode
4T
t
CYK
SB0, SB1 low setup time (from SCK
) t
SSBSK
4T
t
CYK
SB0, SB1 low-level width
t
WSBL
4T20
ns
SB0, SB1 high-level width
t
WBSH
4T20
ns
Remark
T = t
CYK
= 1/f
CLK
(f
CLK
is the internal system clock frequency and is provided by dividing f
XX
or f
X
by two.)
PD78P328
26
Other operations (T
A
= 10 to +70C, V
DD
= +5 V
5%, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
NMI high-, low-level widths
t
WNIH
,
5
s
t
WNIL
INTP0 high-, low-level widths
t
WIOH
,
8T
t
CYK
t
WIOL
INTP1 high-, low-level widths
t
WI1H
,
8T
t
CYK
t
WI1L
INTP2 high-, low-level widths
t
WI2H
,
8T
t
CYK
t
WI2L
RESET high-, low-level widths
t
WRSH
,
5
s
t
WRSL
TI high-, low-level widths
t
WTIH
,
TM1
8T
t
CYK
t
WTIL
In the event counter mode
Remark
T = t
CYK
= 1/f
CLK
(f
CLK
is the internal system clock frequency and is provided by dividing f
XX
or f
X
by two.)
External clock timing (T
A
= 10 to +70C, V
DD
= +5 V
5%, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
X1 input high-, low-level widths
t
WXH
,
25
80
ns
t
WXL
X1 input rise, fall times
t
XR
,
0
20
ns
t
XF
TI input cycle time
t
CYK
62
125
ns
PD78P328
27
A/D Converter (T
A
= 10 to +70C, V
DD
= +5 V
5%, V
SS
= AV
SS
= 0 V, V
DD
0.5 V
AV
DD
V
DD
)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
bit
Total error
Note1
4.5 V
AV
REF
AV
DD
0.4
%FSR
3.4 V
AV
REF
AV
DD
0.7
%FSR
Quantification error
1/2
LSB
Conversion time
t
CONV
144
t
CYK
Sampling time
t
SAMP
24
t
CYK
Zero scale error
Note1
4.5 V
AV
REF
AV
DD
+1.5
2.5
LSB
3.4 V
AV
REF
AV
DD
+1.5
4.5
LSB
Fullscale error
Note1
4.5 V
AV
REF
AV
DD
+1.5
2.5
LSB
3.4 V
AV
REF
AV
DD
+1.5
4.5
LSB
Nonlinear error
Note1
4.5 V
AV
REF
AV
DD
+1.5
2.5
LSB
3.4 V
AV
REF
AV
DD
+1.5
4.5
LSB
Analog input voltage
Note2
V
IAN
0.3
AV
DD
V
Basic voltage
AV
REF
3.4
AV
DD
V
AV
REF
current
AI
REF
1.0
3.0
mA
AV
DD
supply current
AI
DD
2.0
6.0
mA
A/D converter data
AI
DDDR
STOP mode
AV
DDDR
= 2.5 V
2.0
10
A
retention current
AV
DDDR
= 5 V
5%
10
50
A
Notes 1. Quantization error is excluded.
2. When 0.3 V
V
IAN
0 V, conversion result is 000H.
When 0 V < V
IAN
< AV
REF
, conversion is executed by 10-bit resolution.
When AV
REF
V
IAN
AV
DD
, conversion result is 3 FFH.
Standby flag retention characteristics (T
A
= 10C to 70C)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Standby flag retention power supply voltage
V
DDDR
2.5
5.5
V
V
DD
rising, falling time
t
RVD
,
200
ns
t
FVD
*
AC Timing Test Points
0.8 V
DD
or 2.2 V
0.8 V
V
DD
1 V
0.45 V
0.8 V
DD
or 2.2 V
0.8 V
Test
Points
PD78P328
28
Timing Wave Forms
Discontinuous Read Operation
Discontinuous Write Operation
(CLK)
P50-P57
(output)
ASTB
(output)
P40-P47
(input/output)
t
SODW
t
WWL
t
DAW
WR (output)
t
DSTW
t
DWOD
t
HSTA
t
DSTA
t
HWOD
t
DSTOD
t
WSTH
t
SAST
Low-order address
(output)
Data (output)
Low-order address
(output)
High-order address
High-order address
(CLK)
P50-P57
(output)
P50-P57
(output)
P40-P47
(input/output)
t
DRA
t
WRA
t
DAR
RD (output)
t
DSTR
t
HSTA
t
FRA
t
HRID
t
DRID
t
CYK
t
WSTH
t
SAST
t
DAID
Low-order address
(output)
High-order address
High-order address
Hi-Z
Hi-Z
Hi-Z
Data (input)
Low-order address
(output)
PD78P328
29
SCK
SO
SI
Output data
Input data
t
WSKL
t
CYSK
t
WSKH
t
SRXSK
t
HSKRX
t
DSBSKI
SCK
t
HSBSK
t
WSBL
t
WSBH
t
SSBSK
SB0
SCK
t
HSBSK
t
SSBSK
t
CYSK
t
DSBSK2
t
SSSK
t
HSSK
t
WSKL
t
WSKH
SB0
I/O data
Serial Operation
Three-Wire Serial I/O Mode:
SBI Mode
Bus Release Signal Transfer
Command Signal Transfer
PD78P328
30
Interrupt Input Timing
Reset Input Timing
NMI
t
WNIL
t
WNIH
0.8 V
DD
0.8 V
INTP0
t
WIOL
t
WIOH
INTP1
t
WI1L
t
WI1H
INTP2
t
WI2L
t
WI2H
RESET
t
WRSL
t
WRSH
0.8 V
DD
0.8 V
PD78P328
31
External Clock Timing
Standby Flag Retention Timing
TI Pin Input Timing
X1
t
WXL
t
XR
t
XF
t
CYX
t
WXH
V
DD
V
DDDR
t
FVD
t
RVD
TI
t
WTIH
t
WTIL
PD78P328
32
Parameter
Symbol Symbol Test conditions
MIN.
TYP.
MAX.
Unit
Note1
Input voltage, high
V
IH
V
IH
2.2
V
DDP
V
+0.3
Input voltage, low
V
IL
V
IL
0.3
0.8
V
Input leakage current
I
LIP
I
LI
0
V
I
V
DDP
Note 2
10
A
Output voltage, high
V
OH
V
OH
I
OH
= 400
A
2.4
V
Output voltage, low
V
OL
V
OL
I
OL
= 2.0 mA
0.45
V
Input current
I
A9
--
A9 (P20/NMI) pin
10
A
Output leakage current
I
LO
--
0
V
O
V
DDP
, OE = V
IN
10
A
PROG pin high voltage input
I
IP
--
10
A
current
V
DDP
power supply voltage
V
DDP
V
DD
Program memory write mode
5.75
6.0
6.25
V
Program memory read mode
4.5
5.0
5.5
V
V
PP
power supply voltage
V
PP
V
PP
Program memory write mode
12.2
12.5
12.8
V
Program memory read mode
V
PP
= V
DDP
V
V
DDP
power supply current
I
DD
I
DD
Program memory write mode
10
30
mA
Program memory read mode
10
30
mA
CE = V
IL
, OE = V
IN
V
PP
power supply current
I
PP
I
PP
Program memory write mode
10
30
mA
CE = V
IL
, OE = V
IN
Program memory read mode
1
100
A
DC Programming Characteristics (T
A
= 25
5
C, V
SS
= 0 V)
Notes 1. Corresponding
PD27C256A symbols.
2. V
DDP
is V
DD
pin during the programming mode.
PD78P328
33
AC Programming Characteristics (T
A
= 25
5
C, V
SS
= 0 V)
Note
Corresponding
PD27C256A symbols.
Parameter
Symbol Symbol Test conditions
MIN.
TYP.
MAX.
Unit
Note
Address setup time (to CE
)
t
SAC
t
AS
2
s
Data
OE
delay time
t
DDOO
t
OES
2
s
Input data setup time (to CE
)
t
SIDC
t
DS
2
s
Address hold time (from CE
)
t
HCA
t
AH
2
s
Input data hold time (from CE
)
t
HCID
t
DH
2
s
Output data hold time (from OE
)
t
HOOD
t
DF
0
130
ns
V
PP
setup time (to CE
)
t
SVPC
t
VPS
2
s
V
DDP
setup time (to CE
)
t
SVDC
t
VDS
2
s
Initial program pulse width
t
WL1
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
WL2
t
OPW
2.85
78.75
ms
Address
data output time
t
DAOD
t
ACC
OE = V
IL
2
s
OE
data output time
t
DOOD
t
OE
1
s
Data hold time (from OE
)
t
HCOD
t
DF
0
130
ns
Data hold time (from address)
t
HAOD
t
OH
OE = V
IL
0
ns
PD78P328
34
PROM Write Mode Timing
Cautions 1. Apply V
DDP
before V
PP
and remove it after V
PP
.
2. V
PP
must not exceed +13 V, including the overshoot.
PROM Read Mode Timing
A12-A0
D7-D0
V
PP
V
DDP
V
DDP
V
IH
V
IL
V
IH
V
IL
V
DDP
+1
CE
OE
V
PP
V
DDP
t
DOOD
t
DDOO
t
SVDC
t
SVPC
t
SIDC
t
HCID
t
SIDC
t
HCID
t
HOOD
t
SAC
t
WL1
t
HCA
t
WL2
Data input
Effective address
Data output
Data onput
A12-A0
D7-D0
OE
t
HAOD
t
DAOD
t
DOOD
t
HCOD
Data output
Effective address
Hi-Z
Hi-Z
PD78P328
35
8.
PACKAGE DRAWINGS
A
I
J
G
H
F
D
N
M
C
B
M
R
64
33
32
1
K
L
NOTE
Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
P64C-70-750A,C-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
58.68 MAX.
1.778 (T.P.)
3.20.3
0.51 MIN.
4.31 MAX.
1.78 MAX.
L
M
0.17
0.25
19.05 (T.P.)
5.08 MAX.
17.0
N
0~15
0.500.10
0.9 MIN.
R
2.311 MAX.
0.070 MAX.
0.020
0.035 MIN.
0.1260.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007
0~15
+0.004
0.003
0.070 (T.P.)
1)
Item "K" to center of leads when formed parallel.
2)
+0.10
0.05
+0.004
0.005
64 PIN PLASTIC SHRINK DIP (750 mil)
PD78P328
36
PD78P328
37
64 PIN PLASTIC QFP (14
20)
P64GF-100-3B8,3BE,3BR-2
ITEM
MILLIMETERS
INCHES
A
B
C
23.60.4
20.00.2
14.00.2
0.9290.016
0.795
0.551
D
17.60.4
0.6930.016
F
1.0
0.039
G
1.0
0.039
H
0.400.10
0.016
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P)
K
1.80.2
0.071
L
0.80.2
0.031
M
0.15
0.006
N
0.10
0.004
P
2.7
0.106
Q
0.10.1
0.0040.004
R
55
55
S
3.0 MAX.
0.119 MAX.
+0.008
0.009
+0.009
0.008
+0.004
0.005
+0.008
0.009
+0.009
0.008
+0.004
0.003
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
51
52
32
64
1
20
19
33
I
J
M
N
H
G
F
A
S
P
K
L
M
B
C
D
detail of lead end
Q
R
+0.10
0.05
PD78P328
38
9.
RECOMMENDED SOLDERING CONDITIONS
It is recommended that this device be soldered under the following conditions.
For details on the recommended soldering conditions, refer to information document "Semiconductor Devices
Mounting Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.
Table 9-1. Soldering Conditions for Surface Mount Devices
PD78P328GF-3BE: 64-pin plastic QFP (14 x 20 mm)
Soldering Method
Soldering Conditions
Recommended Soldering
Code
Infrared reflow
Package peak temperature: 235C,
IR35-207-2
Time: 30 seconds max. (210C min.),
Number of times: 2 max, Maximum number of days: 7 days
Note
(thereafter, 20 hours of prebaking is required at 125C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first
reflow before starting the second reflow.
(2) Do not perform flux cleaning with water after the first reflow.
VPS
Package peak temperature: 215C,
VP15-207-2
Time: 40 seconds max. (200C min.),
Number of times: 2 max, Maximum number of days: 7 days
Note
(thereafter, 20 hours of prebaking is required at 125C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first
reflow before starting the second reflow.
(2) Do not perform flux cleaning with water after the first reflow.
Wave soldering
Soldering bath temperature: 260C max., Time: 10 seconds max.,
WS60-207-1
Number of times: 1,
Preheating temperature: 120
C max. (package surface temperature),
Maximum number of days: 7 days
Note
(thereafter, 20 hours of
prebaking is required at 125C).
Partial heating
Pin temperature: 300C max.,
--
Time: 3 seconds max. (per pin row)
Note Number of days after unpacking the dry pack. Storage conditions are 25
C and 65% RH max.
Caution
Do not use different soldering methods together (except the partial heating method).
Table 9-2. Soldering Conditions for Through-hole Devices
PD78P328CW: 64-pin Plastic Shrink DIP (750 mils)
PD78P328DW: 64-pin Ceramic Shrink DIP (750 mils) (with window)
Soldering Method
Soldering Conditions
Wave soldering (pin only)
Soldering bath temperature: 260C max., Time: 10 seconds max.
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin)
Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact
with the package.
*
PD78P328
39
APPENDIX A. DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT
The emulation probe (EP-78327GF-R) for the
PD78P328GF-3BE is connected with the target system in
combination with the conversion socket (EV-9200G-64).
The drawings of the socket and recommended footprint are shown below.
Figure A-1. Drawing of Conversion Socket (EV-9200G-64)
(for reference only)
A
G
E
1
No.1 pin index
F
B
C
N
O
P
M
L
T
S
J
I
R
D
U
Q
EV-9200G-64
K
H
EV-9200G-64-G0
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
O
N
P
Q
R
S
T
U
25.0
20.30
4.0
14.45
19.0
4-C 2.8
0.8
11.0
22.0
24.7
5.0
16.2
18.9
8.0
7.8
2.5
2.0
1.35
0.350.1
2.3
1.5
0.984
0.799
0.157
0.569
0.748
4-C 0.11
0.031
0.433
0.866
0.972
0.197
0.638
0.744
0.315
0.307
0.098
0.079
0.053
0.014
0.091
0.059
+0.004
0.005
*
PD78P328
40
Figure A-2. Recommended Footprint for EV-9200G-64
(for reference only)
A
F
D
E
B
G
J
K
C
L
M
H
I
0.039
0.709=0.709
0.039
0.472=0.472
EV-9200G-64-P0
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
25.7
21.0
15.2
19.9
11.000.08
5.500.03
5.000.08
2.500.03
0.60.02
2.360.03
1.570.03
1.012
0.827
0.598
0.783
0.433
0.217
0.197
0.098
0.024
0.093
0.062
1.00.02
18=18.00.05
1.00.02
12=12.00.05
+0.002
0.001
+0.002
0.003
+0.002
0.001
+0.003
0.002
+0.004
0.003
+0.001
0.002
+0.003
0.004
+0.002
0.001
+0.001
0.002
+0.001
0.002
+0.001
0.002
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).
Caution
PD78P328
41
APPENDIX B. TOOLS
B.1 Development Tools
The following development tools are readily available to support development of systems using the
PD78P328:
Language Processor
Remark
The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under
the operating systems listed above.
78K/III Series
Relocatable assembler common to the 78K/III series. Since it contains the macro function, the
relocatable assembler
development efficiency can be improved. A structured assembler which enables you to explicity
(RA78K/III)
describe program control structure is also attached and program productivity and maintenance
can be improved.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
TM
3.5-inch 2HD
S5A13RA78K3
5-inch 2HD
S5A10RA78K3
IBM PC/AT
TM
PC DOS
TM
3.5-inch 2HC
S7B13RA78K3
and compatible machine
5-inch 2HC
S7B10RA78K3
HP9000 series 700
TM
HP-UX
TM
DAT
S3P16RA78K3
SPARCstation
TM
SunOS
TM
Cartridge tape
S3K15RA78K3
NEWS
TM
NEWS-OS
TM
(QIC-24)
S3R15RA78K3
78K/III Series
C compiler common to the 78K/III series. This is a program to convert a program written in C
C compiler
language into an object code executable with a microcontroller. When using the compiler,
(CC78K/III)
78K/III series relocatable assembler(RA78K/III) is necessary.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13CC78K3
5-inch 2HD
S5A10CC78K3
IBM PC/AT
TM
PC DOS
3.5-inch 2HC
S7B13CC78K3
and compatible machine
5-inch 2HC
S7B10CC78K3
HP9000 series 700
HP-UX
DAT
S3P16CC78K3
SPARCstation
SunOS
Cartridge tape
S3K15CC78K3
NEWS
NEWS-OS
(QIC-24)
S3R15CC78K3
*
PD78P328
42
PROM Write Tools
Hard-
PG-1500
PG-1500 is a PROM programmer which enables you to program single chip micro-
ware
controllers containing PROM by stand-alone or host machine operation by connecting an
attached board and optional programmer adapter to PG-1500. It also enables you to
program typical PROM devices of 256K bits to 4M bits.
UNISITE
PROM programmer manufactured by Data I. O. Japan.
2900
PA-78P328CW
PROM programmer adapters to write programs onto the
PD78P328 on a general
PA-78P328GF
purpose PROM programmer such as PG-1500.
PA-78P328CW ...
PD78P328CW and 78P328DW
PA-78P328GF ...
PD78P328GF
Soft-
PG-1500 controller
Connects PG-1500 and a host machine by a serial or parallel interface and controlls
ware
PG-1500 on the host machine.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13PG1500
5-inch 2HD
S5A10PG1500
IBM PC/AT
PC DOS
3.5-inch 2HD
S7B13PG1500
and compatible machine
5-inch 2HC
S7B10PG1500
Hard-
IE-78327-R
IE-78327-R is an in-circuit emulator that can be used for application system development
ware
and debugging.
EP-78327CW-R
Emulation probe for 64-pin plastic shrink DIP to connect IE-78327-R to the target system.
EP-78327GF-R
Emulation probe for 94-pin plastic QFP to connect IE-78327-R to the target system.
EV-9200G-64 One conversion socket EV-9200G-64 used for connection to the target system
is attached.
Soft-
IE-78327-R
Program to control IE-78327-R on a host machine. Automatic execution of commands,
ware
control program
etc., is enabled for more efficient debugging.
(IE controller)
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13IE78327
5-inch 2HD
S5A10IE78327
IBM PC/AT
PC DOS
3.5-inch 2HD
S7B13IE78327
and compatible machine
5-inch 2HC
S7B10IE78327
Remark
The operation of the PG-1500 controller is guaranteed only on the host machine under the operating
systems listed above.
Debugging Tools
Remark
The operation of the IE controller is guaranteed only on the host machine under the operating systems
listed above.
PD78P328
43
Development Tool Configuration
Note The socket is attached to the emulation probe.
Remarks 1. The host machine and PG-1500 can be connected directly by RS-232-C.
2. Supply media of software are represented as 3.5-inch floppy disks in the figure above.
Host machine
PC-9800 series or
IBM PC/AT
Software
RS-232C
RS-232C
PG-1500
Relocatable
assembler (with
structure assembler)
PG-1500
controller
IE controller
IE-78327-R
In-circuit
emulator
PROM
programmer
On-chip PROM version
Programmer adapter
PD78P328GF
PA-78P328GF
EV-9200G-64
EP-78327GF-R
EP-78327GF-R
Socket to connect emulation probe and target system
Note
SDIP socket
Target system
PA-78P328CW
Emulation probe
+
+
+
+
+
PD78P328CW
PD78P328DW
PD78P328
44
B.2 Evaluation Tools
The following evaluation tools are provided to evaluate the
PD78P328 function:
Ordering Code
Host Machine
Function
(product name)
EB-78327-98
PC-9800 series
The
PD78P328 function can be easily evaluated by connecting the evaluation tool to
a host machine. The EB-78327-98/PC command system basically is compliant with the
EB-78327-PC
IBM PC/AT
IE-78327-R command system. Thus, easy transition to application system development
and compatible
process by IE-78327-R can be made. The evaluation tools enable turbo access manager
machine
(
PD71P301)
Note
to be mounted on the printed circuit board.
Note Turbo access manager (
PD71P301) is available for maintenance purpose only.
Cautions
1.
EB-78327-98/PC is not the
PD78P328 application system development tool.
2.
EB-78327-98/PC does not contain the emulation function at internal PROM execution of the
PD78P328.
B.3 Embedded Software
The following embedded software products are readily available to support more efficient program development
and maintenance:
Real-time OS
Real-time OS
The purpose of RX78K/III is to realize a multi-task environment in a control area which requires
(RX78K/III)
real-time processing. RX78K/III allocates idle times of CPU to other processing to improve
overall performance of the system.
RX78K/III provides a system call based on the
ITRON specification.
RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to
prepare multiple information tables.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13RX78320
5-inch 2HD
S5A10RX78320
IBM PC/AT
PC DOS
3.5-inch 2HC
S7B13RX78320
and compatible machine
5-inch 2HC
S7B10RX78320
Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the
User's Agreement.
Remark
When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary.
PD78P328
45
Fuzzy Inference Development Support System
Fuzzy knowledge Data
Program supporting input of fuzzy knowledge data (fuzzy rule and membership function),
Preparation Tool
input/editing (edit), and evaluation (simulation).
(FE9000, FE9200)
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13FE9000
5-inch 2HD
S5A10FE9000
IBM PC/AT
PC DOS Windows
TM
3.5-inch 2HC
S7B13FE9200
and compatible machine
5-inch 2HC
S7B10FE9200
Translator
Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation
(FT78K3)
Note
tool to the assembler source program for the RA78K/III.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13FT78K3
5-inch 2HD
S5A10FT78K3
IBM PC/AT
PC DOS
3.5-inch 2HC
S7B13FT78K3
and compatible machine
5-inch 2HC
S7B10FT78K3
Fuzzy Inference Module
Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge
(FI78K/III)
Note
data converted by translator.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13FI78K3
5-inch 2HD
S5A10FI78K3
IBM PC/AT
PC DOS
3.5-inch 2HC
S7B13FI78K3
and compatible machine
5-inch 2HC
S7B10FI78K3
Fuzzy Inference Debugger
Support software evaluating and adjusting fuzzy knowledge data at hardware level by using
(FD78K/III)
in-circuit emulator.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
S5A13FD78K3
5-inch 2HD
S5A10FD78K3
IBM PC/AT
PC DOS
3.5-inch 2HC
S7B13FD78K3
and compatible machine
5-inch 2HC
S7B10FD78K3
Note
Under development
46
CHAPTER 2 PIN FUNCTIONS
[MEMO]
PD78P328
47
NOTES FOR CMOS DEVICES
(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate
oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it once,
when it has occurred. Environmental control must be adequate. When it is dry,
humidifier should be used. It is recommended to avoid using insulators that easily
build static electricity. Semiconductor devices must be stored and transported in an
anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
(2) HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection
is provided to the input pins, it is possible that an internal input level may be generated
due to noise, etc., hence causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by
using a pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output pin.
All handling related to the unused pins must be judged device by device and related
specifications governing the devices.
(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device. Immediately
after the power source is turned ON, the devices with reset function have not yet been
initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or
contents of registers. Device is not initialized until the reset signal is received. Reset
operation must be executed immediately after power-on for devices having reset
function.
QTOP is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
PD78P328
M4 94.11
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computer, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for
life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
The export of these products from Japan is regulated by the Japanese government. The export of some
or all of these products may be prohibited without governmental license. To export or re-export some or
all of these products from a country other than Japan may also be prohibited without a license from that
country. Please call an NEC sales representative.
License not needed:
PD78P328DW
The customer must judge the need for license:
PD78P328CW, 78P328GF-3BE
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