Document Outline

COVER
DESCRIPTION
FEATURES
APPLICATIONS
ORDERING INFORMATION
78K/IV SERIES LINEUP
OVERVIEW OF FUNCTIONS
1. DIFFERENCES AMONG MODELS IN mPD784218, 784218Y SUBSERIES
2. DIFFERENCES BETWEEN mPD784218 AND mPD784216
3. MAJOR DIFFERENCES FROM mPD78078, 78078Y SUBSERIES
4. PIN CONFIGURATION (TOP VIEW)
5. BLOCK DIAGRAM
6. PIN FUNCTIONS
- 6.1 Port Pins
- 6.2 Non-Port Pins
- 6.3 Pin I/O Circuits and Recommended Connections of Unused Pins
7. CPU ARCHITECTURE
- 7.1 Memory Space
- 7.2 CPU Registers
  - 7.2.1 General-purpose registers
  - 7.2.2 Control registers
  - 7.2.3 Special function registers (SFRs)
8. PERIPHERAL HARDWARE FUNCTION FEATURES
- 8.1 Ports
- 8.2 Clock Generator
- 8.3 Real-Time Output Port
- 8.4 Timer/Event Counter
- 8.5 A/D Converter
- 8.6 D/A Converter
- 8.7 Serial Interfaces
  - 8.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
  - 8.7.2 Clocked serial interface (CSI)
- 8.8 Clock Output Function
- 8.9 Buzzer Output Function
- 8.10 Edge Detection Function
- 8.11 Watch Timer
- 8.12 Watchdog Timer
9. INTERRUPT FUNCTION
- 9.1 Interrupt Sources
- 9.2 Vectored Interrupt
- 9.3 Context Switching
- 9.4 Macro Service
- 9.5 Application Example of Macro Service
10. LOCAL BUS INTERFACE
- 10.1 Memory Expansion
- 10.2 Programmable Wait
- 10.3 External Access Status Function
11. STANDBY FUNCTION
12. RESET FUNCTION
13. ROM CORRECTION
14. INSTRUCTION SET
15. ELECTRICAL SPECIFICATIONS
16. PACKAGE DRAWINGS
17. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A DEVELOPMENT TOOLS
APPENDIX B RELATED DOCUMENTS

DATA SHEET

1997, 2000

MOS INTEGRATED CIRCUIT

PD784218, 784218Y

16-/8-BIT SINGLE-CHIP MICROCONTROLLERS

Document No. U12304EJ2V0DS00 (2nd edition)
Date Published March 2000 N CP(K)
Printed in Japan

DESCRIPTION

The

PD784218 is a member of the

PD784218 Subseries of the 78K/IV Series. In addition to a high-speed and

high-performance CPU, the

PD784218 incorporates a variety of peripheral hardware such as ROM, RAM, I/O ports,

8-bit resolution A/D and D/A converters, timers, serial interfaces, real-time output ports, and an interrupt function.

The

PD784218Y

Note

is the

PD784218 Subseries with a multi-master supporting I

C bus interface added.

Flash memory versions, the

PD78F4218 and 78F4218Y, which can operate in the same voltage range as the

mask ROM versions, and various development tools are also available.

Note Under development

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

PD784218, 784218Y Subseries User's Manual Hardware: U12970E

78K/IV Series User's Manual Instructions:

U10905E

The mark shows major revised points.

FEATURES

· On-chip ROM correction function

· Inherits peripheral functions of

PD78078Y Subseries

· Minimum instruction execution time

160 ns

(@ f

= 12.5 MHz operation with main system clock)

(@ f

= 32.768 kHz operation with subsystem clock)

· Internal high-capacity memory

· ROM: 256 KB

· RAM: 12,800 bytes

· I/O ports: 86

· Timer/counters: 16-bit timer/event counter

1 unit

8-bit timer/event counter

6 units

· Serial interfaces: 3 channels

UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O, multi-master supporting I

bus

Note

): 1 channel

· Standby function

HALT/STOP/IDLE mode

In power-saving mode: HALT/IDLE mode (with

subsystem clock)

· Clock division function

· Watch timer: 1 channel

· Watchdog timer: 1 channel

· Clock output function

Selectable from f

, f

/2, f

, f

· Buzzer output function

Selectable from f

, f

· A/D converter: 8-bit resolution

8 channels

· D/A converter: 8-bit resolution

2 channels

· Supply voltage: V

= 2.2 to 5.5 V

Note

PD784218Y only

Unless otherwise specified, references in this document to the

PD784218 refer to the

PD784218 and

the

PD784218Y.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216

PD784216Y

PD784038

PD784038Y

PD784225Y

PD784225

PD784218Y

PD784218

Enhanced
A/D converter,
16-bit timer, and
power management

Enhanced internal memory capacity
Pin-compatible with the PD784026

C bus supported

Multi-master I

C bus supported

80-pin, ROM correction added

Multi-master I

C bus supported

Enhanced internal memory
capacity, ROM correction added

100-pin, enhanced I/O and
internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control
On-chip analog circuit for VCRs
Enhanced timer

Multi-master I

C bus supported

Enhanced functions
of the PD784915

Standard models

ASSP models

Multi-master I

C bus supported

: Under mass production

: Under development

PD784967

On-chip FIP controller/driver

PD784938

Enhanced functions of the
PD784908, enhanced
internal memory capacity,
ROM correction added.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

OVERVIEW OF FUNCTIONS (1/2)

Part Number

PD784218,

PD784218Y

Note 1

Item

Number of basic instructions

113

(mnemonics)

General-purpose registers

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

Minimum instruction execution

· 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@ f

= 12.5 MHz operation with main system clock)

time

· 61

s (@ f

= 32.768 kHz operation with subsystem clock)

Internal

ROM

256 KB

memory

RAM

12,800 bytes

Memory space

1 MB with program and data spaces combined

I/O ports

Total

CMOS input

CMOS I/O

N-ch open-drain I/O

Pins with pull-up

resistor

LED direct

drive outputs

Middle-

voltage pins

Real-time output port

4 bits

2, or 8 bits

Timer/counters

Timer/event counter:

Timer counter

Pulse output

(16-bit)

Capture/compare register

· PPG output
· Square wave output
· One-shot pulse output

Timer/event counter 1:

Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer/event counter 2:

Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer/event counter 5:

Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer/event counter 6:

Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer/event counter 7:

Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer/event counter 8:

Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Serial interfaces

· UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
· CSI (3-wire serial I/O, multi-master supporting I

C bus

Note 3

): 1 channel

A/D converter

8-bit resolution

8 channels

D/A converter

8-bit resolution

2 channels

Notes 1. Under development

2. The pins with ancillary functions are included in the I/O pins.

PD784218Y only

Pins with
ancillary
functions

Note 2

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

CONTENTS

DIFFERENCES AMONG MODELS IN

PD784218, 784218Y SUBSERIES ...............................

DIFFERENCES BETWEEN

PD784218 AND

PD784216 ..........................................................

MAJOR DIFFERENCES FROM

PD78078, 78078Y SUBSERIES ..............................................

PIN CONFIGURATION (TOP VIEW) ..............................................................................................

BLOCK DIAGRAM ..........................................................................................................................

PIN FUNCTIONS .............................................................................................................................

6.1

Port Pins ................................................................................................................................ 14

6.2

Non-Port Pins .......................................................................................................................

6.3

Pin I/O Circuits and Recommended Connections of Unused Pins ..............................

CPU ARCHITECTURE ....................................................................................................................

7.1

Memory Space ......................................................................................................................

7.2

CPU Registers ......................................................................................................................

7.2.1 General-purpose registers ..........................................................................................................

7.2.2 Control registers ..........................................................................................................................

7.2.3 Special function registers (SFRs) ...............................................................................................

PERIPHERAL HARDWARE FUNCTION FEATURES ...................................................................

8.1

Ports ....................................................................................................................................... 31

8.2

Clock Generator ...................................................................................................................

8.3

Real-Time Output Port .........................................................................................................

8.4

Timer/Event Counter ............................................................................................................

8.5

A/D Converter .......................................................................................................................

8.6

D/A Converter .......................................................................................................................

8.7

Serial Interfaces ...................................................................................................................

8.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................

8.7.2 Clocked serial interface (CSI) .....................................................................................................

8.8

Clock Output Function ........................................................................................................

8.9

Buzzer Output Function ......................................................................................................

8.10 Edge Detection Function ....................................................................................................

8.11 Watch Timer ..........................................................................................................................

8.12 Watchdog Timer ...................................................................................................................

INTERRUPT FUNCTION.................................................................................................................

9.1

Interrupt Sources .................................................................................................................

9.2

Vectored Interrupt ................................................................................................................

9.3

Context Switching ................................................................................................................

9.4

Macro Service .......................................................................................................................

9.5

Application Example of Macro Service .............................................................................

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

10. LOCAL BUS INTERFACE ..............................................................................................................

10.1 Memory Expansion ..............................................................................................................

10.2 Programmable Wait .............................................................................................................

10.3 External Access Status Function ......................................................................................

11. STANDBY FUNCTION .....................................................................................................................

12. RESET FUNCTION..........................................................................................................................

13. ROM CORRECTION .......................................................................................................................

14. INSTRUCTION SET ........................................................................................................................

15. ELECTRICAL SPECIFICATIONS ...................................................................................................

16. PACKAGE DRAWINGS ..................................................................................................................

17. RECOMMENDED SOLDERING CONDITIONS .............................................................................

APPENDIX A DEVELOPMENT TOOLS ..............................................................................................

APPENDIX B RELATED DOCUMENTS .............................................................................................

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

1. DIFFERENCES AMONG MODELS IN

PD784218, 784218Y SUBSERIES

The

PD784218Y is the

PD784218 with I

C bus control added.

The

PD78F4218 and 78F4218Y are provided with a 256 KB flash memory instead of the mask ROM of the above

models. These differences are summarized in Table 1-1.

Table 1-1. Differences Among Models in

PD784218, 784218Y Subseries

Part Number

PD784218,

PD784218Y

PD78F4218,

PD78F4218Y

Item

Internal ROM

256 KB

(mask ROM)

(Flash memory)

Internal RAM

12,800 bytes

Internal memory

None

Provided

Note

size switching

Supply voltage

= 2.2 to 5.5 V

= 2.7 to 5.5 V

Electrical

Refer to the data sheet for each device.

specifications

Recommended

soldering

conditions

TEST pin

Provided

None

Provided

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal

memory size switching register (IMS).

Caution

There are differences in noise immunity and noise radiation between the flash memory

and mask ROM versions. When pre-producing an application set with the flash memory

version and then mass-producing it with the mask ROM version, be sure to conduct

sufficient evaluations on the commercial samples (not engineering samples) of the mask

ROM version.

2. DIFFERENCES BETWEEN

PD784218 AND

PD784216

Table 2-1 shows the differences between the

PD784218 and

PD784216.

Table 2-1. Differences between

PD784218 and

PD784216

Part Number

PD784218

PD784216

Item

Internal ROM

256 KB

128 KB

Internal RAM

12,800 bytes

8,192 bytes

ROM correction

Provided

None

External access status function

Provided

None

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

3. MAJOR DIFFERENCES FROM

PD78078, 78078Y SUBSERIES

Series Name

PD784218, 784218Y Subseries

PD78078, 78078Y Subseries

Item

CPU

16-bit CPU

8-bit CPU

Minimum instruction

With main

160 ns (@ 12.5 MHz operation)

400 ns (@ 5.0 MHz operation)

execution time

system clock

With subsystem

s (@ 32.768 kHz operation)

122

s (@ 32.768 kHz operation)

clock

Memory space

1 MB

64 KB

I/O ports

Total

CMOS input

CMOS I/O

N-ch open-drain I/O

Pins with ancillary

Pins with pull-up

functions

Note 1

resistor

LED direct drive

outputs

Middle-voltage pins

Timer/counters

· 16-bit timer/event counter

1 unit

· 16-bit timer/event counter

1 unit

· 8-bit timer/event counter

6 units

· 8-bit timer/event counter

4 units

Serial interfaces

· UART/IOE (3-wire serial I/O)

2 channels

1 channel

· CSI (3-wire serial I/O, multi-master

· CSI (3-wire serial I/O, 2-wire serial

supporting I

C bus

Note 2

)

I/O, I

C bus

Note 3

)

1 channel

· CSI (3-wire serial I/O, 3-wire serial

I/O with automatic transmit/receive

function)

1 channel

Interrupts

NMI pin

Provided

None

Macro service

Provided

None

Context switching

Provided

None

Programmable priority

4 levels

None

Standby function

HALT/STOP/IDLE modes

HALT/STOP modes

In low-power consumption mode:

HALT/IDLE modes

ROM correction

Provided

None

External access status function

Provided

None

Package

· 100-pin plastic LQFP (fine pitch)

(14

14 mm)

(14

14 mm)

· 100-pin plastic QFP (14

20 mm)

· 100-pin plastic QFP (14

20 mm)

· 100-pin ceramic WQFN

(14

20 mm) (

PD78P078 and

78P078Y only)

Notes 1. The pins with ancillary functions are included in the I/O pins.

PD784218Y Subseries only

PD78078Y Subseries only

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

4. PIN CONFIGURATION (TOP VIEW)

· 100-pin plastic LQFP (fine pitch) (14

14 mm)

PD784218GC-

×××

-8EU, 784218YGC-

×××

-8EU

Note 5

100

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

Note 2

REF0

P10/ANI0

P62/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

P84/A4

P83/A3

P95

P94

P93

P92

P91

P90

TEST

Note 1

P37/EXA

P36/TI01

P35/TI00

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P103/TI8/TO8

P102/TI7/TO7

P101/TI6/TO6

P100/TI5/TO5

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P63/A19

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

Note 3

P130/ANO0

P131/ANO1

REF1

P70/RxD2/SI2

P71/TxD2/SO2

P72/ASCK2/SCK2

P20/RxD1/SI1

P21/TxD1/SO1

P22/ASCK1/SCK1

P23/PCL

P24/BUZ

P25/SI0/SDA0

Note 4

P26/SO0

P27/SCK0/SCL0

Note 4

P80/A0

P81/A1

P82/A2

Notes 1. Connect the TEST pin directly to V

or pull down. For the pull-down connection, use of a resistor whose

resistance is between 470

and 10 k

is recommended.

2. Connect the AV

pin to V

3. Connect the AV

pin to V

4. The SCL0 and SDA0 pins are incorporated only in the

PD784218Y.

5. Under development

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

· 100-pin plastic QFP (14

20 mm)

PD784218GF-

×××

-3BA, 784218YGF-

×××

-3BA

Note 5

100

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

P84/A4

P83/A3

P82/A2

P81/A1

P80/A0

P27/SCK0/SCL0

Note 4

P26/SO0

P25/SI0/SDA0

Note 4

P24/BUZ

P23/PCL

P22/ASCK1/SCK1

P21/TxD1/SO1

P20/RxD1/SI1

P72/ASCK2/SCK2

P71/TxD2/SO2

P70/RxD2/SI2

REF1

P131/ANO1

P130/ANO0

Note 3

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

REF0

Note 2

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P100/TI5/TO5

P101/TI6/TO6

P102/TI7/TO7

P103/TI8/TO8

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/TI00

P36/TI01

P37/EXA

TEST

Note 1

P90

P91

P92

P93

P94

P95

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

Notes 1. Connect the TEST pin directly to V

or pull down. For the pull-down connection, use of a resistor whose

resistance is between 470

and 10 k

is recommended.

2. Connect the AV

pin to V

3. Connect the AV

pin to V

4. The SCL0 and SDA0 pins are incorporated only in the

PD784218Y.

5. Under development

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

A0 to A19:

Address Bus

AD0 to AD7:

Address/Data Bus

ANI0 to ANI7:

Analog Input

ANO0, ANO1:

Analog Output

ASCK1, ASCK2

Asynchronous Serial Clock

ASTB:

Address Strobe

Analog Power Supply

REF0

, AV

REF1

Analog Reference Voltage

Analog Ground

BUZ:

Buzzer Clock

EXA:

External Access Status Output

INTP0 to INTP6:

Interrupt from Peripherals

NMI:

Non-maskable Interrupt

P00 to P06:

Port 0

P10 to P17:

Port 1

P20 to P27:

Port 2

P30 to P37:

Port 3

P40 to P47:

Port 4

P50 to P57:

Port 5

P60 to P67:

Port 6

P70 to P72:

Port 7

P80 to P87:

Port 8

P90 to P95:

Port 9

P100 to P103:

Port 10

P120 to P127:

Port 12

P130, P131:

Port 13

PCL:

Programmable Clock

RD:

Read Strobe

RESET:

Reset

RTP0 to RTP7:

Real-time Output Port

RxD1, RxD2:

Receive Data

SCK0 to SCK2:

Serial Clock

SCL0

Note

Serial Clock

SDA0

Note

Serial Data

SI0 to SI2:

Serial Input

SO0 to SO2:

Serial Output

TEST:

Test

TI00, TI01,

TI1, TI2, TI5 to TI8:

Timer Input

TO0 to TO2, TO5 to TO8: Timer Output

TxD1, TxD2:

Transmit Data

Power Supply

Ground

WAIT:

Wait

WR:

Write Strobe

X1, X2:

Crystal (Main System Clock)

XT1, XT2:

Crystal (Subsystem Clock)

Note The SCL0 and SDA0 pins are incorporated only in the

PD784218Y.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

5. BLOCK DIAGRAM

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP6

Programmable
interrupt
controller

Real-time
output port

Timer/event

counter 7

(8 bits)

Timer/event

counter 6

(8 bits)

Timer/event

counter 5

(8 bits)

Timer/event

counter 2

(8 bits)

Timer/event

counter 1

(8 bits)

Timer/event

counter

(16 bits)

Watch timer

Timer/event

counter 8

(8 bits)

Watchdog timer

TI00
TI01

TO0

TI1

TO1

TI2

TO2

TI5/TO5

TI6/TO6

TI7/TO7

TI8/TO8

NMI/INTP2

P03

RTP0 to RTP7

Clock output
control

A/D
converter

PCL

BUZ

REF0

ANI0 to ANI7

D/A
converter

ANO0

REF1

ANO1

78K/IV

CPU core

ROM

RAM

Baud-rate
generator

RxD1/SI1

TxD1/SO1

ASCK1/SCK1

RxD2/SI2

TxD2/SO2

ASCK2/SCK2

SI0/SDA0

Note

SO0
SCK0/SCL0

Note

Bus I/F

UART/IOE1

EXA

ASTB

WR
WAIT

A0 to A7

AD0 to AD7

A8 to A15

A16 to A19

Port 1

P10 to P17

Port 0

P00 to P06

Port 2

P20 to P27

Port 3

P30 to P37

Port 4

P40 to P47

Port 5

P50 to P57

Port 6

P60 to P67

Port 7

P70 to P72

Port 8

P80 to P87

Port 9

P90 to P95

Port 10

P100 to P103

Port 12

P120 to P127

Port 13

P130,P131

Buzzer output

System control

RESET

XT2

XT1

TEST

Clocked
serial
interface

Baud-rate
generator

UART/IOE2

Note SDA0 and SCL0 are incorporated only in the

PD784218Y and support the I

C bus interface.

Remark The internal ROM capacity varies depending on the product.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

6. PIN FUNCTIONS

6.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00

I/O

INTP0

P01

INTP1

P02

INTP2/NMI

P03

INTP3

P04

INTP4

P05

INTP5

P06

INTP6

P10 to P17

Input

ANI0 to ANI7

P20

I/O

RxD1/SI1

P21

TxD1/SO1

P22

ASCK1/SCK1

P23

PCL

P24

BUZ

P25

SI0/SDA0

Note

P26

SO0

P27

SCK0/SCL0

Note

P30

I/O

TO0

P31

TO1

P32

TO2

P33

TI1

P34

TI2

P35

TI00

P36

TI01

P37

EXA

P40 to P47

I/O

AD0 to AD7

Port 4 (P4):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· All pins set in input mode can be connected to on-chip pull-up

resistors by means of software.

· LEDs can be driven directly.

P50 to P57

I/O

A8 to A15

Port 5 (P5):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· All pins set in input mode can be connected to on-chip pull-up

resistors by means of software.

· LEDs can be driven directly.

Note SDA0 and SCL0 are incorporated only in the

PD784218Y.

Port 1 (P1):

· 8-bit input-only port

Port 0 (P0):

· 7-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

Port 2 (P2):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

Port 3 (P3):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

6.1 Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

P60

I/O

A16

P61

A17

P62

A18

P63

A19

P64

P65

P66

WAIT

P67

ASTB

P70

I/O

RxD2/SI2

P71

TxD2/SO2

P72

ASCK2/SCK2

P80 to P87

I/O

A0 to A7

Port 8 (P8):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

· The interrupt control flag (KRIF) is set to 1 when the falling edge is

detected at a pin of this port.

P90 to P95

I/O

Port 9 (P9):

· N-ch open-drain middle-voltage I/O port

· 6-bit I/O port

· Input/output can be specified in 1-bit units.

· LEDs can be driven directly.

P100

I/O

TI5/TO5

P101

TI6/TO6

P102

TI7/TO7

P103

TI8/TO8

P120 to P127

I/O

RTP0 to RTP7

Port 12 (P12):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P130, P131

I/O

ANO0, ANO1

Port 13 (P13):

· 2-bit I/O port

· Input/output can be specified in 1-bit units.

Port 6 (P6):

· 8-bit I/O port

· Input/output can be specified in 1-bit units.

· All pins set in input mode can be connected to on-chip pull-up

resistors by means of software.

Port 7 (P7):

· 3-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

Port 10 (P10):

· 4-bit I/O port

· Input/output can be specified in 1-bit units.

· Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of software.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

6.2 Non-Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TI00

Input

P35

External count clock input to 16-bit timer counter

TI01

P36

Capture trigger signal input to capture/compare register 00

TI1

P33

External count clock input to 8-bit timer counter 1

TI2

P34

External count clock input to 8-bit timer counter 2

TI5

P100/TO5

External count clock input to 8-bit timer counter 5

TI6

P101/TO6

External count clock input to 8-bit timer counter 6

TI7

P102/TO7

External count clock input to 8-bit timer counter 7

TI8

P103/TO8

External count clock input to 8-bit timer counter 8

TO0

Output

P30

16-bit timer output (also used as 14-bit PWM output)

TO1

P31

8-bit timer output (also used as 8-bit PWM output)

TO2

P32

TO5

P100/TI5

TO6

P101/TI6

TO7

P102/TI7

TO8

P103/TI8

RxD1

Input

P20/SI1

Serial data input (UART1)

RxD2

P70/SI2

Serial data input (UART2)

TxD1

Output

P21/SO1

Serial data output (UART1)

TxD2

P71/SO2

Serial data output (UART2)

ASCK1

Input

P22/SCK1

Baud rate clock input (UART1)

ASCK2

P72/SCK2

Baud rate clock input (UART2)

SI0

Input

P25/SDA0

Serial data input (3-wire serial clock I/O0)

SI1

P20/RxD1

Serial data input (3-wire serial clock I/O1)

SI2

P70/RxD2

Serial data input (3-wire serial clock I/O2)

SO0

Output

P26

Serial data output (3-wire serial I/O0)

SO1

P21/TxD1

Serial data output (3-wire serial I/O1)

SO2

P71/TxD2

Serial data output (3-wire serial I/O2)

SDA0

Note

I/O

P25/SI0

Serial data input/output (I

C bus)

SCK0

P27

Serial clock input/output (3-wire serial I/O0)

SCK1

P22/ASCK1

Serial clock input/output (3-wire serial I/O1)

SCK2

P72/ASCK2

Serial clock input/output (3-wire serial I/O2)

SCL0

Note

P27/SCK0

Serial data input/output (I

C bus)

Note Incorporated only in the

PD784218Y.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

6.2 Non-Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

NMI

Input

P02/INTP2

Non-maskable interrupt request input

INTP0

P00

External interrupt request input

INTP1

P01

INTP2

P02/NMI

INTP3

P03

INTP4

P04

INTP5

P05

INTP6

P06

PCL

Output

P23

Clock output (for trimming main system clock and subsystem clock)

BUZ

Output

P24

Buzzer output

RTP0 to RTP7

Output

P120 to P127

Real-time output port that outputs data in synchronization with

trigger

AD0 to AD7

I/O

P40 to P47

Lower address/data bus for expanding memory externally

A0 to A7

Output

P80 to P87

Lower address bus for expanding memory externally

A8 to A15

P50 to P57

Middle address bus for expanding memory externally

A16 to A19

P60 to P63

Higher address bus for expanding memory externally

Output

P64

Strobe signal output for read operation of external memory

P65

Strobe signal output for write operation of external memory

WAIT

Input

P66

To insert wait state(s) when external memory is accessed

ASTB

Output

P67

Strobe output to externally latch address information output to ports

4 through 6 and port 8 to access external memory

EXA

Output

P37

Status signal output during external memory access

RESET

Input

System reset input

Input

Crystal connection for main system clock oscillation

XT1

Input

Crystal connection for subsystem clock oscillation

XT2

ANI0 to ANI7

Input

P10 to P17

Analog voltage input for A/D converter

ANO0, ANO1

Output

P130, P131

Analog voltage output for D/A converter

REF0

To apply reference voltage for A/D converter

REF1

To apply reference voltage for D/A converter

Positive power supply for A/D converter. Connect to V

GND for A/D converter and D/A converter. Connect to V

Positive power supply

GND

TEST

Connect directly to V

or pull down (this pin is for the IC test). For

the pull-down connection, use of a resistor whose resistance is

between 470

and 10 k

is recommended.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

6.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 6-

For the input/output circuit configuration of each type, refer to Figure 6-1.

Table 6-1. Type of Pin Input/Output Circuits and Recommended Connections of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connections of Unused Pins

P00/INTP0

8-N

I/O

Input:

Independently connect to V

via a resistor

P01/INTP1

Output: Leave open

P02/INTP2/NMI

P03/INTP3 to P06/INTP6

P10/ANI0 to P17/ANI7

Input

Connect to V

or V

P20/RxD1/SI1

10-K

I/O

Input:

Independently connect to V

via a resistor

P21/TxD1/SO1

10-L

Output: Leave open

P22/ASCK1/SCK1

10-K

P23/PCL

10-L

P24/BUZ

P25/SDA0

Note

/SI0

10-K

P26/SO0

10-L

P27/SCL0

Note

/SCK0

10-K

P30/TO0 to P32/TO2

12-E

P33/TI1, P34/TI2

8-N

P35/TI00, P36/TI01

10-M

P37/EXA

12-E

P40/AD0 to P47/AD7

5-A

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P70/RxD2/SI2

8-N

P71/TxD2/SO2

10-M

P72/ASCK2/SCK2

8-N

P80/A0 to P87/A7

12-E

P90 to P95

13-D

P100/TI5/TO5

8-N

P101/TI6/TO6

P102/TI7/TO7

P103/TI8/TO8

P120/RTP0 to P127/RTP7

12-E

Note SDA0 and SCL0 are incorporated only in the

PD784218Y.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

7. CPU ARCHITECTURE

7.1 Memory Space

A memory space of 1 MB can be accessed. Mapping of the internal data area (special function registers and

internal RAM) can be specified by the LOCATION instruction. The LOCATION instruction must always be executed

after reset cancellation, and must not be used more than once.

(1) When LOCATION 0H instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784218,

0CD00H to 0FFFFH

00000H to 0CCFFH

PD784218Y

10000H to 3FFFFH

Caution

The following areas that overlap the internal data area of the internal ROM cannot be used when

the LOCATION 0 instruction is executed.

Part Number

Unusable Area

PD784218,

0CD00H to 0FFFFH (13,056 bytes)

PD784218Y

· External memory

The external memory is accessed in external memory expansion mode.

(2) When LOCATION 0FH instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784218,

FCD00H to FFFFFH

00000H to 3FFFFH

PD784218Y

· External memory

The external memory is accessed in external memory expansion mode.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

Figure 7-1. Memory Map of

PD784218, 784218Y

Internal ROM
(52,480 bytes)

(256 bytes)

Special function registers (SFRs)

Internal RAM
(12,800 bytes)

External memory

Note 1

(768 KB)

Note 1

General-purpose
registers (128 bytes)

Macro service control word
area (54 bytes)

Data area (512 bytes)

Program/data area
(12,288 bytes)

CALLF entry
area (2 KB)

Program/data area

Note 3

CALLT table
area (64 bytes)

Vector table area
(64 bytes)

Internal RAM
(12,800 bytes)

External memory

Note 1

(773,376 bytes)

(256 bytes)

Internal ROM
(256 KB)

On execution of

LOCATION 0H instruction

Special function registers (SFRs)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Internal ROM
(196,608 bytes)

Note 2

Notes 1. Accessed in external memory expansion mode.

2. This 13,056-byte area can be used as internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 249,088 bytes, on execution of LOCATION 0FH instruction: 262,144 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

7.2 CPU Registers

7.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit

24-bit address specification registers.

Eight banks of these register sets are available and can be selected by using software or the context switching

function.

The general-purpose registers except the V, U, T, and W registers for address expansion are mapped to the

internal RAM.

Figure 7-2. General-Purpose Register Format

Caution

Registers R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling

the program of the 78K/III Series.

A (R1)

B (R3)

R11

D (R13)

H (R15)

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

X (R0)

C (R2)

R10

E (R12)

L (R14)

AX (RP0)

BC (RP1)

RP2

RP3

VP (RP4)

UP (RP5)

DE (RP6)

HL (RP7)

Parentheses ( ) indicate an absolute name.

8 banks

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

7.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral

hardware, are registers to which special functions are allocated. These registers are mapped to the 256-byte space

of addresses 0FF00H through 0FFFFH

Note

Note On execution of the LOCATION 0H instruction. FFF00H through FFFFFH on execution of the LOCATION

0FH instruction.

Caution

Do not access an address in this area to which no SFR is allocated. If such an address is accessed

by mistake, the

PD784218 may enter a deadlock state. This deadlock state can be cleared only

by inputting the RESET signal.

Table 7-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

Symbol ...............................

Symbol indicating an SFR. This symbol is reserved for NEC's assembler

(RA78K4). It can be used as sfr variable by the #pragma sfr command with the

C compiler (CC78K4).

R/W ....................................

Indicates whether the SFR is read-only, write-only, or read/write.

R/W: Read/write

Read-only

Write-only

Bit units for manipulation ..

Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the

operand sfrp of an instruction. To specify the address of this SFR, describe

an even address.

SFRs that can be manipulated in 1-bit units can be described as the operand

of a bit manipulation instruction.

After reset ..........................

Indicates the status of the register when the RESET signal has been input.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

Table 7-1. Special Function Register (SFR) List (1/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

After Reset

1 bit

8 bits

16 bits

0FF00H

Port 0

R/W

00H

Note 2

0FF01H

Port 1

0FF02H

Port 2

R/W

0FF03H

Port 3

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

0FF07H

Port 7

0FF08H

Port 8

0FF09H

Port 9

0FF0AH

Port 10

P10

0FF0CH

Port 12

P12

0FF0DH

Port 13

P13

0FF10H

16-bit timer counter

TM0

0000H

0FF11H

0FF12H

Capture/compare register 00

CR00

R/W

0FF13H

(16-bit timer/event counter)

0FF14H

Capture/compare register 01

CR01

0FF15H

(16-bit timer/event counter)

0FF16H

Capture/compare control register 0

CRC0

00H

0FF18H

16-bit timer mode control register

TMC0

0FF1AH

16-bit timer output control register

TOC0

0FF1CH

Prescaler mode register 0

PRM0

0FF20H

Port mode 0 register

PM0

FFH

0FF22H

Port mode 2 register

PM2

0FF23H

Port mode 3 register

PM3

0FF24H

Port mode 4 register

PM4

0FF25H

Port mode 5 register

PM5

0FF26H

Port mode 6 register

PM6

0FF27H

Port mode 7 register

PM7

0FF28H

Port mode 8 register

PM8

0FF29H

Port mode 9 register

PM9

0FF2AH

Port mode 10 register

PM10

0FF2CH

Port mode 12 register

PM12

0FF2DH

Port mode 13 register

PM13

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2. Because each port is initialized to input mode after reset, "00H" is not actually read. The output latch

is initialized to "0".

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Table 7-1. Special Function Register (SFR) List (2/4)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

After Reset

1 bit

8 bits

16 bits

0FF30H

Pull-up resistor option register 0

PU0

R/W

00H

0FF32H

Pull-up resistor option register 2

PU2

0FF33H

Pull-up resistor option register 3

PU3

0FF37H

Pull-up resistor option register 7

PU7

0FF38H

Pull-up resistor option register 8

PU8

0FF3AH

Pull-up resistor option register 10

PU10

0FF3CH

Pull-up resistor option register 12

PU12

0FF40H

Clock output control register

CKS

0FF42H

Port function control register

PF2

0FF4EH

Pull-up resistor option register

PUO

0FF50H

8-bit timer counter 1

TM1

TM1W

0000H

0FF51H

8-bit timer counter 2

TM2

0FF52H

Compare register 10 (8-bit timer/event counter 1) CR10 CR1W

R/W

0FF53H

Compare register 20 (8-bit timer/event counter 2) CR20

0FF54H

8-bit timer mode control register 1

TMC1 TMC1W

0FF55H

8-bit timer mode control register 2

TMC2

0FF56H

Prescaler mode register 1

PRM1 PRM1W

0FF57H

Prescaler mode register 2

PRM2

0FF60H

8-bit timer counter 5

TM5 TM5W

0FF61H

8-bit timer counter 6

TM6

0FF62H

8-bit timer counter 7

TM7 TM7W

0FF63H

8-bit timer counter 8

TM8

0FF64H

Compare register 50 (8-bit timer/event counter 5) CR50 CR5W

R/W

0FF65H

Compare register 60 (8-bit timer/event counter 6) CR60

0FF66H

Compare register 70 (8-bit timer/event counter 7) CR70 CR7W

0FF67H

Compare register 80 (8-bit timer/event counter 8) CR80

0FF68H

8-bit timer mode control register 5

TMC5 TMC5W

0FF69H

8-bit timer mode control register 6

TMC6

0FF6AH

8-bit timer mode control register 7

TMC7 TMC7W

0FF6BH

8-bit timer mode control register 8

TMC8

0FF6CH

Prescaler mode register 5

PRM5 PRM5W

0FF6DH

Prescaler mode register 6

PRM6

0FF6EH

Prescaler mode register 7

PRM7 PRM7W

0FF6FH

Prescaler mode register 8

PRM8

0FF70H

Asynchronous serial interface mode register 1

ASIM1

00H

0FF71H

Asynchronous serial interface mode register 2

ASIM2

0FF72H

Asynchronous serial interface status register 1

ASIS1

0FF73H

Asynchronous serial interface status register 2

ASIS2

Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

Data Sheet U12304EJ2V0DS00

PD784218, 784218Y

Table 7-1. Special Function Register (SFR) List (3/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

After Reset

1 bit

8 bits

16 bits

0FF74H

Transmit shift register 1

TXS1

FFH

Receive buffer register 1

RXB1

0FF75H

Transmit shift register 2

TXS2

Receive buffer register 2

RXB2

0FF76H

Baud rate generator control register 1

BRGC1

R/W

00H

0FF77H

Baud rate generator control register 2

BRGC2

0FF7AH

Oscillation mode select register

0FF80H

A/D converter mode register

ADM

0FF81H

A/D converter input select register

ADIS

0FF83H

A/D conversion result register

ADCR

Undefined

0FF84H

D/A conversion value setting register 0

DACS0

R/W

00H

0FF85H

D/A conversion value setting register 1

DACS1

0FF86H

D/A converter mode register 0

DAM0

0FF87H

D/A converter mode register 1

DAM1

0FF88H

ROM correction control register

CORC

0FF89H

ROM correction address pointer H

CORAH

0FF8AH

ROM correction address pointer L

CORAL

0000H

0FF8BH

0FF8CH

External bus type select register

EBTS

00H

0FF8DH

External access status enable register

EXAE

0FF90H

Serial operation mode register 0

CSIM0

0FF91H

Serial operation mode register 1

CSIM1

0FF92H

Serial operation mode register 2

CSIM2

0FF94H

Serial I/O shift register 0

SIO0

0FF95H

Serial I/O shift register 1

SIO1

0FF96H

Serial I/O shift register 2

SIO2

0FF98H

Real-time output buffer register L

RTBL

0FF99H

Real-time output buffer register H

RTBH

0FF9AH

Real-time output port mode register

RTPM

0FF9BH

Real-time output port control register

RTPC

0FF9CH

Watch timer mode control register

WTM

0FFA0H

External interrupt rising edge enable register

EGP0

0FFA2H

External interrupt falling edge enable register

EGN0

0FFA8H

In-service priority register

ISPR

0FFA9H

Interrupt select control register

SNMI

R/W

0FFAAH

Interrupt mode control register

IMC

80H

0FFACH

Interrupt mask flag register 0L

MK0L MK0

FFFFH

0FFADH

Interrupt mask flag register 0H

MK0H

0FFAEH

Interrupt mask flag register 1L

MK1L MK1

0FFAFH

Interrupt mask flag register 1H

MK1H

0FFB0H

C bus control register

Note 2

IICC0

00H

0FFB2H

Prescaler mode register for serial clock

SRPM0

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

PD784218Y only

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Table 7-1. Special Function Register (SFR) List (4/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

After Reset

1 bit

8 bits

16 bits

0FFB4H

Slave address register

SVA0

R/W

00H

0FFB6H

C bus status register

Note 2

IICS0

0FFB8H

Serial shift register

IIC0

R/W

0FFC0H

Standby control register

STBC

30H

0FFC2H

Watchdog timer mode register

WDM

00H

0FFC4H

Memory expansion mode register

20H

0FFC7H

Programmable wait control register 1

PWC1

AAH

0FFCEH

Clock status register

PCS

32H

0FFCFH

Oscillation stabilization time specification register

OSTS

R/W

00H

0FFD0H to

External SFR area

0FFDFH

0FFE0H

Interrupt control register (INTWDTM)

WDTIC

43H

0FFE1H

Interrupt control register (INTP0)

PIC0

0FFE2H

Interrupt control register (INTP1)

PIC1

0FFE3H

Interrupt control register (INTP2)

PIC2

0FFE4H

Interrupt control register (INTP3)

PIC3

0FFE5H

Interrupt control register (INTP4)

PIC4

0FFE6H

Interrupt control register (INTP5)

PIC5

0FFE7H

Interrupt control register (INTP6)

PIC6

0FFE8H

Interrupt control register (INTIIC0/INTCSI0)

CSIIC0

0FFE9H

Interrupt control register (INTSER1)

SERIC1

0FFEAH

Interrupt control register (INTSR1/INTCSI1)

SRIC1

0FFEBH

Interrupt control register (INTST1)

STIC1

0FFECH

Interrupt control register (INTSER2)

SERIC2

0FFEDH

Interrupt control register (INTSR2/INTCSI2)

SRIC2

0FFEEH

Interrupt control register (INTST2)

STIC2

0FFEFH

Interrupt control register (INTTM3)

TMIC3

0FFF0H

Interrupt control register (INTTM00)

TMIC00

0FFF1H

Interrupt control register (INTTM01)

TMIC01

0FFF2H

Interrupt control register (INTTM1)

TMIC1

0FFF3H

Interrupt control register (INTTM2)

TMIC2

0FFF4H

Interrupt control register (INTAD)

ADIC

0FFF5H

Interrupt control register (INTTM5)

TMIC5

0FFF6H

Interrupt control register (INTTM6)

TMIC6

0FFF7H

Interrupt control register (INTTM7)

TMIC7

0FFF8H

Interrupt control register (INTTM8)

TMIC8

0FFF9H

Interrupt control register (INTWT)

WTIC

0FFFAH

Interrupt control register (INTKR)

KRIC

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

PD784218Y only

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Table 8-1. Port Functions

Port Name

Pin Name

Function

Specification of Pull-up Resistor

Connection by Software

Port 0

P00 to P06

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 1

P10 to P17

· Input port

Port 2

P20 to P27

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 3

P30 to P37

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 4

P40 to P47

· Can be set in input or output mode in 1-bit units

Can be specified in 1-port units

· Can directly drive LEDs

Port 5

P50 to P57

· Can be set in input or output mode in 1-bit units

Can be specified in 1-port units

· Can directly drive LEDs

Port 6

P60 to P67

· Can be set in input or output mode in 1-bit units

Can be specified in 1-port units

Port 7

P70 to P72

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 8

P80 to P87

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 9

P90 to P95

· N-ch open-drain I/O port

· Can be set in input or output mode in 1-bit units

· Can directly drive LEDs

Port 10

P100 to P103

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 12

P120 to P127

· Can be set in input or output mode in 1-bit units

Can be specified in 1-bit units

Port 13

P130, P131

· Can be set in input or output mode in 1-bit units

8.2 Clock Generator

An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider.

If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider

to reduce the current consumption.

Figure 8-2. Clock Generator Block Diagram

XT2

XT1

STOP, bit 2 of standby
control register (STBC)
(MCK) = 1 when
subsystem clock is
selected as CPU clock

Main system
clock
oscillator

IDLE
controller

Subsystem
clock
oscillator

Watch timer,
clock output
function

Clock to
peripheral
hardware

CPU
clock
(f

CPU

)

Frequency

divider

Prescaler

STOP,
IDLE
controller

HALT
controller

Selector

Internal system
clock (f

CLK

)

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Figure 8-3. Example of Using Main System Clock Oscillator

Figure 8-4. Example of Using Subsystem Clock Oscillator

Caution

When using the main system clock and subsystem clock oscillator, wire as following in the area

enclosed by the broken lines in Figures 8-3 and 8-4 to avoid an adverse effect from wiring

capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor the same potential as V

. Do not

ground the capacitor to a ground pattern in which a high current flows.

Do not fetch signals from the oscillator.

Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing

current consumption.

External
clock

PD74HCU04

Crystal resonator
or
ceramic resonator

(1) Crystal/ceramic oscillation

(2) External clock

32.768

kHz

XT2

XT1

XT2

XT1

External
clock

PD74HCU04

(1) Crystal oscillation

(2) External clock

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

8.3 Real-Time Output Port

The real-time output function is to transfer data preset in the real-time output buffer register to the output latch

as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device.

The pins that output the data to the external device constitute a port called a real-time output port.

Because the real-time output port can output signals without jitter, it is ideal for controlling stepper motors, etc.

Figure 8-5. Block Diagram of Real-Time Output Port

Internal bus

RTPOE

BYTE

EXTR

Output trigger
controller

Real-time output port
control register (RTPC)

Real-time output
port mode register
(RTPM)

Real-time output port output latch

RTP7······································ RTP0

Higher 4 bits of
real-time output
buffer register
(RTBH)

Lower 4 bits of
real-time output
buffer register
(RTBL)

INTP2TRG

INTTM1

INTTM2

Port 12 output latch

P127······································ P120

P12n/RTPn pin output (n = 0 to 7)

P127/ P120/
RTP7 RTP0

······································

RTPOE bit

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Figure 8-6. Block Diagram of Timer/Event Counters

16-bit timer/event counter

/16

INTTM3

TI01

TI00

Edge detector

16-bit timer counter (TM0)

16-bit capture/compare register 00

(CR00)

16-bit capture/compare register 01

(CR01)

Clear

INTTM00

INTTM01

TO0

Selector

Output controller

8-bit timer/event counter 1, 5, 7

TIn

8-bit timer counter n

(TMn)

8-bit compare register n0

(CRn0)

Clear

OVF

INTTMn + 1

INTTMn

TOn

Edge detector

Output

controller

Selector

Remarks 1. n = 1, 5, 7

2. OVF: Overflow flag

8-bit timer/event counter 2, 6, 8

TIn

TMn1

8-bit timer counter n

(TMn)

8-bit compare register n0

(CRn0)

Clear

OVF

INTTMn

TOn

Edge detector

Output

controller

Selector

Remarks 1. n = 2, 6, 8

2. OVF: Overflow flag

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

8.5 A/D Converter

An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with an

A/D converter with a resolution of 8 bits and 8 channels (ANI0 through ANI7).

This A/D converter is of successive approximation type and the result of conversion is stored in the 8-bit A/D

conversion result register (ADCR).

The A/D converter can be started in the following two ways:

· Hardware start

Conversion is started by trigger input (P03).

· Software start

Conversion is started by setting the A/D converter mode register (ADM).

One analog input channel is selected from ANI0 through ANI7 for A/D conversion. When A/D conversion is started

by means of hardware start, conversion is stopped after it has been completed. When conversion is started by

means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed,

an interrupt request (INTAD) is generated.

Figure 8-7. A/D Converter Block Diagram

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Sample & hold circuit

Series resistor string

Voltage comparator

Successive approximation
register (SAR)

A/D conversion result register

(ADCR)

Controller

Edge
detector

INTP3/P03

INTAD

INTP3

REF0

Internal bus

Selector

Tap selector

Edge
detector

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

8.7 Serial Interfaces

Three independent serial interface channels are provided.

· Asynchronous serial interface (UART)/3-wire serial I/O (IOE)

· Clocked serial interface (CSI)

3-wire serial I/O (IOE)

C bus interface (I

C) (

PD784218Y Subseries only)

Therefore, communication with an external system and local communication within the system can be simultaneously

executed (refer to Figure 8-9).

Figure 8-9. Example of Serial Interface

(a) UART + I

(b) UART + 3-wire serial I/O

Note Handshake line

PD784218 (master)

RS-232C

driver/receiver

[UART]

Port

RxD2

TxD2

PD753106 (slave)

SCK

Port

INT

[3-wire serial I/O]

Note

SO1

SI1

SCK1

INTPm

Port

PD4711A

[UART]

RS-232C

driver/receiver

RxD1

TxD1

RS-232C

driver/receiver

Port

RxD2

TxD2

Port

SDA0

SCL0

SDA

SCL

SDA

SCL

LCD

PD4711A

PD784218Y (master)

PD780078Y (slave)

PD780308Y (slave)

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

8.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two channels of serial interfaces for which an asynchronous serial interface mode and 3-wire serial I/O mode

can be selected are provided.

(1) Asynchronous serial interface mode

In this mode, data of 1 byte following the start bit is transmitted or received.

Because an on-chip baud rate generator is provided, a wide range of baud rates can be set.

Moreover, the clock input to the ASCK pin can be divided to define a baud rate.

When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can also

be obtained.

Figure 8-10. Block Diagram When in Asynchronous Serial Interface Mode

Internal bus

Receive buffer register
1, 2 (RXB1, RXB2)

Receive shift register
1, 2 (RX1, RX2)

Transmit shift register
1, 2 (TXS1, TXS2)

Receive control
parity check

Transmit control
parity added

RxD1, RxD2

TxD1, TxD2

ASCK1, ASCK2

Baud rate generator

INTSR1,
INTSR2

INTST1,
INTST2

Selector

5-bit counter

transmit/receive clock generation

to f

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

8.7.2 Clocked serial interface (CSI)

In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in

synchronization with this clock.

(1) 3-wire serial I/O mode

This mode is to communicate with devices having the conventional clocked serial interface.

Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial

data (SI0 and SO0) lines.

Generally, a handshake line is necessary to check the reception status.

Figure 8-12. Block Diagram When in 3-Wire Serial I/O Mode

SI0

SO0

SCK0

INTCSI0

TO2
f

/16

Internal bus

Interrupt
generator

Selector

Serial clock
counter

Serial clock
controller

Serial I/O shift register 0

(SIO0)

(2) I

C bus (Inter IC) bus mode (multi-master supporting)

This mode is for communication with devices conforming to the I

C bus format.

This mode is for transferring 8-bit data between two or more devices by using two lines: a serial clock (SCL0)

and a serial data bus (SDA0).

During transfer, a "start condition", "data", and "stop condition" can be output onto the serial data bus. During

reception, this data is automatically detected by hardware.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

8.9 Buzzer Output Function

Clocks of the following frequencies can be output as buzzer output.

· 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (@ 12.5 MHz operation with main system clock)

Figure 8-15. Block Diagram of Buzzer Output Function

Output controller

BUZ

Selector

8.10 Edge Detection Function

The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 through INTP6) are used not only to input interrupt

requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge

of the input signal, they have a function to detect an edge. Moreover, a noise reduction function is also provided

to prevent erroneous detection due to noise.

Pin Name

Detectable Edge

Noise Reduction

NMI

Either or both of rising and falling edges

By analog delay

INTP0 to INTP6

8.11 Watch Timer

The watch timer has the following functions:

· Watch timer

· Interval timer

The watch timer and interval timer functions can be used at the same time.

(1) Watch timer

The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds

using the 32.768 kHz subsystem clock.

(2) Interval timer

The interval timer generates an interrupt request (INTTM3) at preset time intervals.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

9. INTERRUPT FUNCTION

The three types of servicing in response to an interrupt request shown in Table 9-1 can be selected by program.

Table 9-1. Servicing of Interrupt Request

Servicing Mode

Servicing Means

Servicing

Contents of PC and PSW

Vectored interrupt

Software

Branches and executes servicing routine

Saves to and restores

(servicing is arbitrary)

from stack

Context switching

Automatically switches register bank,

Saves to or restores from

branches and executes servicing routine

fixed area in register bank

(servicing is arbitrary)

Macro service

Firmware

Executes data transfer between memory

Retained

and I/O (servicing is fixed)

9.1 Interrupt Sources

Table 9-2 shows the interrupt sources available. As shown, interrupts are generated by 29 sources, execution

of the BRK instruction, BRKCS instruction, or an operand error.

The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt

servicing, and so that which of the two or more interrupts that simultaneously occur should be serviced first can be

decided. When the macro service function is used, however, nesting always proceeds (i.e., is not held pending).

The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having

the same priority, are simultaneously generated (refer to Table 9-2).

Table 9-2. Interrupt Sources (1/2)

Type

Default

Source

Internal/

Macro

Priority

Name

Trigger

External

Service

Software

BRK instruction

Instruction execution

BRKCS instruction

Instruction execution

Operand error

If result of exclusive OR between operands
byte and byte is not FFH when MOV STBC,
#byte instruction, MOV WDM, #byte instruction,
or LOCATION instruction is executed

Non-maskable

NMI

Pin input edge detection

External

INTWDT

Overflow of watchdog timer

Internal

Maskable

0 (highest)

INTWDTM

Overflow of watchdog timer

Internal

INTP0

Pin input edge detection

External

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

INTIIC0

End of I

C bus transfer by CSI0

Internal

INTCSI0

End of 3-wire transfer by CSI0

INTSER1

Occurrence of UART reception error in ASI1

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Table 9-2. Interrupt Sources (2/2)

Type

Default

Source

Internal/

Macro

Priority

Name

Trigger

External

Service

Maskable

INTSR1

End of UART reception by ASI1

Internal

INTCSI1

End of 3-wire transfer by CSI1

INTST1

End of UART transmission by ASI1

INTSER2

Occurrence of UART reception error in ASI2

INTSR2

End of UART reception by ASI2

INTCSI2

End of 3-wire transfer by CSI2

INTST2

End of UART transmission by ASI2

INTTM3

Reference time interval signal from watch timer

INTTM00

Signal indicating coincidence between 16-bit
timer counter and capture/compare register
(CR00)

INTTM01

Signal indicating coincidence between 16-bit
timer counter and capture/compare register
(CR01)

INTTM1

Occurrence of coincidence signal of 8-bit
timer/event counter 1

INTTM2

Occurrence of coincidence signal of 8-bit
timer/event counter 2

INTAD

End of conversion by A/D converter

INTTM5

Occurrence of coincidence signal of 8-bit
timer/event counter 5

INTTM6

Occurrence of coincidence signal of 8-bit
timer/event counter 6

INTTM7

Occurrence of coincidence signal of 8-bit
timer/event counter 7

INTTM8

Occurrence of coincidence signal of 8-bit
timer/event counter 8

INTWT

Overflow of watch timer

26 (lowest)

INTKR

Detection of falling edge of port 8

External

Remarks 1. ASI: Asynchronous Serial Interface

CSI: Clocked Serial Interface

2. Two watchdog timer interrupt sources, non-maskable interrupt (INTWDT) and maskable interrupt

(INTWDTM), are available and only one of those can be selected.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

9.2 Vectored Interrupt

Execution branches to a servicing routine by using the memory contents of a vector table address corresponding

to the interrupt source as the address of the branch destination.

So that the CPU performs interrupt servicing, the following operations are performed:

· On branching: Saves the status of the CPU (contents of PC and PSW) to stack

· On returning:

Restores the status of the CPU (contents of PC and PSW) from stack

To return to the main routine from an interrupt service routine, the RETI instruction is used.

The branch destination address is in a range of 0 to FFFFH.

Table 9-3. Vector Table Address

Interrupt Source

Vector Table Address

Interrupt Source

Vector Table Address

BRK instruction

003EH

INTST1

001CH

TRAP0 (operand error)

003CH

INTSER2

001EH

NMI

0002H

INSR2

0020H

INTWDT (non-maskable)

0004H

INTCSI2

INTWDTM (maskable)

0006H

INTST2

0022H

INTP0

0008H

INTTM3

0024H

INTP1

000AH

INTTM00

0026H

INTP2

000CH

INTTM01

0028H

INTP3

000EH

INTTM1

002AH

INTP4

0010H

INTTM2

002CH

INTP5

0012H

INTAD

002EH

INTP6

0014H

INTTM5

0030H

INTIIC0

0016H

INTTM6

0032H

INTCSI0

INTTM7

0034H

INTSER0

0018H

INTTM8

0036H

INTSR1

001AH

INTWT

0038H

INTCSI1

INTKR

003AH

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

9.3 Context Switching

When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register

bank is selected by hardware. Context switching is a function that branches execution to a vector address stored

in advance in the register bank, and stacks the current contents of the program counter (PC) and program status

word (PSW) to the register bank.

The branch address is in a range of 0 to FFFFH.

Figure 9-1. Context Switching Operation When Interrupt Request Is Generated

9.4 Macro Service

This function is to transfer data between memory and a special function register (SFR) without intervention by

the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers

data without loading it.

Because this function does not save or restore the status of the CPU, or load data, data can be transferred at

high speeds.

Figure 9-2. Macro Service

0000B
<7> Transfer

PC19-16

PC15-0

<6> Exchange

<5> Save

<2> Save

Temporary register

<1> Save

PSW

<3> Switching of register bank
(RBS0 to RBS2

(0 to 7)

(bits 8 through 11
of temporary register)

<4> RSS

CPU

Memory

SFR

Macro service

controller

Read

Write

Read

Internal bus

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

9.5 Application Example of Macro Service

(1) Serial interface transmission

Transmit data storage buffer (memory)

Data n

Data n 1

Data 1

Data 2

Internal bus

Transmit shift register

TXS1, TXS2 (SFR)

Transmit control

TxD1, TxD2

INTST1, INTST2

Each time macro service requests INTST1 and INTST2 are generated, the next transmit data is transferred from

memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit

data storage buffer has become empty), vectored interrupt requests INTST1 and INTST2 are generated.

(2) Serial interface reception

Receive data storage buffer (memory)

Data n

Data n 1

Data 1

Data 2

Internal bus

Receive shift register

RXB1, RXB2 (SFR)

Reception control

INTSR1, INTSR2

RxD1, RxD2

Receive buffer register

Each time macro service requests INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1

and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage

buffer has become full), vectored interrupt requests INTSR1 and INTSR2 are generated.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

10.1 Memory Expansion

External program memory and data memory can be connected in two stages: 256 KB and 1 MB.

To connect the external memory, ports 4 through 6 and port 8 are used.

The external memory can be connected in the following two modes:

· Multiplexed bus mode: The external memory is connected by using a time-division address/data bus. The

number of ports used when the external memory is connected can be reduced in this

mode.

· Separate bus mode:

The external memory is connected by using an address bus and data bus independent

of each other. Because an external latch circuit is not necessary, this mode is useful

for reducing the number of components and mounting area on the printed wiring board.

10.2 Programmable Wait

Wait state(s) can be inserted to the memory space (00000H through FFFFFH) while the RD and WR signals are

active.

In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address

decode time.

10.3 External Access Status Function

An active-low external access status signal is output from the P37/EXA pin. This signal informs other devices

that are connected with external buses of the external access status, prohibits other devices from outputting data

to an external bus, and enables receive operations.

The external access status signal is output during external accessing.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

11. STANDBY FUNCTION

This function is to reduce the power consumption of the chip, and can be used in the following modes:

HALT mode:

Stops supply of the operating clock to the CPU. This mode is used

in combination with the normal operation mode for intermittent operation

to reduce the average power consumption.

IDLE mode:

Stops the entire system with the oscillator continuing operation. The

power consumption in this mode is close to that in the STOP mode.

However, the time required to restore the normal program operation

from this mode is almost the same as that from the HALT mode.

STOP mode:

Stops the main system clock and thereby stops all the internal

operations of the chip. Consequently, the power consumption is

minimized with only leakage current flowing.

Low power consumption mode:

The main system clock is stopped with the subsystem clock used as

the system clock. The CPU can operate on the subsystem clock to

reduce the current consumption.

Low power consumption HALT mode: This is a standby function in the low power consumption mode and

stops the operation clock of the CPU, to reduce the power consumption

of the entire system.

Low power consumption IDLE mode:

This is a standby function in the low power consumption mode and

stops the entire system except the oscillator, to reduce the power

consumption of the entire system.

These modes are programmable.

The macro service can be started from the HALT mode or low power consumption HALT mode. After macro

service processing is executed, the system returns to the HALT mode again.

The transition of the standby status is shown in Figure 11-1.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Figure 11-1. Standby Function State Transition

Normal

operation

(Main system

clock

operation)

Macro

service

HALT

(Standby)

IDLE

(Standby)

Low power

consumption

mode

(Subsystem

clock operation)

Low

power

consumption

HALT mode

(Standby)

Low power

consumption

IDLE mode

(Standby)

STOP

(Standby)

Macro service request

One time processing ends

Macro service ends

Macro service request

One time processing ends

Interrupt request

Note 1

RESET input

HALT set

IDLE set

NMI, INTP0 to INTP6 input, INTWT,

key return interrupt

Note 2

STOP set

Low power consumption
IDLE mode set

RESET input

Low power

consumption mode set

Return to normal operation

Low power consumption HALT mode set

RESET input

Interrupt request

Note 1

Interrupt
request for
masked interrupt

Interrupt
request for
masked
interrupt

Interrupt
request
for
masked
interrupt

Macro

service

Macro service request

One time processing ends

Macro service ends

One time processing ends

NMI, INTP0 to INTP6 input,
INTWT, key return interrupt

Note 2

Wait for

stable

oscillation

RESET input

NMI, INTP0 to INTP6 input,

INTWT, key return interrupt

Note 2

RESET input

Oscillation stabilization time ends

Notes 1. Only unmasked interrupt requests

2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87)

Remark NMI is valid only for an external input.

The watchdog timer cannot be used for the release of standby (HALT mode/STOP mode/IDLE mode).

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

12. RESET FUNCTION

When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset).

During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current

consumption of the entire system can be reduced.

When the RESET signal goes high, the reset status is cleared, the oscillation stabilization time (84.0 ms at 12.5

MHz operation) elapses, the contents of the reset vector table are set to the program counter (PC), execution

branches to an address set to the PC, and program execution is started from that branch address. Therefore, the

program can be reset and started from any address.

Figure 12-1. Oscillation of Main System Clock During Reset Period

Oscillation is unconditionally
stopped during reset period

Oscillation stabilization time

Main system clock
oscillator

CLK

RESET input

The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise.

Figure 12-2. Acknowledgement of Reset Signal

Analog delay

Analog
delay

Oscillation
stabilization
time

RESET input

Internal reset signal

Internal clock

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

14. INSTRUCTION SET

(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC,

CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC

Table 14-1. Instruction List by 8-Bit Addressing

Second Operand

#byte

saddr

sfr

!addr16

mem

[WHL+]

None

Note 2

saddr'

!!addr24

[saddrp]

PSWL

[WHL]

First Operand

[%saddrg]

PSWH

(MOV)

MOV

(MOV)

Note 6

MOV

(MOV)

MOV

(MOV)

ADD

Note 1

(XCH)

XCH

(XCH)

Note 6

(XCH)

XCH

(XCH)

(ADD)

Note 1

(ADD)

Note 1

(ADD)

Notes 1,6

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 1

MOV

(MOV)

MOV

ROR

Note 3

MULU

ADD

Note 1

(XCH)

XCH

DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

INC

DEC

saddr

MOV

(MOV)

Note 6

MOV

INC

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

XCH

DEC

ADD

Note 1

DBNZ

sfr

MOV

PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

!addr16

MOV

(MOV)

MOV

!!addr24

ADD

Note 1

mem

MOV

[saddrp]

ADD

Note 1

[%saddrg]

mem3

ROR4

ROL4

MOV

PSWL

PSWH

B, C

DBNZ

STBC, WDM

MOV

[TDE+]

(MOV)

MOVBK

Note 5

[TDE]

(ADD)

Note 1

MOVM

Note 4

Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as those of ADD.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as those of ROR.

4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as those of MOVM.

5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as those of

MOVBK.

6. The code length of some instructions having saddr2 as saddr in this combination is short.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as

rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,

POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 14-2. Instruction List by 16-Bit Addressing

Second Operand

#word

saddrp

sfrp

!addr16

mem

[WHL+]

byte

None

Note 2

rp'

saddrp'

!!addr24

[saddrp]

First Operand

[%saddrg]

(MOVW)

(MOVW) (MOVW)

Note 3

MOVW

(MOVW)

MOVW

(MOVW)

ADDW

Note 1

(XCHW)

(XCHW) (XCHW)

Note 3

(XCHW)

XCHW

(XCHW)

(ADD)

Note 1

(ADDW)

Note 1

(ADDW)

Notes 1, 3

(ADDW)

Note 1

MOVW

(MOVW)

MOVW

SHRW

MULW

Note 4

ADDW

Note 1

(XCHW)

XCHW

SHLW

INCW

(ADDW)

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

DECW

saddrp

MOVW

(MOVW)

Note 3

MOVW

INCW

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

XCHW

DECW

ADDW

Note 1

sfrp

MOVW

PUSH

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

POP

!addr16

MOVW

(MOVW)

MOVW

MOVTBLW

!!addr24

mem

MOVW

[saddrp]

[%saddrg]

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE+]

(MOVW)

SACW

byte

MACW

MACSW

Notes 1. The operands of SUBW and CMPW are the same as those of ADDW.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The code length of some instructions having saddrp2 as saddrp in this combination is short.

4. The operands of MULUW and DIVUX are the same as those of MULW.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

15. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

0.3 to +6.5

0.3 to V

+ 0.3

0.3 to V

+ 0.3

REF0

A/D converter reference voltage input

0.3 to V

+ 0.3

REF1

D/A converter reference voltage input

0.3 to V

+ 0.3

Input voltage

Other than P90 to P95

0.3 to V

+ 0.3

P90 to P95 N-ch open drain

0.3 to +12

Analog input voltage

Analog input pin

0.3 to AV

REF0

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current, low

Per pin

Total of P2, P4 to P8

Total of P0, P3, P9, P10, P12, P13

Output current, high

Per pin

Total of P2, P4 to P8

Total of P0, P3, P9, P10, P12, P13

Operating ambient

40 to +85

temperature

Storage temperature

stg

65 to +150

Caution

Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Main System Clock Oscillator Characteristics (T

= 40 to +85

Resonator Recommended Circuit

Parameter

Test Conditions

MIN.

TYP.

MAX.

Unit

Ceramic

Oscillation

4.5 V

5.5 V

12.5

MHz

resonator

frequency (f

)

or crystal

resonator

2.7 V

< 4.5 V

6.25

2.2 V

< 2.7 V

External

X1 input frequency

4.5 V

5.5 V

MHz

clock

)

2.7 V

< 4.5 V

12.5

2.2 V

< 2.7 V

6.25

X1 input high-/low-

250

level width (t

WXH

, t

WXL

)

X1 input rise/fall

4.5 V

5.5 V

time (t

, t

)

2.7 V

< 4.5 V

2.2 V

< 2.7 V

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor the same potential as V

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

X1 V

PD74HCU04

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Subsystem Clock Oscillator Characteristics (T

= 40 to +85

Resonator Recommended Circuit

Parameter

Test Conditions

MIN.

TYP.

MAX.

Unit

Crystal

Oscillation

32.768

kHz

resonator

frequency (f

)

Oscillation

4.5 V

5.5 V

1.2

stabilization time

Note

2.2 V

< 4.5 V

External

XT1 input

kHz

clock

frequency (f

)

XT1 input high-/low-

level width (t

XTH

, t

XTL

)

Note Time required to stabilize oscillation after the power supply voltage (V

) is applied.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor the same potential as V

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

XT2

XT1

XT2

XT1

PD74HCU04

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

DC Characteristics (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V) (1/2)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input voltage, low

IL1

Note 1

0.3V

IL2

Total for P00 to P06, P20, P22, P33, P34, P70,

0.2V

P72, P100 to P103, RESET

IL3

P90 to P95 (N-ch open drain)

0.3V

IL4

Total for P10 to P17, P130, P131

0.3V

IL5

Total for X1, X2, XT1, XT2

0.2V

IL6

P25, P27

0.3V

Input voltage, high

IH1

Note 1

0.7V

IH2

Total for P00 to P06, P20, P22, P33, P34, P70,

0.8V

P72, P100 to P103, RESET

IH3

P90 to P95 (N-ch open drain)

0.7V

IH4

Total for P10 to P17, P130, P131

0.7V

IH5

Total for X1, X2, XT1, XT2

0.8V

IH6

P25, P27

0.7V

Output voltage, low

OL1

For pins other than P40 to

= 4.5 to 5.5 V

0.4

P47, P50 to P57, P90 to P95

= 1.6 mA

Note 2

Total for P40 to P47,

= 4.5 to 5.5 V

1.0

P50 to P57

= 8 mA

Note 2

P90 to P95 I

= 15 mA

Note 2

= 4.5 to 5.5 V

0.8

2.0

OL2

= 400

Note 2

0.5

Output voltage, high

OH1

= 1 mA

Note 2

= 4.5 to 5.5 V V

1.0

= 100

Note 2

0.5

Input leakage current, low

LIL1

= 0 V

Except X1, X2,

XT1, XT2

LIL2

X1, X2, XT1, XT2

Input leakage current, high

LIH1

= V

Except X1, X2,

XT1, XT2

LIH2

X1, X2, XT1, XT2

Output leakage current, low

LOL1

OUT

= 0 V

Output leakage current, high

LOH1

OUT

= V

Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,

P120 to P127

2. Per pin

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

DC Characteristics (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V) (2/2)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Supply current

DD1

Operation

= 12.5 MHz

mode

= 6 MHz, 2.7 V

3.3 V

= 3 MHz, 2.2 V

< 2.7 V

DD2

HALT mode

= 12.5 MHz

= 6 MHz, 2.7 V

3.3 V

= 3 MHz, 2.2 V

< 2.7 V

1.3

3.5

DD3

IDLE mode

= 12.5 MHz

2.5

= 6 MHz, 2.7 V

3.3 V

0.5

1.3

= 3 MHz, 2.2 V

< 2.7 V

0.3

0.9

DD4

Operation

= 32 kHz

100

200

mode

Note

= 32 kHz, 2.7 V

3.3 V

110

= 32 kHz, 2.2 V

< 2.7 V

100

DD5

HALT

= 32 kHz

160

mode

Note

= 32 kHz, 2.7 V

3.3 V

= 32 kHz, 2.2 V

< 2.7 V

DD6

IDLE

= 32 kHz

150

mode

Note

= 32 kHz, 2.7 V

3.3 V

= 32 kHz, 2.2 V

< 2.7 V

Data retention voltage

DDDR

HALT, IDLE modes

2.2

5.5

Data retention current

DDDR

STOP mode

= 2.2 V

= 4.5 to 5.5 V

Pull-up resistor

= 0 V

100

Note When main system clock is stopped

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

AC Characteristics (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Cycle time

CYK

4.5 V

5.5 V

2.7 V

< 4.5 V

160

2.2 V

< 2.7 V

320

Address setup time (to ASTB

)

SAST

= 5.0 V

(0.5 + a) T 11

= 3.0 V

(0.5 + a) T 15

Address hold time (from ASTB

)

HSTLA

= 5.0 V

0.5T 19

= 3.0 V

0.5T 24

ASTB high-level width

WSTH

= 5.0 V

(0.5 + a) T 17

= 3.0 V

(0.5 + a) T 40

Address hold time (from RD

)

HRA

= 5.0 V

0.5T 14

= 3.0 V

0.5T 14

Delay time from address to RD

DAR

= 5.0 V

(1 + a) T 24

= 3.0 V

(1 + a) T 24

Address float time (from RD

)

FRA

Data input time from address

DAID

= 5.0 V

(2.5 + a + n) T 37

= 3.0 V

(2.5 + a + n) T 52

Data input time from ASTB

DSTID

= 5.0 V

(2 + n) T 35

= 3.0 V

(2 + n) T 50

Data input time from RD

DRID

= 5.0 V

(1.5 + n) T 40

= 3.0 V

(1.5 + n) T 50

Delay time from ASTB

to RD

DSTR

= 5.0 V

0.5T 9

= 3.0 V

0.5T 9

Data hold time (from RD

)

HRID

Address active time from RD

DRA

= 5.0 V

0.5T 2

= 3.0 V

0.5T 12

Delay time from RD

to ASTB

DRST

= 5.0 V

0.5T 9

= 3.0 V

0.5T 9

RD low-level width

WRL

= 5.0 V

(1.5 + n) T 25

= 3.0 V

(1.5 + n) T 30

Delay time from address to WR

DAW

= 5.0 V

(1 + a) T 24

= 3.0 V

(1 + a) T 24

Address hold time (from WR

)

HWA

= 5.0 V

0.5T 14

= 3.0 V

0.5T 14

Delay time from ASTB

to data

DSTOD

= 5.0 V

0.5T + 15

output

= 3.0 V

0.5T + 20

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise 0

n: Number of waits (n

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

AC Characteristics

(2) External wait timing

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input time from address to

DAWT

= 5.0 V

(2 + a) T 40

WAIT

= 3.0 V

(2 + a) T 60

Input time from ASTB

DSTWT

= 5.0 V

1.5T 40

WAIT

= 3.0 V

1.5T 60

Hold time from ASTB

HSTWT

= 5.0 V

(0.5 + n) T + 5

WAIT

= 3.0 V

(0.5 + n) T + 10

Delay time from ASTB

DSTWTH

= 5.0 V

(1.5 + n) T 40

WAIT

= 3.0 V

(1.5 + n) T 60

Input time from RD

to WAIT

DRWTL

= 5.0 V

T 40

= 3.0 V

T 60

Hold time from RD

to WAIT

HRWT

= 5.0 V

nT + 5

= 3.0 V

nT + 10

Delay time from RD

to WAIT

DRWTH

= 5.0 V

(1 + n) T 40

= 3.0 V

(1 + n) T 60

Input time from WAIT

to data

DWTID

= 5.0 V

0.5T 5

= 3.0 V

0.5T 10

Delay time from WAIT

to RD

DWTR

= 5.0 V

0.5T

= 3.0 V

0.5T

Delay time from WAIT

to WR

DWTW

= 5.0 V

0.5T

= 3.0 V

0.5T

Input time from WR

to WAIT

DWWTL

= 5.0 V

T 40

= 3.0 V

T 60

Hold time from WR

to WAIT

HWWT

= 5.0 V

nT + 5

= 3.0 V

nT + 10

Delay time from WR

to WAIT

DWWTH

= 5.0 V

(1 + n) T 40

= 3.0 V

(1 + n) T 60

Remark

T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise 0

n: Number of waits (n

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Serial Operation (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V)

(a) 3-wire serial I/O mode (SCK: internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY1

2.7 V

5.5 V

800

3,200

SCK high-/low-level width

KH1

2.7 V

5.5 V

350

KL1

1,500

SI setup time (to SCK

)

SIK1

2.7 V

5.5 V

SI hold time (from SCK

)

KSI1

SO output delay time

KSO1

(from SCK

)

(b) 3-wire serial I/O mode (SCK: external clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY2

2.7 V

5.5 V

800

3,200

SCK high-/low-level width

KH2

2.7 V

5.5 V

400

KL2

1,600

SI setup time (to SCK

)

SIK2

2.7 V

5.5 V

SI hold time (from SCK

)

KSI2

SO output delay time

KSO2

(from SCK

)

(c) UART mode

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

ASCK cycle time

KCY3

4.5 V

5.5 V

417

2.7 V

< 4.5 V

833

1,667

ASCK high-/low-level width

KH3

4.5 V

5.5 V

208

KL3

2.7 V

< 4.5 V

416

833

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

(d) I

C bus mode (

PD784218Y only)

Parameter

Symbol

Standard Mode

High-Speed Mode

Unit

MIN.

MAX.

MIN.

MAX.

SCL0 clock frequency

CLK

100

400

kHz

Bus free time (between stop

BUF

4.7

1.3

and start conditions)

Hold time

Note1

HD : STA

4.0

0.6

Low-level width of SCL0 clock

LOW

4.7

1.3

High-level width of SCL0 clock

HIGH

4.0

0.6

Setup time of start/restart

SU : STA

4.7

0.6

conditions

Data

When using CBUS-

HD : DAT

5.0

hold

compatible master

time

When using I

C bus

Note 2

0.9

Note 3

Data setup time

SU : DAT

250

100

Note 4

Rise time of SDA0 and SCL0

1,000

20 + 0.1Cb

Note 5

300

signals

Fall time of SDA0 and SCL0

300

20 + 0.1Cb

Note 5

300

signals

Setup time of stop condition

SU : STO

4.0

0.6

Pulse width of spike restricted

by input filter

Load capacitance of each bus

400

line

Notes 1. For the start condition, the first clock pulse is generated after the hold time.

2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal

SDA0 signal (on V

IHmin.

) with at least 300 ns of hold time.

3. If the device does not extend the SCL0 signal low hold time (t

LOW

), only maximum data hold time

HD : DAT

needs to be satisfied.

4. The high-speed mode I

C bus can be used in a standard mode I

C bus system. In this case, the

conditions described below must be satisfied.

If the device does not extend the SCL0 signal low state hold time

SU : DAT

250 ns

If the device extends the SCL0 signal low state hold time

Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released

Rmax.

+ t

SU : DAT

= 1,250 ns by standard mode I

C bus specification)

5. Cb: total capacitance per one bus line (unit: pF)

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

Other Operations (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

NMI high-/low-level width

WNIL

WNIH

INTP input high-/low-level width

WITL

INTP0 to INTP6

WITH

RESET high-/low-level width

WRSL

WRSH

Clock Output Operation (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

PCL cycle time

CYCL

= 4.5 to 5.5 V, nT

31,250

PCL high-/low-level width

CLL

= 4.5 to 5.5 V, 0.5T 10

15,615

CLH

PCL rise/fall time

CLR

4.5 V

5.5 V

CLF

2.7 V

< 4.5 V

2.2 V

< 2.7 V

Remark T: t

CYK

= 1/f

: main system clock frequency)

n: Divided frequency ratio set by software in the CPU

· When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128

· When using the subsystem clock: n = 1

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

A/D Converter Characteristics (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

Note

2.7 V

REF0

1.2

2.2 V

REF0

< 2.7 V (only when AV

REF0

= AV

)

1.6

Conversion time

CONV

144

Sampling time

SAMP

24/f

Analog input voltage

IAN

REF0

Reference voltage

REF0

2.2

Resistance between AV

REF0

and AV

AVREF0

29.4

Note Excludes quantization error (

1/2 LSB).

Remark f

: Main system clock frequency

D/A Converter Characteristics (T

= 40 to +85

C, V

= AV

= 2.2 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Total error

R = 2 M

, 2.2 V < AV

REF1

5.5 V

1.2

R = 4 M

, 2.2 V < AV

REF1

5.5 V

0.8

R = 10 M

, 2.2 V < AV

REF1

5.5 V

0.6

Settling time

Load conditions:

4.5 V

REF1

5.5 V

C = 30 pF

2.7 V

REF1

< 4.5 V

2.2 V

REF1

< 2.7 V

Output resistance

DACS0, 1 = 55 H

5.3

Reference voltage

REF1

2.2

REF1

current

REF1

For only 1 channel

2.5

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

17. RECOMMENDED SOLDERING CONDITIONS

The

PD784218 should be soldered and mounted under the following recommended conditions. For the details

of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology

Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales representative.

Caution

Soldering conditions for the

PD784218YGC-

×××

-8EU and

PD784218YGF-

×××

-3BA are undetermined

because these products are under development.

Table 17-1. Soldering Conditions for Surface Mount Type

(1)

PD784218GC-

×××

-8EU: 100-pin plastic LQFP (Fine pitch) (14

14 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or

IR35-107-2

higher), Count: Two times or less, Exposure limit: 7 days

Note

(after that,

prebake at 125

C for 10 hours)

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or

VP-15-107-2

higher), Count: Two times or less, Exposure limit: 7 days

Note

(after that,

prebake at 125

C for 10 hours)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Caution

Do not use different soldering methods together (except for partial heating).

(2)

PD784218GF-

×××

-3BA: 100-pin plastic QFP (14

20 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or

IR35-00-2

higher), Count: Two times or less

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or

VP15-00-2

higher), Count: Two times or less

Wave soldering

Solder bath temperature: 260

C max., Time: 10 seconds max., Count: Once,

WS60-00-1

Preheating temperature: 120

C max. (package surface temperature)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Caution

Do not use different soldering methods together (except for partial heating).

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD784218. Also refer to (5)

Cautions on Using Development Tools.

(1) Language Processing Software

RA78K4

Assembler package common to 78K/IV Series

CC78K4

C compiler package common to 78K/IV Series

DF784218

Device file common to

PD784218, 784218Y Subseries

CC78K4-L

C compiler library source file common to 78K/IV Series

(2) Flash Memory Writing Tools

Flashpro II

Dedicated flash programmer for microcontroller incorporating flash memory

(Part No.: FL-PR2),

Flashpro III

(Part No.: FL-PR3, PG-FP3)

FA-100GF

Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory.

FA-100GC

Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory.

(3) Debugging Tools

When IE-78K4-NS in-circuit emulator is used

IE-78K4-NS

In-circuit emulator common to 78K/IV Series

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter used when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-CD-IF-A

PC card and cable when notebook PC is used as host machine (PCMCIA socket supported)

IE-70000-PC-IF-C

Interface adapter when using IBM PC/AT

or compatible as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter when using PC that incorporates PCI bus as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784218, 784218Y Subseries

NP-100GF

Emulation probe for 100-pin plastic QFP (GF-3BA type)

NP-100GC

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the NP-100GC and a target system board on which a 100-

pin plastic LQFP (GC-8EU type) can be mounted

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4

System simulator common to 78K/IV Series

DF784218

Device file common to

PD784218, 784218Y Subseries

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

When IE-784000-R in-circuit emulator is used

IE-784000-R

In-circuit emulator common to 78K/IV Series

IE-70000-98-IF-C

Interface adapter used when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-PC-IF-C

Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter when using PC that incorporates PCI bus as host machine

IE-78000-R-SV3

Interface adapter and cable used when EWS is used as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784218, 784218Y Subseries

IE-784218-R-EM1

IE-784000-R-EM

Emulation board common to 78K/IV Series

IE-78K4-R-EX3

Emulation probe conversion board necessary when using IE-784225-NS-EM1 on IE-

784000-R. Not necessary when IE-784216-R-EM1 is used.

EP-78064GF-R

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EP-78064GC-R

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the NP-100GC and a target system board on which a 100-

pin plastic LQFP (GC-8EU type) can be mounted

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator common to 78K/IV Series

DF784218

Device file common to

PD784218, 784218Y Subseries

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series

MX78K4

OS for 78K/IV Series

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

(5) Cautions on Using Development Tools

The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.

The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.

The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito

Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).

The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.

For further information, contact Daimaru Kogyo, Ltd.

Tokyo Electronic Division (TEL: +81-3-3820-7112)

Osaka Electronic Division (TEL: +81-6-6244-6672)

For third-party development tools, see the 78K/IV Series Selection Guide (U13355E).

The host machine and OS suitable for each software are as follows:

Host Machine

EWS

[OS]

PC-9800 series [Windows]

HP9000 series 700

[HP-UX

]

IBM PC/AT and compatibles

SPARCstation

[SunOS

, Solaris

]

Software

[Japanese/English Windows]

NEWS

(RISC) [NEWS-OS

]

RA78K4

Note

CC78K4

Note

ID78K4-NS

ID78K4

SM78K4

RX78K/IV

Note

MX78K4

Note

Note DOS-based software

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

APPENDIX B RELATED DOCUMENTS

Documents Related to Devices

Document Name

Document No.

Japanese

English

PD784218, 784218Y Data Sheet

U12304J

This document

PD78F4218, 78F4218Y Preliminary Product Information

U12440J

U12440E

PD784218, 784218Y Subseries User's Manual Hardware

U12970J

U12970E

78K/IV Series User's Manual Instructions

U10905J

U10905E

78K/IV Series Instruction Table

U10594J

78K/IV Series Instruction Set

U10595J

78K/IV Series Application Note Software Fundamentals

U10095J

U10095E

Documents Related to Development Tools (User's Manuals)

Document Name

Document No.

Japanese

English

RA78K4 Assembler Package

Language

U11162J

U11162E

Operation

U11334J

U11334E

RA78K Structured Assembler Preprocessor

U11743J

U11743E

CC78K4 C Compiler

Language

U11571J

U11571E

Operation

U11572J

U11572E

IE-78K4-NS

U13356J

U13356E

IE-784000-R

U12903J

U12903E

IE-784218-R-EM1

U12155J

U12155E

IE-784225-NS-EM1

U13742J

U13742E

EP-78064

EEU-934

EEU-1469

SM78K4 System Simulator Windows Based

Reference

U10093J

U10093E

SM78K Series System Simulator

External Part User Open

U10092J

U10092E

Interface Specifications

ID78K4-NS Integrated Debugger PC Based

Reference

U12796J

U12796E

ID78K4 Integrated Debugger Windows Based

Reference

U10440J

U10440E

ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based

Reference

U11960J

U11960E

Caution

The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

IEBus is a trademark of NEC Corporation.

Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other

countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use these

components in an I

C system, provided that the system conforms to the I

C Standard Specification as defined

by Philips.

PD784218, 784218Y

Data Sheet U12304EJ2V0DS00

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J99.1

PD784218, 784218Y

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98. 8

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