MOS INTEGRATED CIRCUIT

8-BIT SINGLE-CHIP MICROCONTROLLER

PD780053Y,780054Y,780055Y,780056Y,780058Y

DESCRIPTION

The

PD780053Y,780054Y,780055Y,780056Y and 780058Y are versions of the

PD780053, 780054, 780055,

780056, 780058 to which an I

C bus control function has been added. These microcontrollers suppress the EMI

(Electro Magnetic Interference) noise internally generated to the lower level than the existing

PD78054 subseries.

In addition, they have many peripheral hardware units such as an 8-bit resolution A/D converter, 8-bit resolution D/

A converter, timers, serial interface, real-time output ports, and interrupt functions.

A flash memory model that can operate on the same voltage as the mask ROM models,

PD78F0058Y, and various

development tools are now under development.

The funcitons are explaned in detail in the following User's Manuals. Be sure to read these manuals when

designing your system.

PD780058, 780058Y Subseries User's Manual : U12013E

78K/0 Series User's Manual - Instruction

: U12326E

FEATURES

Internal high-capacity ROM & RAM

External memory expansion space: 64K bytes

Minimum instruction execution time changeable from high speed (0.4

s) to ultra low-speed (122

I/O ports: 68 pins (N-ch open-drain : 4 pins)

8-bit resolution A/D converter : 8 channels (V

= 2.7 to 5.5 V)

8-bit resolution D/A converter : 2 channels (V

= 2.7 to 5.5 V)

Serial interface

: 3 channels (I

C bus mode supported: 1ch)

Timer

: 5 channels

Operating voltage range

: V

= 1.8 to 5.5 V

APPLICATION FIELDS

Car audio systems, cellular phones, pagers, printers, AV systems, cameras, PPCs, and vending machines

Item

Part Number

Internal high-speed RAM

Internal buffer RAM

Internal expanded RAM

Data Memory

24K bytes

32K bytes

40K bytes

48K bytes

60K bytes

PD780053Y

PD780054Y

PD780055Y

PD780056Y

PD780058Y

None

1024 bytes

Program Memory

(ROM)

32 bytes

1997

PRELIMINARY DATA SHEET

The information in this document is subject to change without notice.

The mark shows major revised points.

Document No. U12328EJ1V1DS00 (1st edition)
Date Published January 1999 N CP(K)
Printed in Japan

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

ORDERING INFORMATION

Part Number

Package

PD780053YGC-

×××

-8BT

80-pin plastic QFP (14

14 mm)

PD780053YGK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

PD780054YGC-

×××

-8BT

80-pin plastic QFP (14

14 mm)

PD780054YGK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

PD780055YGC-

×××

-8BT

80-pin plastic QFP (14

14 mm)

PD780055YGK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

PD780056YGC-

×××

-8BT

80-pin plastic QFP (14

14 mm)

PD780056YGK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

PD780058YGC-

×××

-8BT

80-pin plastic QFP (14

14 mm)

PD780058YGK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

Remark

×××

indicates ROM code suffix.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

78K/0 SERIES PRODUCT DEVELOPMENT

The following shows the 78K/0 Series products development. Subseries name are shown inside frames.

Note Under planning

Control

FIP

drive

100-pin

LCD drive

IEBus

supported

42/44-pin

64-pin

80-pin

100-pin

80-pin

100-pin

80-pin

78K/0

Series

Basic subseries for driving FIP, Display output total: 34

Basic subseries for driving LCDs, On-chip UART

Y subseries products are compatible with I

C bus.

Products under
development

Products in
mass production

80-pin

100-pin

PD78054

PD78014

PD780001

PD78002

PD78054Y

PD78014Y

PD78002Y

PD78083

PD780208

PD78044H

PD78044F

PD78064B

PD78064

PD78098

PD78064Y

An IEBus controller was added to the PD78054

EMI-noise reduced version of the PD78078

I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53

EMI-noise reduced version of the PD78064

PD78058F

PD78058FY

PD780058Y

Note

PD780058

PD78070A

PD78070AY

PD78078

PD78078Y

80-pin

PD780308

PD780308Y

The SIO of the PD78064 was enhanced and ROM, RAM capacity increased

100-pin

Meter control

80-pin

On-chip controller/driver for automotive meter drive

PD780973

Inverter control

64-pin

On-chip inverter control circuit and UART. EMI-noise was reduced.

PD780988

PD78075B

100-pin

PD780018Y

Note

100-pin

PD780024Y

PD780024

64-pin

PD780034Y

PD780034

64-pin

PD78014H

64-pin

PD78018F

PD78018FY

A timer was added to the PD78054 and external interface was enhanced

ROM-less version of the PD78078

EMI-noise reduced version of the PD78054

UART and D/A converter were added to the PD78014 and I/O was enchanced

A/D converter of the PD780024 was enchanced

Serial I/O of the PD78018F was added

Serial I/O of the PD78054 was enhanced and EMI-noise was reduced

EMI-noise reduced version of PD78018F

Serial I/O of the PD78078Y was enhanched and the function is limited

Low-voltage (1.8 V) operation version of the PD78014, with larger
selection of ROM and RAM capacities

An A/D converter and 16-bit timer were added to the PD78002

An A/D converter was added to the PD78002

Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)

PD780228

100-pin

I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48

N-ch open drain was added to the PD78044F, Display output total: 34

PD78098B

80-pin

EMI-noise reduced version of the PD78098

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

The following lists the main functional differences between subseries products.

Function

ROM

Serial Interface

I/O

Subseries Name

Capacity

MIN. Value

Control

PD78078Y

48 K-60 K

3-wire/2-wire/I

: 1 ch

1.8 V

PD78070AY

3-wire with automatic transmit/receive function

: 1 ch

2.7 V

3-wire/UART

: 1 ch

PD780018AY

48 K-60 K

3-wire with automatic transmit/receive function

: 1 ch

Time division 3-wire

: 1 ch

C bus (multi-master compatible)

: 1 ch

PD780058Y

24 K-60 K

3-wire/2-wire/I

: 1 ch

1.8 V

3-wire with automatic transmit/receive function

: 1 ch

3-wire/time division UART

: 1 ch

PD78058FY

48 K-60 K

3-wire/2-wire/I

: 1 ch

2.7 V

PD78054Y

16 K-60 K

3-wire with automatic transmit/receive function

: 1 ch

2.0 V

3-wire/UART

: 1 ch

PD780034Y

8 K-32 K

UART

: 1 ch

1.8 V

PD780024Y

3-wire

: 1 ch

C bus (multi-master compatible)

: 1 ch

PD78018FY

8 K-60 K

3-wire/2-wire/I

: 1 ch

3-wire with automatic transmit/receive function

: 1 ch

PD78014Y

8 K-32 K

3-wire/2-wire/SBI/I

: 1 ch

2.7 V

3-wire with automatic transmit/receive function

: 1 ch

PD78002Y

8 K-16 K

3-wire/2-wire/SBI/I

: 1 ch

LCD drive

PD780308Y

48 K-60 K

3-wire/2-wire/I

: 1 ch

2.0 V

3-wire/time division UART

: 1 ch

3-wire

: 1 ch

PD78064Y

16 K-32 K

3-wire/2-wire/I

: 1 ch

3-wire/UART

: 1 ch

Remark

The functions other than serial interface are common to the subseries without suffix Y.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

OVERVIEW OF FUNCTION

When main system

clock selected

When subsystem

clock selected

Item

Product Name

24K bytes

32K bytes

40K bytes

48K bytes

60K bytes

1024 bytes

32 bytes

None

64 K bytes

8 bits

32 registers (8 bits

8 registers

4 banks)

On-chip minimum instruction execution time cycle modification function

0.4

s/0.8

s/1.6

s/3.2

s/6.4

s/12.8

s (at 5.0 MHz operation)

122

s (at 32.768 kHz operation)

· 16-bit operation

· Multiplication/division (8 bits

8 bits,16 bits

8 bits)

· Bit manipulation (set, reset, test, boolean operation)

· BCD correction, etc.

Total

: 68

· CMOS input

· CMOS I/O

: 62

· N-ch open-drain I/O

· 8-bit resolution

8 channels (V

= 2.7 to 5.5 V)

· 8-bit resolution

2 channels (V

= 2.7 to 5.5 V)

· 3-wire serial I/O/2-wire serial I/O/I

C bus mode selectable: 1 channel

· 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function):

1 channel

· 3-wire/serial I/O/UART mode (on-chip time division transfer function) selectable:

1 channel

· 16-bit timer/event counter

: 1 channel

· 8-bit timer/event counter

: 2 channels

· Watch timer

: 1 channel

· Watchdog timer

: 1 channel

3 (14-bit PWM output

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz

(at main system clock: 5.0 MHz operation)

32.768 kHz (at subsystem clock: 32.768 kHz operation)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 5.0 MHz operation)

Internal interrupt : 13, external interrupt : 6

Internal interrupt : 1

Internal : 1, external : 1

= 1.8 to 5.5 V

= 40 to +85

· 80-pin plastic QFP (14

14 mm)

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

Serial interface

PD780053Y

Memory space

General registers

Minimum instruction execution

time

Instruction set

I/O ports

A/D converter

D/A converter

Timer

Timer output

Clock output

Buzzer output

Test input

Supply voltage

Operating ambient temperature

Package

Internal
memory

1024 bytes

PD780054Y

PD780055Y

PD780056Y

PD780058Y

ROM

High-speed RAM

Buffer RAM

Expanded RAM

Maskable

Non-maskable

Software

Vectored

interrupt

sources

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

CONTENTS

PIN CONFIGURATION (TOP VIEW) .............................................................................................. 7

BLOCK DIAGRAM ......................................................................................................................... 9

PIN FUNCTIONS ............................................................................................................................ 10

3.1

PORT PINS .............................................................................................................................................. 10

3.2

OTHER PINS ............................................................................................................................................ 12

3.3

PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ................................. 14

MEMORY SPACE ............................................................................................................................ 18

PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 19

5.1

PORTS ...................................................................................................................................................... 19

5.2

CLOCK GENERATOR ............................................................................................................................. 20

5.3

TIMER/EVENT COUNTER ...................................................................................................................... 20

5.4

CLOCK OUTPUT CONTROL CIRCUIT ................................................................................................. 23

5.5

BUZZER OUTPUT CONTROL CIRCUIT ................................................................................................ 23

5.6

A/D CONVERTER .................................................................................................................................... 24

5.7

D/A CONVERTER .................................................................................................................................... 25

5.8

SERIAL INTERFACES ............................................................................................................................ 25

5.9

REAL-TIME OUTPUT PORT FUNCTIONS ............................................................................................ 27

INTERRUPT FUNCTIONS .............................................................................................................. 28

6.1

INTERRUPT FUNCTIONS ....................................................................................................................... 28

6.2

TEST FUNCTIONS .................................................................................................................................. 32

EXTERNAL DEVICE EXPANSION FUNCTIONS .......................................................................... 33

STANDBY FUNCTION .................................................................................................................... 33

RESET FUNCTION .......................................................................................................................... 33

10. INSTRUCTION SET ......................................................................................................................... 34

11. ELECTRICAL SPECIFICATIONS ................................................................................................... 36

12. PACKAGE DRAWINGS .................................................................................................................. 63

APPENDIX A. DEVELOPMENT TOOLS ........................................................................................... 65

APPENDIX B. RELATED DOCUMENTS ........................................................................................... 68

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

1. PIN CONFIGURATION (TOP VIEW)

· 80-pin plastic QFP (14

14 mm)

PD780053YGC-

×××

-8BT, 780054YGC-

×××

-8BT, 780055YGC-

×××

-8BT, 780056YGC-

×××

-8BT, 780058YGC-

×××

-8BT

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD780053YGK-

×××

-BE9, 780054YGK-

×××

-BE9, 780055YGK-

×××

-BE9, 780056YGK-

×××

-BE9, 780058YGK-

×××

-BE9

Cautions 1.

Directly connect the IC (Internally Connected) pins to V

SS0

or V

SS1

Connect the AV

pin to V

SS0

Remarks 1.

×××

indicates ROM code suffix.

2. If the microcontroller is used in an application where the noise generated from the microcontroller

must be suppressed, it is recommended that power be supplied to V

DD0

and V

DD1

from separate

sources, and that V

SS0

and V

SS1

be connected to separate group lines, to improve noise immunity.

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

RESET

P127/RTP7

P126/RTP6

P125/RTP5

P124/RTP4

P123/RTP3

P122/RTP2

P121/RTP1

P120/RTP0

P37

P36/BUZ

P35/PCL

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P67/ASTB

P66/WAIT

P65/WR

P15/ANI5

P16/ANI6

P17/ANI7

P130/ANO0

P131/ANO1

REF1

P70/SI2/RxD0

P71/SO2/TxD0

P72/SCK2/ASCK

P20/SI1

P21/SO1

P22/SCK1

P23/STB/TxD1

P24/BUSY/RxD1

P25/SI0/SB0/SDA0

P26/SO0/SB1/SDA1

P27/SCK0/SCL

P40/AD0

P41/AD1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

REF0

DD0

XT1/P07

XT2

DD1

SS0

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

P01/INTP1/TI01

P00/INTP0/TI00

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

SS1

P56/A14

P57/A15

P60

P61

P62

P63

P64/RD

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

A8-A15

: Address Bus

AD0-AD7

: Address/Data Bus

ANI0-ANI7

: Analog Input

ANO0, ANO1

: Analog Output

ASCK

: Asychronous Serial Clock

ASTB

: Address Strobe

REF0, 1

: Analog Reference Voltage

: Analog Ground

BUSY

: Busy

BUZ

: Buzzer Clock

: Internally Connected

INTP0-INTP5

: Interrupt from Peripherals

P00-P05, P07

: Port0

P10-P17

: Port1

P20-P27

: Port2

P30-P37

: Port3

P40-P47

: Port4

P50-P57

: Port5

P60-P67

: Port6

P70-P72

: Port7

P120-P127

: Port12

P130, P131

: Port13

PCL

: Programmable Clock

: Read Strobe

RESET

: Reset

RTP0-RTP7

: Real-Time Output Port

RxD0, RxD1

: Receive Data

SB0, SB1

: Serial Bus

SCK0-SCK2

: Serial Clock

SCL

: Serial Clock

SDA0, SDA1

: Serial Data

SI0-SI2

: Serial Input

SO0-SO2

: Serial Output

STB

: Strobe

TI00, TI01

: Timer Input

TI1, TI2

: Timer Input

TO0-TO2

: Timer Output

TxD0, TxD1

: Transmit Data

DD0

, V

DD1

: Power Supply

SS0

, V

SS1

: Ground

WAIT

: Wait

: Write Strobe

X1, X2

: Crystal (Main System Clock)

XT1, XT2

: Crystal (Subsystem Clock)

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

2. BLOCK DIAGRAM

Remark The internal ROM and RAM capacities differ depending on the product.

16-bit TIMER/
EVENT COUNTER

WATCHDOG TIMER

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

8-bit TIMER/
EVENT COUNTER 1

TO1/P31

TI1/P33

8-bit TIMER/
EVENT COUNTER 2

TO2/P32

TI2/P34

WATCH TIMER

SERIAL
INTERFACE 0

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SERIAL
INTERFACE 1

SI1/P20

SO1/P21

SCK1/P22

STB/TxD1/P23

SERIAL
INTERFACE 2

A/D CONVERTER

REF0

ANI0/P10-
ANI7/P17

D/A CONVERTER

REF1

ANO0/P130,
ANO1/P131

INTP0/P00-
INTP5/P05

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

BUZ/P36

PCL/P35

DD0

DD1

SS0

SS1

RAM

78K/0

CPU CORE

ROM

PORT0

P01-P05

P00

P07

PORT1

P10-P17

PORT2

P20-P27

PORT3

P30-P37

PORT4

P40-P47

PORT5

P50-P57

PORT6

P60-P67

PORT7

P70-P72

PORT12

P120-P127

PORT13

P130,P131

EXTERNAL

ACCESS

AD0/P40-
AD7/P47
A8/P50-
A15/P57
RD/P64

WR/P65

WAIT/P66

ASTB/P67

REAL-TIME

OUTPUT PORT

RTP0/P120-
RTP7/P127

SYSTEM

CONTROL

RESET

XT1/P07

XT2

BUSY/RxD1/P24

STB/TxD1/P23

SI2/RxD0/P70

SO2/TxD0/P71

SCK2/ASCK/P72

BUSY/RxD1/P24

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Dual-

Function Pin

Pin Name

I/O

Input only

Input

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up

resistor can be used by software.

Input/

output

Input only

Port 1

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by

software

Note 2

Input/

output

Input/

output

Port 2

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by

software.

Port 3

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by

software.

Input/

output

Input/

output

Port 4

8-bit input/output port.

Input/output can be specified in 8-bit unit.

When used as an input port, on-chip pull-up resistor can be used by

software. Test input flag (KRIF) is set to 1 by falling edge detection.

3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

INTP0/TI00

INTP1/TI01

INTP2

INTP3

INTP4

INTP5

XT1

ANI0-ANI7

SI1

SO1

SCK1

STB/TxD1

BUSY/RxD1

SI0/SB0/SDA0

SO0/SB1/SDA1

SCK0/SCL

TO0

TO1

TO2

TI1

TI2

PCL

BUZ

AD0-AD7

P00

P01

P02

P03

P04

P05

P07

Note 1

P10-P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

P40-P47

Input

Function

Port 0

7-bit input/output port

Input

After

Reset

Input

Notes 1. When using the P07/XT1 pins as an input port, set 1 in the bit 6 (FRC) of the processor clock control

2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to input

mode. Use of the on-chip pull-up resistor is cancelled automatically.

Input

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

3.1 PORT PINS (2/2)

Dual-

Function Pin

Function

Pin Name

I/O

Input/

output

Input/

output

P50-P57

When used as an input

port, on-chip pull-up

resistor can be used by

software.

P60

P61

P62

P63

P64

P65

P66

P67

P70

P71

P72

P120-P127

P130, P131

Input/

output

Input/

output

Input/

output

N-ch open-drain input/

output port. On-chip pull-

up resistor can be used

by mask option. LED can

be driven directly.

After

Reset

Port 5

8-bit input/output port.

LED can be driven directly.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 6

8-bit input/outport port. Input/output can be

specified bit-wise.

Port 13

2-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 12

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 7

3-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

A8-A15

WAIT

ASTB

SI2/RxD0

SO2/TxD0

SCK2/ASCK

RTP0-RTP7

ANO0, ANO1

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

SI0

SI1

SI2

SO0

SO1

SO2

SB0

SB1

SDA0

SDA1

SCK0

SCK1

SCK2

SCL

STB

BUSY

RxD0

RxD1

TxD0

TxD1

ASCK

TI00

TI01

TI1

TI2

TO0

TO1

TO2

PCL

BUZ

RTP0-RTP7

AD0-AD7

Dual-

Function Pin

Function

Pin Name

I/O

Input

External interrupt request input for which the effective edge (rising edge,

falling edge, or both rising edge and falling edge) can be specified.

Input

Serial interface serial data input.

Output

Serial interface serial data output.

Serial interface serial data input/output.

Input/

output

Input/

output

Serial interface serial clock input/ output

Serial interface automatic transmit/receive strobe output.

Serial interface automatic transmit/receive busy input.

Output

Input

Output

Input

Output

Asynchronous serial interface serial data input.

Asynchronous serial interface serial data output.

3.2 OTHER PINS (1/2)

P00/TI00

P01/TI01

P02

P03

P04

P05

P25/SB0

P20

P70/RxD

P26/SB1

P21

P71/TxD

P25/SI0/SDA0

P26/SO0/SDA1

P25/SI0/SB0

P26/SO0/SB1

P27/SCL

P22

P72/ASCK

P27/SCK0

P23/TxD1

P24/RxD1

P70/SI2

P24/BUSY

P71/SO2

P23/STB

P72/SCK2

P00/INTP0

P01/INTP1

P33

P34

P30

P31

P32

P35

P36

P120-P127

P40-P47

Output

Clock output (for main system clock, subsystem clock trimming).

Buzzer output.

Real-time output port by which data is output in synchronization with a trigger.

Low-order address/data bus at external memory expansion.

Input/

output

After

Reset

Input

External count clock input to the 16-bit timer (TM0)

Asynchronous serial interface serial clock input.

Capture trigger signal input to the capture register (CR00)

External count clock input to the 8-bit timer (TM1)

External count clock input to the 8-bit timer (TM2)

16-bit timer (TM0) output (dual-function as 14-bit PWM output)

8-bit timer (TM1) output

8-bit timer (TM2) output

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

P50-P57

P64

P65

P66

P67

P10-P17

P130, P131

P07

Input

High-order address bus at external memory expansion.

External memory read operation strobe signal output.

External memory write operation strobe signal output.

Wait insertion at external memory access.

Strobe output which latches the address information output at port 4 to access

external memory.

A/D converter analog input.

D/A converter analog output.

A/D converter reference voltage input (dual-function as analog power supply).

D/A converter reference voltage input.

A/D converter, D/A converter ground potential. Use at the same potential as

SS0

System reset input.

Main system clock oscillation crystal connection.

Subsystem clock oscillation crystal connection.

Port block positive power supply.

Port block ground potential.

Positive power supply (except for port and analog blocks).

Ground potiential (except for port and analog blocks).

Internally connected. Connect to V

SS0

or V

SS1

directly.

Output

Input

Output

Input

Output

Input

A8-A15

WAIT

ASTB

ANI0-ANI7

ANO0, ANO1

REF0

REF1

RESET

XT1

XT2

DD0

SS0

DD1

SS1

3.2 OTHER PINS (2/2)

Dual-

Function Pin

Function

Pin Name

I/O

After

Reset

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output circuit configuration of each type, see Figure 3-1.

Table 3-1. Input/Output Circuit Type of Each Pin (1/2)

Input/Output

Circuit Type

8-C

11-D

8-C

5-H

8-C

5-H

8-C

10-B

5-H

8-C

5-H

5-N

5-H

13-J

5-H

Input

Input/output

Input

Input/output

Connect to V

SS0

Independently connect to V

SS0

through resistor.

Connect to V

DD0

P00/INTP0/TI00

P01/INTP1/TI01

P02/INTP2

P03/INTP3

P04/INTP4

P05/INTP5

P07/XT1

P10/ANI0-P17/ANI7

P20/SI1

P21/SO1

P22/SCK1

P23/STB/TxD1

P24/BUSY/RxD1

P25/SI0/SB0/SDA0

P26/SO0/SB1/SDA1

P27/SCK0/SCL

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

P40/AD0-P47/AD7

P50/A8-P57/A15

P60-P63

P64/RD

P65/WR

P66/WAIT

P67/ASTB

Pin Name

I/O

Recommended Connection when Not Used

Independently connect to V

DD0

or V

SS0

through resistor.

Independently connect to V

DD0

through resistor.

Independently connect to V

DD0

or V

SS0

through resistor.

Independently connect to V

DD0

through resistor.

Independently connect to V

DD0

or V

SS0

through resistor.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

4. MEMORY SPACE

Figure 4-1 shows the

PD780053Y/780054Y/780055Y/780056Y/780058Y memory map.

Figure 4-1. Memory Map

Notes 1.

PD780058Y only

2. When the external device expansion function is used with the

PD780058Y, set the internal ROM

capacity to 56K bytes or less using the memory size switching register (IMS).

3. The internal ROM capacity depends on the products (see the next table).

Special Function Registers

(SFR) 256

8 bits

General Registers

8 bits

Internal High-Speed

RAM

Note 3

Use Prohibited

Internal Buffer RAM

8 bits

Use Prohibited

External Memory

Internal ROM

Note 3

Data Memory
Space

Program Memory
Space

FFFFH

FF00H
FEFFH

FEE0H

FEDFH

FB00H

FAFFH

FAE0H

FADFH

FAC0H

FABFH

FA80H

FA7FH

nnnnH + 1

nnnnH

0000H

Use Prohibited

Internal Expanded RAM

1024

8 bits

Use Prohibited

Note 2

FA7FH

F800H
F7FFH

F400H
F3FFH

F000H

Program Area

CALLF Entry Area

Program Area

CALLT Table Area

Vector Table Area

nnnnH

1000H
0FFFH

0800H
07FFH

0080H
007FH

0040H
003FH

0000H

Note 1

Internal ROM Last Address

nnnnH

Relevant Product Name

PD780053Y

PD780054Y

PD780055Y

PD780056Y

PD780058Y

5FFFH

7FFFH

9FFFH

BFFFH

EFFFH

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

5. PERIPHERAL HARDWARE FUNCTION FEATURES

5.1 PORTS

The following three types of I/O ports are available.

· CMOS input (P00, P07)

· CMOS input/output (P01-P05, port 1-port 5, P64-P67, port 7, port 12, port 13)

· N-channel open-drain input/output (P60-P63)

Total

Table 5-1. Port Functions

Pin Name

Function

Dedicated input port pins

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable in 8-bit units.

When used as input port pins, on-chip pull-up resistor can be used by software.

Test flag (KRIF) is set to 1 by falling edge detection.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

LED direct drive capability.

N-channel open-drain input/output port pins. Input/output specifiable bit-wise.

On-chip pull-up resistor can be used by mask option.

LED direct drive capability.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Name

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 12

Port 13

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P63

P64-P67

P70-P72

P120-P127

P130, P131

P00, P07

P01-P05

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

5.2 CLOCK GENERATOR

Two types of generators, a main system clock generator and a subsystem clock generator, are avaibable.

The minimum instruction execution time can also be changed.

· 0.4

s/0.8

s/1.6

s/3.2

s/6.4

s/12.8

s (main system clock: at 5.0 MHz operation)

· 122

(subsystem clock: at 32.768 kHz operation)

Figure 5-1. Clock Generator Block Diagram

5.3 TIMER/EVENT COUNTER

The following five channels of the timer/event counter are available.

· 16-bit timer/event counter : 1 channel

· 8-bit timer/event counter

: 2 channels

· Watch timer

: 1 channel

· Watchdog timer

: 1 channel

Table 5-2. Operations of Timer/Event Counter

16-Bit Timer/

Event Counter

Watch Timer

Watchdog Timer

External event counter

Operation

mode

Timer output

PWM output

Square wave output

Pulse width measurement

Interrupt request

Function

Interval timer

Ono-shot pulse output

8-Bit Timer/

Event Counter

1 channel

1 output

1 input

1 output

2 channels

2 outputs

1 channel

XT1/P07

XT2

Subsystem
Clock
Oscillator

Watch Timer, Clock
Output Function

Prescaler

Main System
Clock
Oscillator

Clock to Peripheral
Hardware

CPU Clock
(f

CPU

)

Standby
Control
Circuit

Wait Control
Circuit

To INTP0
Sampling Clock

Prescaler

Selector

STOP

Scaler

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

Figure 5-2. 16-Bit Timer/Event Counter Block Diagram

Figure 5-3. 8-Bit Timer/Event Counter Block Diagram

Internal Bus

8-Bit Compare
Register (CR10)

8-Bit Timer
Register 1 (TM1)

Clear

Match

Selector

Output
Control
Circuit

INTTM1

TO2/P32

INTTM2

TO1/P31

Clear

Match

Selector

8-Bit Compare
Register (CR20)

8-Bit Timer
Register 2 (TM2)

Internal Bus

/2-f

TI1/P33

/2-f

TI2/P34

Internal Bus

Selector

16-Bit Timer Register

(TM0L)

Clear

Output Control

Circuit

PWM Pulse
Output
Control
Circuit

16-Bit Capture/
Compare Register

Internal Bus

INTP1

INTTM00

TO0/P30

INTTM01

INTP0

TI01/P01/INTP1

Watch Timer

Output

TI00/P00/INTP0

16-Bit Capture/

Compare Register

(CR01)

(CR00)

Edge
Detector

Match

Selector

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

5.4 CLOCK OUTPUT CONTROL CIRCUIT

The clock with the following frequency can be output as a clock output.

· 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: at

5.0 MHz operation)

· 32.768 kHz

(subsystem clock: at 32.768 kHz operation)

Figure 5-6. Clock Output Control Circuit Configuration

5.5 BUZZER OUTPUT CONTROL CIRCUIT

The clock with the following frequency can be output as a buzzer output.

· 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock: at 5.0 MHz operation)

Figure 5-7. Buzzer Output Control Circuit Block Diagram

Selector

Synchronization
Circuit

Output Control
Circuit

PCL/P35

Selector

Output Control
Circuit

BUZ/P36

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

= 0, 1

= 4, 5

= 1, 2

5.8 SERIAL INTERFACES

Three channels of the clocked serial interface are incorporated.

· Serifal interface channel 0

· Serifal interface channel 1

· Serifal interface channel 2

Table 5-3. Types and Functions of Serial Interface

5.7 D/A CONVERTER

A D/A converter of 8-bit resolution

2 channels is available.

Conversion method is R-2R resistor ladder method.

Figure 5-9. D/A Converter Block Diagram

Function

3-wire serial I/O mode with

automatic transmit/receive

function

C bus mode

2-wire serial I/O mode

3-wire serial I/O mode

(MSB/LSB first switchable)

(MSB first)

(Dedicated baud rate

generator incorporated)

Serial Interface Channel 0

Serial Interface Channel 1

Serial Interface Channel 2

(MSB/LSB first switchable)

Internal Bus

Selector

D/A Conversion Value Set Register n

(DACSn)

REF1

DAMm

INTTMx

DACSn
Write

ANOn

D/A Converter
Mode Register

Asynchronous serial interface

(UART) mode (on-chip time

division transfer function)

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Figure 5-10. Serial Interface Channel 0 Block Diagram

Figure 5-11. Serial Interface Channel 1 Block Diagram

Internal Bus

Interrupt Request
Signal Generator

Handshake
Control
Circuit

Buffer RAM

Serial Clock Control Circuit

Selector

Serial Clock Counter

Serial I/O Shift Register 1 (SIO1)

Automatic Data Transmit/
Receive Address Pointer
(ADTP)

Automatic Data

Transmit/Receive

Interval Specification

5-Bit Counter

INTCSI1

/2-f

TO2

SI1/P20

SO1/P21

STB/TxD1/P23

BUSY/RxD1/P24

SCK1/P22

Match

Acknowledge
Output Circuit

Output
Latch

Serial I/O Shift

Internal Bus

Interrupt
Request
Signal
Generator

Serial Clock Counter

Start Condition/Stop
Condition/Acknowledge
Detection Circuit

Serial Clock

Control Circuit

Selector

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

INTCSI0

TO2

/2-f

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

Figure 5-12. Serial Interface Channel 2 Block Diagram

5.9 REAL-TIME OUTPUT PORT FUNCTIONS

Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently

with timer interrupt request and external interrupt request generation in order to output to off-chip. This is real-time

output function. And pins to output to off-chip are called real-time output ports.

By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control of

stepping motor, etc.

Figure 5-13. Real-Time Output Port Block Diagram

Internal Bus

P127

P120

Output Latch

Real-Time Output

Buffer Register

High-order 4 Bits

(RTBH)

Real-Time Output

Buffer Register

Low-order 4 Bits

(RTBL)

Real-Time Output Port Mode

Output Trigger

Control Circuit

INTP2

INTTM1

INTTM2

RxD0/SI2/P70

RxD1/BUSY/P24

Selector

ASCK/SCK2/P72

INTSER

INTSR/INTCSI2

INTST

-f

Internal Bus

Receive Buffer Register

(RXB/SIO2)

Direction Control Circuit

Receive Shift Register

(RXS)

Receive Control Circuit

Direction Control Circuit

Transmit Shift Register

(TXS/SIO2)

Transmit Control Circuit

SCK Output

Control Circuit

Baud Rate

Generator

TxD0/SO2/P71

TxD1/STB/P23

Selector

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

· Non-maskable :

· Maskable

: 19

· Software

Table 6-1. Interrupt Source List (1/2)

Interrupt Type

Note 1

Default

Priority

Name

Watchdog timer overflow

(watchdog timer mode 1 selected)

Interrupt Source

Trigger

Watchdog timer overflow

(interval timer mode selected)

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTCSI0

INTCSI1

INTSER

INTSR

INTCSI2

INTS

0006H

0008H

000AH

000CH

000EH

0010H

0014H

0016H

0018H

001AH

001CH

(C)

Internal/

External

Vector Table

Address

Basic

Configuration

Type

Note 2

INTWDT

Non-maskable

(A)

Internal

0004H

INTWDT

(B)

Pin input edge detection

External

Maskable

(B)

(D)

6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS

6.1 INTERRUPT FUNCTIONS

There are interrupt functions, 21 sources of three different kinds, as shown below.

End of serial interface channel 0

transfer

End of serial interface channel 1

transfer

Generation of serial interface channel

2 UART receive error

End of serial interface channel 2

UART reception

End of serial interface channel 2 3-

wire transfer

End of serial interface channel 2

UART transmission

Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated

simultaneously. 0 is the highest order and 17, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.

Internal

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

Table 6-1. Interrupt Source List (2/2)

Name

Interrupt Source

Reference time interval signal from watch

timer

Generation of match signal of 16-bit

timer register and capture/compare

Generation of match signal of 16-bit

timer register and capture/compare

Generation of match signal of 8-bit

timer/event counter 1

Generation of match signal of 8-bit timer/

event counter 2

End of conversion by A/D converter

BRK instruction execution

INTAD

BRK

0028H

003EH

(E)

Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated

simultaneously. 0 is the highest order and 17, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.

Interrupt

Type

Software

INTTM3

001EH

(B)

Internal/

External

Vector Table

Address

Basic

Configuration

Type

Note 2

Trigger

INTTM00

0020H

Internal

INTTM01

0022H

INTTM1

0024H

INTTM2

0026H

Note 1

Default

Priority

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

7. EXTERNAL DEVICE EXPANSION FUNCTIONS

The external device expansion functions connect external devices to areas other than the internal ROM, RAM and

SFR. Ports 4 to 6 are used for external device connection.

8. STANDBY FUNCTION

There are the following two standby functions to reduce the system power consumption.

· HALT mode : The CPU operating clock is stopped.

The average current consumption can be reduced by intermittent operation in combination with

the normal operating mode.

· STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is

stopped, so that the system operates with ultra-low power consumption using only the subsystem

clock.

Figure 8-1. Standby Function

Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on

the subsystem clock, set the MCC (bit 7 of the processor clock control register (PCC)) to stop the main system

clock. The STOP instruction cannot be used.

Caution

When the main system clock is stopped and the system is operated by the subsystem clock, the

subsystem clock should be switched again to the main system clock after the oscillation

stabilization time is secured by the program.

Remark

CSS: Bit 4 of processor clock control regisrer (PCC).

9. RESET FUNCTION

There are the following two reset methods.

External reset input by RESET pin

Internal reset by watchdog time runaway time detection

Main System
Clock Operation

STOP Mode
(Main system clock
oscillation stopped)

HALT Mode
(Clock supply to CPU is
stopped, oscillation)

Subsystem Clock
Operation

Note

HALT Mode

Note

(Clock supply to CPU is
stopped, oscillation)

Interrupt
Request

HALT
Instruction

STOP
Instruction

CSS=1

CSS=0

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

10. INSTRUCTION SET

(1) 8-bit instruction

MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, ROR4, ROL4, PUSH, POP, DBNZ

Note Except r = A

Second
Operand

First
Operand

#byte

Note

sfr

saddr

!addr16

PSW

[DE]

[HL]

[HL + Byte]

[HL + B]

[HL + C]

$addr16

None

ADD

ADDC

SUB

SUBC

AND

XOR

CMP

MOV

ROR

XCH

ROL

ADD

RORC

ADDC

ROLC

SUB

SUBC

AND

XOR

CMP

MOV

ADD

ADDC

SUB

SUBC

AND

XOR

CMP

INC

DEC

B, C

sfr

MOV

DBNZ

MOV

ADD

ADDC

SUB

SUBC

AND

XOR

CMP

saddr

MOV

DBNZ

INC

DEC

!addr16

MOV

PSW

MOV

PUSH

POP

[DE]

ROR4

[HL]

MOV

ROL4

[HL + Byte]

[HL + B]

[HL + C]

MOV

MULU

DIVUW

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(2) 16-bit instruction

MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Note Only when rp = BC, DE or HL

(3) Bit manipulation instruction

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

(4) Call instruction/branch instruction

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second Operand

First Operand

sfrp

saddrp

!addr16

#word

ADDW
SUBW

CMPW

MOVW

Note

MOVW

Note

XCHW

sfrp

MOVW

saddrp

MOVW

!addr16

MOVW

None

INCW, DECW
PUSH, POP

Second Operand

First Operand

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

$addr16

None

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

MOV1

BTCLR

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

MOV1

AND1

OR1
XOR1

MOV1

AND1

OR1
XOR1

MOV1

AND1

OR1
XOR1

MOV1

AND1

OR1
XOR1

MOV1

AND1

OR1
XOR1

Second Operand

First Operand

!addr16

!addr11

[addr5]

$addr16

Basic instruction

Compound
instruction

CALL
BR

CALLF

CALLT

BR, BC, BNC
BZ, BNZ

BT, BF
BTCLR
DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Test Conditions

Rating

Unit

Supply voltage

0.3 to +7.0

0.3 to V

+ 0.3

REF0

0.3 to V

+ 0.3

REF1

0.3 to V

+ 0.3

0.3 to +0.3

Input voltage

P00-P05, P07, P10-P17, P20-P27, P30-P37, P40-P47,

0.3 to V

+ 0.3

P50-P57, P64-P67, P70-P72, P120-P127, P130, P131,

X1, X2, XT2, RESET

P60-P63 N-ch Open-drain

0.3 to +16

Output voltage

0.3 to V

+ 0.3

Analog input voltage V

P10-P17 Analog input pin

0.3 to AV

REF0

+ 0.3

Output

1 pin

current, high

P01-P05, P30-P37, P56, P57, P60-P67, P120-P127 total

P10-P17, P20-P27, P40-P47, P50-P55, P70-P72,

P130, P131 total

Output

Note

1 pin

Peak value

current, low

rms value

P50-P55 total

Peak value

100

rms value

P56, P57, P60-P63 total

Peak value

100

rms value

P10-P17, P20-P27, P40-P47,

Peak value

P70-P72, P130, P131 total

rms value

P01-P05, P30-P37, P64-P67,

Peak value

P120-P127 total

rms value

Operating ambient

40 to +85

temperature

Storage

stg

65 to +150

temperature

Note rms value should be calculated as follows: [rms value] = [Peak value]

duty

Caution

Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter

or even momentarily. That is, the absolute maximuam ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions which ensure that the absolute maximum ratings are not exceeded.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Main System Clock Oscillation Circuit Characteristics (T

= 40 to +85

C, V

= 1.8 to 5.5 V)

Recommended
Circuit

TYP.

MAX.

5.0

500

Unit

MHz

Resonator

Ceramic

resonator

Crystal

resonator

External

clock

Parameter

Oscillator

frequency (fx)

Note 1

Oscillation

stabilization time

Note 2

Oscillator

frequency (fx)

Note 1

Oscillation

stabilization time

Note 2

X1 input

frequency (fx)

Note 1

X1 input

high/low level width

, t

)

Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions

1. When using the main system clock oscillator, wirinin the area enclosed with the broken line

should be carried out as follows to avoid an adverse effect from wiring capacitance.

· Wiring should be as short as possible.

· Wiring should not cross other signal lines.

· Wiring should not be placed close to a varying high current.

· The potential of the oscillator capacitor ground should be the same as V

SS1

· Do not ground wiring to a ground pattern in which a high current flows.

· Do not fetch a signal from the oscillator.

2. When the main system clock is stopped and the system is operated by the subsystem clock, the

subsystem clock should be switched again to the main system clock after the oscillation

stabilization time is secured in software.

MIN.

1.0

Test Conditions

= Oscillator

voltage range

After V

reaches oscil-

lator voltage range MIN.

= 4.5 to 5.5 V

X1 IC

PD74HCU04

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Subsystem Clock Oscillation Circuit Characteristics

= 40 to +85

C, V

= 1.8 to 5.5 V)

MIN.

Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after V

reaches oscillator voltage MIN.

Resonator

Crystal

resonator

External

clock

Parameter

Oscillator

frequency (f

)

Note 1

Oscillation

stabilization time

Note 2

XT1 input

frequency (f

)

Note 1

XT1 input

high/low level width

XTH

, t

XTL

)

Test Conditions

TYP.

32.768

1.2

MAX.

100

Unit

kHz

Cautions

1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line

should be carried out as follows to avoid an adverse effect from wiring capacitance.

· Wiring should be as short as possible.

· Wiring should not cross other signal lines.

· Wiring should not be placed close to a varying high current.

· The potential of the oscillator capacitor ground should be the same as V

SS1

· Do not ground wiring to a ground pattern in which a high current flows.

· Do not fetch a signal from the oscillator.

2. The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone

to misoperation due to noise than the main system clock. Therefore, when using the subsystem

clock, take care with the wiring.

= 4.5 to 5.5 V

Recommended Circuit

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Capacitance

= 25

= V

= 0 V)

Input

f = 1 MHz

capacitance

Measured pins returned to 0 V.

Input/output

f = 1 MHz

P01-P05, P10-P17,

capacitance

Measured pins returned to 0 V.

P20-P27, P30-P37,
P40-P47, P50-P57,
P64-P67, P70-P72,
P120-P127, P130, P131

P60-P63

Remark

The characteristics of the dual-function pins are the same as those of the port pins unless otherwise

specified.

XT1

IC XT2

XT1

XT2

PD74HCU04

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input voltage,

IH1

P10-P17, P21, P23, P30-P32,

= 2.7 to 5.5 V

0.7 V

high

P35-P37, P40-P47, P50-P57,

P64-P67, P71, P120-P127,

0.8 V

P130, P131

IH2

P00-P05, P20, P22, P24-P27,

= 2.7 to 5.5 V

0.8 V

P33, P34, P70, P72, RESET

0.85 V

IH3

P60-P63

= 2.7 to 5.5 V

0.7 V

(N-ch open-drain)

0.8 V

IH4

X1, X2

= 2.7 to 5.5 V

0.5

0.2

IH5

XT1/P07, XT2

4.5 V

5.5 V

0.8 V

2.7 V

4.5 V

0.9 V

Note

0.9 V

Input voltage,

IL1

P10-P17, P21, P23, P30-P32,

= 2.7 to 5.5 V

0.3 V

low

P35-P37, P40-P47, P50-P57,

P64-P67, P71, P120-P127,

0.2 V

P130, P131

IL2

P00-P05, P20, P22, P24-P27,

= 2.7 to 5.5 V

0.2 V

P33, P34, P70, P72, RESET

0.15 V

IL3

P60-P63

4.5 V

5.5 V

0.3 V

2.7 V

4.5 V

0.2 V

0.1 V

IL4

X1, X2

= 2.7 to 5.5 V

0.4

0.2

IL5

XT1/P07, XT2

4.5 V

5.5 V

0.2 V

2.7 V

4.5 V

0.1 V

Note

0.1 V

Output voltage,

= 4.5 to 5.5 V, I

= 1 mA

1.0

high

= 100

0.5

Output voltage,

OL1

P50-P57, P60-P63

= 4.5 to 5.5 V,

0.4

2.0

low

= 15 mA

P01-P05, P10-P17, P20-P27,

= 4.5 to 5.5 V,

0.4

P30-P37, P40-P47, P64-P67,

= 1.6 mA

P70-P72, P120-P127, P130,

P131

OL2

SB0, SB1, SCK0

= 4.5 to 5.5 V,

0.2 V

open-drain,

pulled-up (R = 1 k

)

OL3

= 400

0.5

Note

For use as P07, use an inverter to input the reverse phase of P07 to the XT2 pin.

Remark

The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input leakage

LIH1

= V

P00-P05, P10-P17, P20-P27,

current, high

P30-P37, P40-P47, P50-P57,

P60-P67, P70-P72, P120-P127,

P130, P131, RESET

LIH2

X1, X2, XT1/P07, XT2

LIH3

= 15 V

P60-P63

Input leakage

LIL1

= 0 V

P00-P05, P10-P17, P20-P27,

current, low

P30-P37, P40-P47, P50-P57,

P64-P67, P70-P72,

P120-P127, P130, P131, RESET

LIL2

X1, X2, XT1/P07, XT2

LIL3

P60-P63

Note

Output leakage

LOH

OUT

= V

current, high

Output leakage

LOL

OUT

= 0 V

current, low

Mask option pull-up

= 0 V, P60-P63

120

resistor

Software pull-up

= 0 V, P01-P05, P10-P17, P20-P27, P30-P37,

resistor

P40-P47, P50-P57, P64-P67, P70-P72, P120-P127,

P130, P131

Note

For P60 to P63 without on-chip pull-up resistor (specifiable by mask option), a low-level input leakage current

of 200

A (MAX.) flows only during the 1.5 clocks (no wait) after an instruction has been executed to read

out port 6 (P6) or port mode register 6 (PM6). Outside the period of 1.5 clocks following executing a read-

out instruction, the current is 3

A (MAX.).

Remark

The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 5.5 V)

= 5.0 V

10 %

Note 1

= 3.0 V

10 %

Note 2

0.6

1.8

= 2.0 V

10 %

Note 2

0.35

1.05

= 5.0 V

10 %

Note 1

6.5

19.5

= 3.0 V

10 %

Note 2

0.8

2.4

= 5.0 V

10 %

1.4

4.2

= 3.0 V

10 %

0.5

1.5

= 2.0 V

10 %

280

840

= 5.0 V

10 %

1.6

4.8

= 3.0 V

10 %

0.65

1.95

= 5.0 V

10 %

120

= 3.0 V

10 %

= 2.0 V

10 %

= 5.0 V

10 %

= 3.0 V

10 %

= 2.0 V

10 %

2.5

12.5

= 5.0 V

10 %

= 3.0 V

10 %

0.5

= 2.0 V

10 %

0.3

= 5.0 V

10 %

0.1

= 3.0 V

10 %

0.05

= 2.0 V

10 %

0.05

DD1

5.0 MHz Crystal oscillation
operating mode

= 2.5 MHz)

Note 3

5.0 MHz Crystal oscillation
operating mode
(f

= 5.0 MHz)

Note 4

5.0 MHz Crystal oscillation
HALT mode
(f

= 5.0 MHz)

Note 4

DD2

5.0 MHz Crystal oscillation
HALT mode
(f

= 2.5 MHz)

Note 3

DD3

32.768 kHz Crystal oscillation
operating mode

Note 6

DD4

32.768 kHz Crystal oscillation
HALT mode

Note 6

DD5

XT1 = V

STOP mode
When feedback resistor is used

DD6

XT1 = V

STOP mode
When feedback resistor is unused

Notes 1. Operating in high-speed mode (when set the processor clock control register (PCC) to 00H).

2. Operating in low-speed mode (when set the PCC to 04H).

3. Operation with f

= f

/2 (when oscillation mode selection register (OSMS) is set to 00H)

4. Operation with f

= f

(when OSMS is set to 01H)

5. This current flows in the V

and AV

pins. However, a current flowing in the A/D converter, D/A converter,

and on-chip pull-up resistor are not included.

6. When the main system clock is halted

Parameter Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Power supply

current

Note 5

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

AC Characteristics

(1) Basic operation

= 40 to +85

C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Cycle time

Operating on main system clock

= 2.7 to 5.5 V

0.8

(Min. instruction

= 2.5 MHz)

Note 1

2.0

execution time)

Operating on main system clock

= 3.5 to 5.5 V

0.4

= 5.0 MHz)

Note 2

= 2.7 to 3.5 V

0.8

Operating on subsystem clock

Note 3

122

125

TI00 input high/

TIH00

3.5 V

5.5 V

2/f

sam

+0.1

Note 4

low-level width

TIL00

2.7 V

< 3.5 V

2/f

sam

+0.2

Note 4

2/f

sam

+0.5

Note 4

TI01 input high/

TIH01

= 2.7 to 5.5 V

low-level width

TIL01

TI1, TI2, TI5, TI6

TI1

= 4.5 to 5.5 V

MHz

input frequency

275

kHz

TI1, TI2, TI5, TI6

TIH1

= 4.5 to 5.5 V

100

input high/

TIL1

1.8

low-level width

Interrupt request

INTH

INTP0

3.5 V

5.5 V 2/f

sam

+0.1

Note 4

input high/

INTL

2.7 V

< 3.5 V 2/f

sam

+0.2

Note 4

low-level width

2/f

sam

+0.5

Note 4

INTP1-INTP5, P40-P47

= 2.7 to 5.5 V

RESET low

RSL

= 2.7 to 5.5 V

level width

Notes 1. Operation with f

= f

/2 (when oscillation mode selection register (OSMS) is set to 00H)

2. Operation with f

= f

(when OSMS is set to 01H)

3. Value when external clock is used. When a crystal resonator is used, it is 114

s (MIN.)

4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of f

sam

is possible between f

, f

/32, f

/64 and f

/128 (when N= 0 to 4).

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(2) Read/write operation

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

ASTB high-level width

ASTH

0.85t

Address setup time

ADS

0.85t

Address hold time

ADH

Data input time from address

ADD1

(2.85 + 2n)t

ADD2

(4 + 2n)t

100

Data input time from RD

RDD1

(2 + 2n)t

100

RDD2

(2.85 + 2n)t

100

Read data hold time

RDH

RD low-level width

RDL1

(2 + 2n)t

RDL2

(2.85 + 2n)t

WAIT

input time from RD

RDWT1

0.85t

RDWT2

WAIT

input time from WR

WRWT

WAIT low-level width

WTL

(1.15 + 2n)t

(2 + 2n)t

Write data setup time

WDS

(2.85 + 2n)t

100

Write data hold time

WDH

WR low-level width

WRL

(2.85 + 2n)t

delay time from ASTB

ASTRD

delay time from ASTB

ASTWR

0.85t

+ 20

ASTB

delay time from

RDAST

0.85t

1.15t

+ 20

in external fetch

Address hold time from

RDADH

0.85t

1.15t

+ 50

in external fetch

Write data output time from RD

RDWD

Write data output time from WR

WRWD

Address hold time from WR

WRADH

0.85t

1.15t

+ 40

delay time from WAIT

WTRD

1.15t

+ 40

3.15t

+ 40

delay time from WAIT

WTWR

1.15t

+ 30

3.15t

+ 30

Remarks

MCS: Oscillation mode selection register (OSMS) bit 0

PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0

= T

n indicates number of waits.

(a) When MCS = 1, PCC2 to PCC0 = 000B (T

= 40 to +85

C, V

= 4.5 to 5.5 V)

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(b) When except MCS = 1, PCC2 to PCC0 = 000B (T

= 40 to +85

C, V

= 2.0 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

ASTB high-level width

ASTH

= 2.7 to 5.5 V

150

Address setup time

ADS

= 2.7 to 5.5 V

150

Address hold time

ADH

= 2.7 to 5.5 V

0.4t

0.37t

Data input time from address

ADD1

= 2.7 to 5.5 V

(3 + 2n)t

160

(3 + 2n)t

320

ADD2

= 2.7 to 5.5 V

(4 + 2n)t

200

(4 + 2n)t

300

Data input time from RD

RDD1

= 2.7 to 5.5 V

(1.4 + 2n)t

(1.37 + 2n)t

120

RDD2

= 2.7 to 5.5 V

(2.4 + 2n)t

(2.37 + 2n)t

120

Read data hold time

RDH

RD low-level width

RDL1

= 2.7 to 5.5 V

(1.4 + 2n)t

(1.37 + 2n)t

RDL2

= 2.7 to 5.5 V

(2.4 + 2n)t

(2.37 + 2n)t

WAIT

input time from RD

RDWT1

= 2.7 to 5.5 V

100

200

RDWT2

= 2.7 to 5.5 V

100

200

WAIT

input time from WR

WRWT

= 2.7 to 5.5 V

100

200

WAIT low-level width

WTL

(1 + 2n)t

(2 + 2n)t

Write data setup time

WDS

= 2.7 to 5.5 V

(2.4 + 2n)t

(2.37 + 2n)t

100

Write data hold time

WDH

WR low-level width

WRL

= 2.7 to 5.5 V

(2.4 + 2n)t

(2.37 + 2n)t

delay time from ASTB

ASTRD

= 2.7 to 5.5 V

0.4t

0.37t

delay time from ASTB

ASTWR

= 2.7 to 5.5 V

1.4t

1.37t

Remarks

MCS: Oscillation mode selection register (OSMS) bit 0

PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0

= T

n indicates number of waits.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(b) When except MCS = 1, PCC2 to PCC0 = 000B (T

= 40 to +85

C, V

= 2.0 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

ASTB

delay time from

RDAST

+ 20

in external fetch

Address hold time from

RDADH

+ 50

in external fetch

Write data output time from RD

RDWD

= 2.7 to 5.5 V

0.4t

0.37t

Write data output time from WR

WRWD

= 2.7 to 5.5 V

120

Address hold time from WR

WRADH

= 2.7 to 5.5 V

+ 60

+ 120

delay time from WAIT

WTRD

= 2.7 to 5.5 V

0.6t

+ 180

2.6t

+ 180

0.63t

+ 350

2.63t

+ 350

delay time from WAIT

WTWR

= 2.7 to 5.5 V

0.6t

+ 120

2.6t

+ 120

0.63t

+ 240

2.63t

+ 240

Remarks

MCS: Oscillation mode selection register (OSMS) bit 0

PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0

= T

n indicates number of waits.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(3) Serial interface (T

= 40 to +85

C, V

= 1.8 to 5.5 V)

(a) Serial interface channel 0

(i) 3-wire serial I/O mode (SCK0... Internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

800

2.7 V

4.5 V

1600

2.0 V

2.7 V

3200

4800

KH1

, t

KL1

= 4.5 to 5.5 V

KCY1

/2 50

KCY1

/2 100

SIK1

4.5 V

5.5 V

100

2.7 V

4.5 V

150

2.0 V

2.7 V

300

400

KSI1

400

KSO1

C = 100 pF

Note

300

Note

C is the load capacitance of SO0 output line.

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

KCY2

4.5 V

5.5 V

800

2.7 V

4.5 V

1600

2.0 V

2.7 V

3200

4800

KH2

, t

KL2

4.5 V

5.5 V

400

2.7 V

4.5 V

800

2.0 V

2.7 V

1600

2400

SIK2

2.0 V

5.5 V

100

150

KSI2

400

KSO2

C = 100 pF

Note

= 2.0 to 5.5V

300

500

, t

When using external device

160

expansion function

When not using external device

1000

expansion function

SCK0 cycle time

SCK0 high/low-level

width

SI0 setup time (to

SCK0

)

SI0 hold time (from

SCK0

)

SO0 output delay time

from SCK0

SCK0 rise, fall time

(ii) 3-wire serial I/O mode (SCK0... External clock input)

KCY1

Note

C is the load capacitance of SO0 output line.

SCK0 cycle time

SCK0 high/low-level

width

SI0 setup time (to

SCK0

)

SI0 hold time (from

SCK0

)

SO0 output delay time

from SCK0

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(iii) I

C bus mode (SCL ... Internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCL cycle time

KCY3

R = 1 K

2.7 V

5.5 V

C = 100 pF

Note

2.0 V

< 2.7 V

SCL high-level width

KH3

= 2.7 to 5.5 V

KCY3

160

KCY3

190

SCL low-level width

KL3

= 4.5 to 5.5 V

KCY3

100

SDA0, SDA1 setup time

SIK3

2.7 V

5.5 V

200

(to SCL

)

2.0 V

< 2.7 V

300

400

SDA0, SDA1 hold time

KSI3

(from SCL

)

SDA0, SDA1 output delay

KSO3

4.5 V

5.5 V

300

time from SCL

2.0 V

< 4.5 V

500

600

SDA0, SDA1

from SCL

KSB

200

SDA0, SDA1

from SCL

SDA0, SDA1

from SCL

SBK

= 2.0 to 5.5 V

400

500

SDA0, SDA1 high-level width t

SBH

500

Note

R and C are the load resistors and load capacitance of the SCL, SDA0, and SDA1 output line.

(iv) I

C bus mode (SCL ... External clock input)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCL cycle time

KCY4

1000

SCL high-/low-level width

KH4

= 2.0 to 5.5 V

400

KL4

600

SDA0, SDA1 setup time

SIK4

= 2.0 to 5.5 V

200

(to SCL

)

300

SDA0, SDA1 hold time

KSI4

(from SCL

)

SDA0, SDA1 output delay

KSO4

R = 1 k

4.5 V

5.5 V

300

time from SCL

C = 100 pF

Note

2.0 V

< 4.5 V

500

600

SDA0, SDA1

from SCL

KSB

200

SDA0, SDA1

from SCL

SDA0, SDA1

from SCL

SBK

= 2.0 to 5.5 V

400

500

SDA0, SDA1 high-level width

SBH

= 2.0 to 5.5 V

500

800

SCL rise, fall time

When using external device expansion

160

function

When not using external device

expansion function

Note

R and C are the load resistors and load capacitance of the SDA0 and SDA1 output line.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(vi) 2-wire serial I/O mode (SCK0... External clock input)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

KCY6

2.7 V

5.5 V

1600

2.0 V

< 2.7 V

3200

4800

KH6

2.7 V

5.5 V

650

2.0 V

< 2.7 V

1300

2100

KL6

2.7 V

5.5 V

800

2.0 V

< 2.7 V

1600

2400

SIK6

= 2.0 to 5.5 V

100

150

KSI6

KCY6

KSO6

4.5 V

5.5 V

300

2.0 V

< 4.5 V

500

800

, t

When using external device

160

expansion function

When not using external device

1000

expansion function

R = 1 k

C = 100 pF

Note

(v) 2-wire serial I/O mode (SCK0... Internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK0 cycle time

KCY5

R = 1 k

2.7 V

5.5 V

1600

C = 100 pF

Note

3200

4800

SCK0 high-level width

KH5

= 2.7 to 5.5 V

KCY5

/2 160

KCY5

/2 190

SCK0 low-level width

KL5

= 4.5 to 5.5 V

KCY5

/2 50

KCY5

/2 100

SB0, SB1 setup time

SIK5

4.5 V

5.5 V

300

(to SCK0

)

2.7 V

4.5 V

350

2.0 V

2.7 V

400

500

SB0, SB1 hold time

KSI5

600

(from SCK0

)

SB0, SB1 output delay

KSO5

300

time from SCK0

Note

R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.

Note

R and C are the load resistors and load capacitance of the SB0 and SB1 output line.

SCK0 cycle time

SCK0 high-level width

SCK0 low-level width

SB0, SB1 setup time

(to SCK0

)

SB0, SB1 hold time

(from SCK0

)

SB0, SB1 output delay

time from SCK0

SCK0 rise, fall time

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(b) Serial interface channel 1

(i) 3-wire serial I/O mode (SCK1...Internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK1 cycle time

KCY7

4.5 V

5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

SCK1 high/low-level width

KH7

, t

KL7

= 4.5 to 5.5 V

KCY7

/250

KCY7

/2100

SI1 setup time (to SCK1

)

SIK7

4.5 V

5.5 V

100

2.7 V

< 4.5 V

150

2.0 V

< 2.7 V

300

400

SI1 hold time (from SCK1

)

KSI7

400

SO1 output delay time from SCK1

KSO7

C = 100 pF

Note

300

(ii) 3-wire serial I/O mode (SCK1...External clock input)

Note

C is the load capacitance of the SO1 output line.

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK1 cycle time

KCY8

4.5 V

5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

SCK1 high/low-level width

KH8

, t

KL8

4.5 V

5.5 V

400

2.7 V

< 4.5 V

800

2.0 V

< 2.7 V

1600

2400

SI1 setup time (to SCK1

)

SIK8

= 2.0 to 5.5 V

100

150

SI1 hold time (from SCK1

)

KIS8

400

SO1 output delay time from SCK1

KSO8

C = 100 pF

Note

= 2.0 to 5.5 V

300

500

SCK1 rise, fall time

, t

When using external device

160

expansion function

When not using external device

1000

expansion function

Note

C is the load capacitance of the SO1 output line.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK1 cycle time

KCY9

4.5 V

5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

SCK1 high/low-level width

KH9

, t

KL9

= 4.5 to 5.5 V

KCY9

/250

KCY9

/2100

SI1 setup time (to SCK1

)

SIK9

4.5 V

5.5 V

100

2.7 V

< 4.5 V

150

2.0 V

< 2.7 V

300

400

SI1 hold time (from SCK1

)

KSI9

400

SO1 output delay time from SCK1

KSO9

C = 100 pF

Note

300

STB

from SCK1

SBD

KCY9

/2100

KCY9

/2+100

Strobe signal high-level width

SBW

2.7 V

< 5.5 V

KCY9

+30

2.0 V < V

< 2.7 V

KCY9

+60

KCY9

+90

Busy signal setup time

BYS

100

(to busy signal detection timing)

Busy signal hold time

BYH

4.5 V

5.5 V

100

(from busy signal detection timing)

2.7 V

< 4.5 V

150

2.0 V

< 2.7 V

200

300

SCK1

from busy inactive

SPS

KCY9

Note

C is the load capacitance of the SO1 output line.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK1 cycle time

KCY10

4.5 V

5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

SCK1 high/low-level width

KH10,

KL10

4.5 V

5.5 V

400

2.7 V

< 4.5 V

800

2.0 V

< 2.7 V

1600

2400

SI1 setup time (to SCK1

)

SIK10

= 2.0 to 5.5 V

100

150

SI1 hold time (from SCK1

)

KSI10

400

SO1 output delay time from SCK1

KSO10

C = 100 pF

Note

= 2.0 to 5.5 V

300

500

SCK1 rise, fall time

R10,

F10

When using external device

160

expansion function

When not using external device

1000

expansion function

Note

C is the load capacitance of the SO1 output line.

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

(c) Serial interface channel 2

(i) 3-wire serial I/O mode (SCK2...Internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK2 cycle time

4.5 V

5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

SCK2 high/low-level width

= 4.5 to 5.5 V

KCY11

/250

KCY11

/2100

SI2 setup time (to SCK2

)

4.5 V

5.5 V

100

2.7 V

< 4.5 V

150

2.0 V

< 2.7 V

300

400

SI2 hold time (from SCK2

)

400

SO2 output delay time from SCK2

C = 100 pF

Note

300

Note

C is the load capacitance of the SO2 output line.

KCY11

KH11

, t

KL11

SIK11

KSI11

KSO11

(ii) 3-wire serial I/O mode (SCK2 ... External clock input)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK2 cycle time

KCY12

4.5 V

< 5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

SCK2 high-/low-level width

KH12

4.5 V

5.5 V

400

KL12

2.7 V

< 4.5 V

800

2.0 V

< 2.7 V

1600

2400

SI2 setup time (to SCK2

)

SIK12

= 2.0 to 5.5 V

100

150

SI2 hold time (from SCK2

)

KSI12

400

SO2 output delay time from SCK2

KSO12

C = 100 pF

Note

= 2.0 to 5.5 V

300

500

SCK2 rise, fall time

R12

Other than below

160

F12

= 4.5 to 5.5 V

When not using external device

expansion function

Note

C is the load capacitance of the SO2 output line.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(iii) UART mode (Dedicated baud rate generator output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Transfer rate

4.5 V

5.5 V

78125

bps

2.7 V

< 4.5 V

39063

bps

2.0 V

< 2.7 V

19531

bps

9766

bps

(iv) UART mode (External clock input)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

ASCK cycle time

KCY13

4.5 V

5.5 V

800

2.7 V

< 4.5 V

1600

2.0 V

< 2.7 V

3200

4800

ASCK high-/low-level width

KH13,

KL13

4.5 V

5.5 V

400

2.7 V

< 4.5 V

800

2.0 V

< 2.7 V

1600

2400

Transfer rate

4.5 V

5.5 V

39063

bps

2.7 V

< 4.5 V

19531

bps

2.0 V

< 2.7 V

9766

bps

6510

bps

ASCK rise, fall time

R13,

F13

= 4.5 to 5.5 V,

1000

when not using external device

expansion function.

160

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

UART mode (external clock input) :

A/D Converter Characteristics (T

= 40 to +85

C, V

= 2.7 to 5.5 V, AV

= V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

Note

1.0

Conversion time

CONV

100

Sampling time

SAMP

12/fxx

Analog input voltage

IAN

REF0

Reference voltage

REF0

2.7

REF0

current

REF0

When A/D converter is operating

Note 2

500

1500

When A/D converter is not operating

Note 3

Resistance between AV

REF0

and

REF0

When A/D conversion is not performed

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

R = 2 M

Note 1

1.2

R = 4 M

Note 1

0.8

R = 10 M

Note 1

0.6

Settling time

REF1

= 4.5 to 5.5 V

C=30pF

Note 1

Output resistance

Note 2

Analog reference voltage

REF1

2.7

REF1

current

REF1

Note 2

2.5

Resistance between AV

REF1

and AV

AIREF1

DACS0, DACS1 = 55H

Note 2

D/A Converter Characteristics (T

= 40 to +85

C, V

= 2.7 to 5.5 V, AV

= V

= 0 V)

Notes 1. Overroll error excluding quantization error (

1/2 LSB). It is indicated as a ratio to the full-scale value.

2. The current flowing to AV

REF0

pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1.

3. The current flowing to AV

REF0

pin when bit 7 (CS) of the A/D converter mode regidter (ADM) is 0.

Remark

: Main system clock frequency (f

or f

/2)

: Main system clock oscillation frequency

Notes 1. R and C denote D/A converter output pin load resistance and load capacitance, respectively.

2. Value for 1 D/A converter channel

Remark DACS0 and DACS1: D/A conversion value setting register 0 and 1

KCY13

KH13

KL13

F13

R13

ASCK

Preliminary Data Sheet

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T

= 40 to +85

Note

In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS) , selection
of 2

and 2

to 2

is possible.

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Data retention power

DDDR

1.8

5.5

supply voltage

Data retention power

DDDR

= 1.8 V

0.1

supply current

Subsystem clock stop and feed-back resistor

disconnected

Release signal set time

SREL

Oscillation stabiliation

WAIT

Release by RESET

/fx

wait time

Release by interrupt

Note

Remark

: Main system clock frequency (f

or f

/2)

: Main system clock oscillatior frequency

Data Retention Timing (STOP Mode Release by RESET)

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

SREL

WAIT

STOP Instruction Execution

STOP Mode

Data Retension Mode

HALT Mode

Operating Mode

Standby Release Signal
(Interrupt Request)

DDDR

SREL

WAIT

RESET

STOP Instruction Execution

STOP Mode

Data Retension Mode

Internal Reset Operation

HALT Mode

Operating Mode

DDDR

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

80 PIN PLASTIC QFP (14

14)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

P80GC-65-8BT

0.825

0.032

14.00±0.20

0.551+0.009

0.008

1.70 MAX.

0.067 MAX.

0.17

0.007+0.001

0.003

+0.03

0.07

+0.009

0.008

14.00±0.20

0.551+0.009

0.008

17.20±0.20

0.677±0.008

0.825

0.032

0.32±0.06

0.013+0.002

0.003

0.13

0.005

0.65 (T.P.)

0.026 (T.P.)

1.60±0.20

0.063±0.008

0.80±0.20

0.031+0.009

0.008

0.10

0.004

1.40±0.10

0.055±0.004

0.125±0.075

0.005±0.003

17.20±0.20

0.677±0.008

detail of lead end

12. PACKAGE DRAWINGS

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

ITEM

MILLIMETERS

INCHES

0.5 (T.P.)

0.10

0.004

0.020 (T.P.)

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.

14.0±0.2

0.551+0.009

0.008

12.0±0.2

0.472+0.009

0.008

12.0±0.2

0.472+0.009

0.008

14.0±0.2

0.551+0.009

0.008

1.25

0.049

0.22

0.009±0.002

P80GK-50-BE9-4

1.27 MAX.

0.050 MAX.

1.0±0.2

0.039+0.009

0.008

0.5±0.2

0.020+0.008

0.009

0.145

0.006±0.002

0.10

0.004

1.05

0.041

0.05±0.05

0.002±0.002

5°±5°

+0.05

0.04

+0.055

0.045

detail of lead end

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for developing systems using the

PD780058Y subseries.

Refer to (5) Cautions when the development tools are used.

(1) Language processing software

RA78K/0

78K/0 series common assembler package

CC78K/0

78K/0 series common C compiler package

DF780058

PD780058 subseries common device file

CC78K/0-L

78K/0 series common C compiler library source file

(2) Flash memory writing tools

Flashpro II

Dedicated flash programmer for microcomputers incorporating flash memory

(Part number: FL-PR2)

FA-80GC

Note

Adapter for flash memory writing

FA-80GK

Note

Note Under development

(3) Debugging tools

When using the IE-78K0-NS in-circuit emulator

IE-78K0-NS

78K/0 series common in-circuit emulator

IE-70000-MC-PS-B

Power supply unit for IE-78K0-NS

IE-70000-98-IF-C

Interface adapter necessary when a PC-9800 series computer (except notebook-type

personal computer) is used as host machine

IE-70000-CD-IF

PC card and interface cable necessary when a PC-9800 series notebook-type personal

computer is used as host machine

IE-70000-PC-IF-C

Interface adapter necessary when an IBM PC/AT

or a compatible machine is used as

host machine

IE-780308-NS-EM1

Note

Emulation board common to the

PD780308 subseries

NP-80GC

Emulation probe for 80-pin plastic QFP (GC-8BT type)

NP-80GK

Note

Emulation probe for 80-pin plastic TQFP (GK-BE9 type)

TGK-080SDW

Conversion adapter to connect the board of the target system to be mounted on 80-pin

plastic TQFP (GK-BE9 type) and NP-80GK

EV-9200GC-80

Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-8BT

type)

ID78K0-NS

Integrated debugger for IE-78K0-NS

SM78K0

78K/0 series common system simulator

DF780058

PD780058 subseries common device file

Note Under development

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

When using the IE-78001-R-A in-circuit emulator

IE-78001-R-A

78K/0 series common in-circuit emulator

IE-70000-98-IF-B

Interface adapter necessary when a PC-9800 series computer (except notebook-type

IE-70000-98-IF-C

personal computer) is used as host machine

IE-70000-PC-IF-B

Interface adapter necessary when an IBM PC/AT or a compatible machine is used

IE-70000-PC-IF-C

as host machine

IE-78000-R-SV3

Interface adapter and cable necessary when an EWS is used as host machine

IE-780308-NS-EM1

Note

Emulation board common to the

PD780308 subseries

IE-780308-R-EM

IE-78K0-R-EX1

Note

Emulation probe conversion board necessary when the IE-780308-NS-EM1 is used in

the IE-78001-R-A.

EP-78230GC-R

Emulation probe for 80-pin plastic QFP (GC-8BT type)

EP-78054GK-R

Emulaiton probe for 80-pin plastic TQFP (GK-BE9 type)

TGK-080SDW

Conversion adapter to connect the board of the target system to be mounted on 80-pin

plastic TQFP (GK-BE9 type) and EP-78054GK-R

EV-9200GC-80

Socket to be mounted on the board of the target system made for the 80-pin plastic

QFP (GC-8BT type)

ID78K0

Integrated debugger for IE-78001-R-A

SM78K0

78K/0 series common system simulator

DF780058

PD780058 subseries common device file

Note Under development

(4) Real-time OS

RX78K/0

Real-time OS for 78K/0 series

MX78K0

OS for 78K/0 series

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

(5) Cautions when the development tools are used

The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780058.

The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and DF780058.

Flashpro II, FA-80GC, FA-80GK, NP-80GC, and NP-80GK are products of Naito Densei Machida Mfg. Co.,

Ltd. (TEL: (044)822-3813). Contact an NEC distributor when purchasing these products.

TGK-080SDW is a product of Tokyo Eletech Corp.

Inquiry : Daimaru Kogyo, Ltd.

Electronics Dept. (TEL: Tokyo (03) 3820-7112)

Electronics 2nd Dept. (TEL: Osaka (06) 244-6672)

Refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools.

Host machines and OSs compatible with the software are as follows:

Host Machine [OS]

EWS

PC-9800 Series [Windows

]

HP9000 series 700

[HP-UX

]

IBM PC/AT and compatible machines

SPARCstation

[SunOS

]

Software

[Japanese/English Windows]

NEWS

(RISC) [NEWS-OS

]

RA78K/0

Note

CC78K/0

Note

ID78K0-NS

ID78K0

SM78K0

RX78K/0

Note

MX78K0

Note

Note DOS based software

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

APPENDIX B. RELATED DOCUMENTS

Documents Related Devices

Document Name

Document No.

Japanese

English

PD780058, 780058Y Subseries User's Manual

U12013J

U12013E

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y Data Sheet

U12328J

This document

PD78F0058Y Preliminary Product Information

U12324J

U12324E

78K/0 Series User's Manual - Instruction

U12326J

U12326E

78K/0 Series Instruction Table

U10903J

78K/0 Series Instruction Set

U10904J

Development Tool Documents (User's Manual)

Document Name

Document No.

Japanese

English

RA78K0 Assembler Package

Operation

U11802J

U11802E

Assembly Language

U11801J

U11801E

Structured Assembly

U11789J

U11789E

Language

RA78K Series Structured Assembler Preprocessor

U12323J

EEU-1402

CC78K0 C Compiler

Operation

U11517J

U11517E

Language

U11518J

U11518E

CC78K/0 C Compiler Application Note

Programming Know-How

U13034J

U13034E

CC78K Series Library Source File

U12322J

IE-78K0-NS

Planned

IE-78001-R-EM

Planned

IE-780308-NS-EM1

Planned

IE-780308-R-EM

U11362J

U11362E

EP-78230

EEU-985

EEU-1515

EP-78054GK-R

EEU-932

EEU-1468

SM78K0 System Simulator Windows Based

Reference

U10181J

U10181E

SM78K Series System Simulator

External Part User Open

U10092J

U10092E

Interface Specifications

ID78K0-NS Integrated Debugger PC Based

Reference

U12900J

Planned

ID78K0 Integrated Debugger EWS Based

Reference

U11151J

ID78K0 Integrated Debugger PC Based

Reference

U11539J

U11539E

ID78K0 Integrated Debugger Windows Based

Guide

U11649J

U11649E

Caution

The documents listed above are subject to change without notice. Be sure to use the latest

documents for designing your system.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

Documents Related to Embedded Software (User's Manual)

Document Name

Document No.

Japanese

English

78K/0 Series Real-Time OS

Fundamentals

U11537J

U11537E

Installation

U11536J

U11536E

78K/0 Series OS MX78K0

Fundamental

U12257J

U12257E

Other Related Documents

Document Name

Document No.

Japanese

English

IC Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

Quality Grades on NEC Semiconductor Devices

C11531J

C11531E

NEC Semiconductor Device Reliability/Quality Control System

C10983J

C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C11892J

C11892E

Semiconductor Device Quality/Reliability Handbook

C12769J

Microcomputer Product Series Guide

U11416J

Caution

The documents listed above are subject to change without notice. Be sure to use the latest

documents for designing your system.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Data Sheet

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J98. 11

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

FIP and IEbus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States
and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked
as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use these components in an I

system, provided that the system conforms to the I

C Standard Specification as defined by Philips.

Document Outline

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Document Outline

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