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MOS INTEGRATED CIRCUIT

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PD77113A, 77114

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS

Document No. U14373EJ3V0DS00 (3rd edition)
Date Published February 2001 N CP(K)
Printed in Japan

DATA SHEET

1999

DESCRIPTION

The

PD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs).

Compared with the

PD77016 family, these DSPs have improved power consumption and are ideal for battery-

powered mobile terminals such as PDAs and cellular phones.

Both mask ROM and RAM models are available.

For details of the functions of these DSPs, refer to the following User's Manuals:

PD77111 Family User's Manual

: U14623E

PD77016 Family User's Manual - Instructions : U13116E

FEATURES

Instruction cycle (operating clock)

PD77113A : 13.3 ns MIN (75 MHz MAX)

PD77114

: 13.3 ns MIN (75 MHz MAX)

Memory

· Internal instruction memory

PD77113A : RAM 3.5K words

32 bits

Mask ROM 48K words

32 bits

PD77114

: RAM 3.5K words

32 bits

Mask ROM 48K words

32 bits

· Data memory

PD77113A : RAM 16K words

16 bits

2 banks

Mask ROM 32K words

16 bits

2 banks

PD77114

: RAM 16K words

16 bits

2 banks

Mask ROM 32K words

16 bits

2 banks

External memory space 8K words

16 bits

2 banks

ORDERING INFORMATION

Part Number

Package

PD77113AF1-xxx-CN1

80-pin plastic fine-pitch BGA (9

PD77114GC-xxx-9EU

100-pin plastic TQFP (fine pitch) (14

14)

Remark xxx indicates ROM code suffix.

The mark

shows major revised points.

ta S

heet U

14373E

J3V

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77113A

, 77114

Item

PD77016

PD77019

PD77018A

PD77019-013

PD77111

PD77112

PD77113A

PD77114

Memory space

(words

bits)

Instruction cycle (at maximum speed)

Multiple

Serial interface (two channels)

Supply voltage

Package

Internal instruction RAM

Internal instruction ROM

Data RAM

(X/Y memory)

Data ROM

(X/Y memory)

External data memory

(X/Y memory)

External instruction

memory

1.5K

256

24K

None

31.75K

16 each

None

12K

16 each

16K

16 each

48K

5 V

3 V

DSP core: 2.5 V

I/O pins : 3 V

160-pin QFP

None

48K

16 each

16K

16 each

None

16K

16 each

30 ns (33 MHz)

100-pin TQFP

80-pin TQFP

80-pin FBGA

100-pin TQFP

116-pin BGA

1, 2, 3, 4, 8 (mask option)

Fixed to

Integer of

1 to 16 (mask option)

16.6 ns (60 MHz)

13.3 ns (75 MHz)

Channels 1 and 2

have same function.

Channel 1 has same function as PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec).

PD77110

35.5K

24K

16 each

32K

16 each

15.3 ns (65 MHz)

Integer of

1 to 8

(external pin)

None

3.5K

48K

16K

16 each

32K

16 each

None

16 each

80-pin FBGA

100-pin TQFP

DSP FUNCTION LIST

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

PIN CONFIGURATION

80-pin plastic fine-pitch BGA (9

×
×
×
×

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PD77113AF1-xxx-CN1

(Bottom View)

(Top View)

Index mark

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

HCS

RESET

GND

TDI

HD1

INT3

TDO

HD2

GND

CLKIN

SCK1

TMS

HA0

SOEN2

GND

SOEN1

SIEN2

TRST

GND

HD0

INT2

SI2

HD7

HD3

INT1

TCK

HD6

INT4/WAKEUP

Note

GND

HD5

HWR

SI1

TICE

HRD

GND

SORQ1

SIEN1

SO2

HA1

SO1

SCK2

CLKOUT

GND

SIAK1

HD4

Note The function of the WAKEUP pin can be activated or deactivated by a mask option.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

100-pin plastic TQFP (fine-pitch) (14

×
×
×
×

14) (Top View)

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PD77114GC-xxx-9EU

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

GND

NC
NC

DA12
DA11
DA10

DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0

D15
D14
D13
D12
D11
D10

D9
D8

CLKIN
CLKOUT
HA1
HA0
HWR
HRD
HCS
HWE
HRE
GND
EV

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
P0
P1
P2
P3
GND

X/Y

I.C.

MRD

MWR

BSTB

HOLDAK

HOLDRQ

INT1

INT2

INT3

INT4/WAKEUP

Note

RESET

GND

TRST

TMS

TDI

TCK

TICE

TDO

GND

SI1

SIEN1

SCK1

SIAK1

SO1

SORQ1

SOEN1

SOEN2

SO2

SCK2

SIEN2

SI2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

Note The functions can be activated or deactivated by a mask option.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

GND

DA12

TDO

DA11

TICE

DA10

HD7

TCK

DA9

HD6

TD1

DA8

HD5

TMS

DA7

HD4

TRST

DA6

HD3

DA5

GND

HD2

GND

DA4

SI1

HD1

RESET

DA3

SIEN1

HD0

INT4/WAKEUP

Note

DA2

SCK1

INT3

DA1

SIAK1

GND

INT2

DA0

SO1

HRE

INT1

D15

SORQ1

HWE

HOLDRQ

D14

SOEN1

HCS

HOLDAK

D13

SOEN2

HRD

BSTB

D12

SO2

HWR

D11

SCK2

HA0

MWR

D10

SIEN2

HA1

MRD

SI2

CLKOUT

I.C.

CLKIN

X/Y

100

Note The function of the WAKEUP pin can be activated or deactivated by a mask option.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

PIN NAME

BSTB

: Bus Strobe

CLKIN

: Clock Input

CLKOUT

: Clock Output

D0 - D15

: 16-bit Data Bus

DA0 - DA12

: External Data Memory Address Bus

: Power Supply for I/O Pins

GND

: Ground

HA0, HA1

: Host Data Access

HCS

: Host Chip Select

HD0 - HD7

: Host Data Bus

HOLDAK

: Hold Acknowledge

HOLDRQ

: Hold Request

HRD

: Host Read

HRE

: Host Read Enable

HWE

: Host Write Enable

HWR

: Host Write

I.C.

: Internally Connected

INT1 - INT4

: Interrupt

: Power Supply for DSP Core

MRD

: Memory Read Output

MWR

: Memory Write Output

: Non-Connection

: Not Used

P0 - P3

: Port

RESET

: Reset

SCK1, SCK2

: Serial Clock Input

SI1, SI2

: Serial Data Input

SIAK1

: Serial Input Acknowledge

SIEN1, SIEN2

: Serial Input Enable

SO1, SO2

: Serial Data Output

SOEN1, SOEN2 : Serial Output Enable

SORQ1

: Serial Output Request

TCK

: Test Clock Input

TDI

: Test Data Input

TDO

: Test Data Output

TICE

: Test In-Circuit Emulator

TMS

: Test Mode Select

TRST

: Test Reset

WAKEUP

: Wakeup from STOP Mode

X/Y

: X/Y Memory Select

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

CONTENTS

1. PIN FUNCTION .................................................................................................................................

1.1 Pin Function Description ..........................................................................................................

1.2 Connection of Unused Pins .....................................................................................................

2. FUNCTION OUTLINE .......................................................................................................................

2.1 Program Control Unit ................................................................................................................

2.2 Arithmetic Unit...........................................................................................................................

2.3 Data Memory Unit ......................................................................................................................

2.4 Peripheral Units .........................................................................................................................

3. CLOCK GENERATOR ......................................................................................................................

4. RESET FUNCTION ...........................................................................................................................

4.1 Hardware Reset .........................................................................................................................

4.2 Initializing PLL ...........................................................................................................................

5. FUNCTIONS OF BOOT-UP ROM...................................................................................................

5.1 Boot at Reset .............................................................................................................................

5.2 Reboot ........................................................................................................................................

5.3 Signature Operation ..................................................................................................................

5.4 Instruction ROM Modification ..................................................................................................

6. STANDBY MODES ...........................................................................................................................

6.1 HALT Mode.................................................................................................................................

6.2 STOP Mode ................................................................................................................................

7. MEMORY MAP..................................................................................................................................

7.1 Instruction Memory ...................................................................................................................

7.2 Data Memory ..............................................................................................................................

8. MASK OPTION .................................................................................................................................

8.1 Clock Control Options ..............................................................................................................

8.2 WAKEUP Function ....................................................................................................................

9. INSTRUCTIONS.................................................................................................................................

9.1 Outline of Instructions ..............................................................................................................

9.2 Instruction Set and Operation..................................................................................................

10. ELECTRICAL SPECIFICATIONS.....................................................................................................

11. PACKAGE DRAWINGS....................................................................................................................

12. RECOMMENDED SOLDERING CONDITIONS...............................................................................

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

1. PIN FUNCTION

Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.

1.1 Pin Function Description

· Power supply

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

35, 77, 85

B5, B7, G5

Power to DSP core (+2.5 V)

25, 50, 64, 75,

100

A3, C9, D1, D9,

G1, J7

Power to I/O pins (+3 V)

GND

1, 26, 36, 51,

65, 76, 78, 86

A5, A7, C1, D6,

E2, E7, F4, G2,

Ground

Remark Please supply voltage to the IV

and EV

pins simultaneously.

· System control

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

CLKIN

Input

System clock input

CLKOUT

Output

Internal system clock output

RESET

Input

Internal system reset signal input

WAKEUP

Input

Stop mode release signal input.

When this pin is asserted active, the stop

mode is released. The function of this pin

can be activated or deactivated by a mask

option.

INT4

· Interrupt

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

INT1 - INT3

91 - 89

B3, D3, A4

Input

INT4

Input

External maskable interrupt input.

Detected at the falling edge.

WAKEUP

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

· External data memory interface (

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PD77114 only)

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

X/Y

Output

(3S)

Memory select signal output.

0: Uses X memory.

1: Uses Y memory.

DA0 - DA12

16 - 4

Output

(3S)

Address bus of external data memory.

Accesses the external memory.

Continuously outputs the external memory

address accessed last when the external

memory is not being accessed. Kept low

(0x000) if the external memory is never

accessed after reset.

D0 - D15

34 - 27, 24 - 17

I/O

(3S)

16-bit data bus.

Accesses the external memory.

MRD

Output

(3S)

Read output

External memory read

MWR

Output

(3S)

Write output

External memory write

HOLDRQ

Input

Hold request signal

Input a low level to this pin when the external

device uses the external data memory bus of

the

PD77114.

BSTB

Output

Bus strobe signal

This pin goes low when the

PD77114 uses

the external data memory bus.

HOLDAK

Output

Hold acknowledge signal

This pin goes low when the external device

is enabled to use the external data memory

bus of the

PD77114.

Remark Pins marked "3S" under the heading "I/O" go into a high-impedance state in the following conditions:

X/Y, DA0-DA12, MRD, MWR: When the bus is released (HOLDAK = low level)

D0-D15: When the external data memory is not being accessed and when the bus is released

(HOLDAK = low level)

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

· Host interface

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

HA1

Input

Specifies the register to be accessed by HD7

through HD0.

1: Accesses the host interface status

0: Accesses the host transmit data register

(HDT (out)) when read (HRD = 0), and

host receive data register (HDT (in))

when written (HWR = 0).

HA0

Input

Specifies the register to be accessed by HD7

through HD0.

1: Accesses bits 15 through 8 of HST, HDT

(in), and HDT (out).

0: Accesses bits 7 through 0 of HST, HDT

(in), and HDT (out).

HCS

Input

Chip select input

HRD

Input

Host read input

HWR

Input

Host write input

HRE

Output

Host read enable output

HWE

Output

Host write enable output

HD0 - HD7

63 - 56

F5, E8, E9, F7,

G6, F9, F8, H8

I/O

(3S)

8-bit host data bus

Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state when the host interface is

not being accessed.

· I/O ports

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

I/O

General-purpose I/O port

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

· Debugging interface

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

TDO

Output

TICE

Output

TCK

Input

TDI

Input

TMS

Input

TRST

Input

For debugging

· Others

Pin No.

Pin Name

100-pin TQFP

80-pin BGA

I/O

Function

Shared by:

I.C.

Internally connected. Leave this pin

unconnected.

A2, B1, B2, C2,

C3, D2, D4, E1,

E4, F1, F2, H1,

H2, H9, J2, J8

No function pins. Connect to EV

via pull-up

resistor, or connect to GND via pull-down

resistor.

2, 3, 49, 95

No-connect pins. Leave these pins

unconnected.

A1, A9, J1, J9

Pins to strengthen soldering. Connect these

pins to the board as necessary.

Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal

operation of the

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PD77113A and 77114 is not guaranteed.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

1.2 Connection of Unused Pins

1.2.1 Connection of Function Pins

When mounting, connect unused pins as follows:

I/O

Recommended Connection

INT1 - INT4

Input

Connect to EV

X/Y

Output

DA0 - DA12

Output

Leave unconnected.

D0 - D15

Note 1

I/O

Connect to EV

via pull-up resistor, or connect to GND via pull-down resistor.

MRD, MWR

Output

Leave unconnected.

HOLDRQ

Input

Leave unconnected. (internally pulled up).

BSTB, HOLDAK

Output

Leave unconnected.

SCK1, SCK2

Input

SI1, SI2

Input

Connect to EV

or GND.

SIEN1, SIEN2

Input

SOEN1, SOEN2

Input

Connect to GND.

SORQ1

Output

SO1, SO2

Output

SIAK1

Output

Leave unconnected.

HA0, HA1

Input

Connect to EV

or GND.

HCS, HRD, HWR

Input

Connect to EV

HRE, HWE

Output

Leave unconnected.

HD0 - HD7

Note 2

I/O

P0 - P3

I/O

Connect to EV

via pull-up resistor, or connect to GND via pull-down resistor.

TCK

Input

Connect to GND via pull-down resistor.

TDO, TICE

Output

Leave unconnected.

TMS, TDI

Input

Leave unconnected. (internally pulled up).

TRST

Input

Leave unconnected. (internally pulled down).

CLKOUT

Output

Leave unconnected.

Notes 1. These pins may be left unconnected if the external data memory is not accessed in the program.

However, connect these pins as recommended in the halt and stop modes when the power

consumption must be lowered.

2. These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level.

However, connect these pins as recommended in the halt and stop modes when the power

consumption must be lowered.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

2. FUNCTION OUTLINE

2.1 Program Control Unit

This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode

of the DSP.

2.1.1 CPU control

A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as

branch instructions, are executed in one system clock.

2.1.2 Interrupt control

Interrupt requests input from external pins (INT1 through INT4) or generated by the internal peripherals (serial

interface and host interface) are serviced. The interrupt of each interrupt source can be enabled or disabled.

Multiple interrupts are also supported.

2.1.3 Loop control task

A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support

multiple loops.

2.1.4 PC stack

A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls.

2.1.5 PLL

A PLL is provided as a clock generator that can multiply or divide an external clock input to supply an operating

clock to the DSP. A multiple of

1 to

16 or a division ratio of 1/1 to 1/16 can be set by a mask option.

Two standby modes are available for lowering the power consumption while the DSP is not in use.

HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The

normal operation mode is recovered by an interrupt or hardware reset.

STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10

A. The

normal operation mode is recovered by hardware reset or WAKEUP pin

Note

Note If the WAKEUP function is activated by mask option

2.1.6 Instruction memory

The capacity and type of the memory differ depending on the model of the DSP.

64 words of the instruction RAM are allocated to interrupt vectors.

A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or

rewritten by self boot (boot from the internal data ROM or external data space) or host boot (boot via host interface).

The

PD77113A and 77114 have 3.5K-word instruction RAM and 48K-word instruction ROM.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

2.2 Arithmetic Unit

This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply

accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers.

2.2.1 General-purpose registers (R0 through R7)

These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to

data memory.

A general-purpose register (R0 to R7) is made up of three parts: R0L through R7L (bits 15 through 0), R0H

through R7H (bits 31 through 16), and R0E through R7E (bits 39 through 32). Depending on the type of operation,

RnL, RnH, and RnE are used as one register or in different combinations.

2.2.2 Multiply accumulator (MAC)

The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and

outputs a 40-bit value.

The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can

arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right .

2.2.3 Arithmetic logic unit (ALU)

This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value.

2.2.4 Barrel shifter (BSFT: Barrel ShiFTer)

The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value.

The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or

logically shifted to the right, in which case 0 is inserted from the MSB.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

2.3 Data Memory Unit

The data memory unit consists of two banks of data memory and two data addressing units.

2.3.1 Data memory

The capacity and type of the memory differ depending on the model of the DSP. All DSPs have two banks of data

memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space.

The

PD77113A and 77114 have 16K words

2 banks data RAM and 32K words

2 banks data ROM.

In addition, the

PD77114 has an external data memory interface so that the external memory can be expanded

to 8K words

2 banks.

2.3.2 Data addressing unit

An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.

Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or

DMY), and an address ALU.

2.4 Peripheral Units

A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal

peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as

memory-mapped I/Os.

2.4.1 Serial interface (SIO)

Two serial interfaces are provided. These serial interfaces have the following features:

Serial clock : Supplied from external source to each interface. The same clock is used for input and output

on the interface.

Frame length: 8 or 16 bits, and MSB or LSB first selectable for each interface and input or output

Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the

internal units, polling, wait, or interrupt are used.

2.4.2 Host interface (HIO)

This is an 8-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In

the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external

device is implemented by using a dedicated status signal. Handshaking with internal units is achieved by means of

polling, wait, or interrupts.

2.4.3 General-purpose I/O port (PIO)

This is a 4-bit I/O port that can be set in the input or output mode in 1-bit units.

2.4.4 Wait cycle register

The number of wait cycles to be inserted when the external data memory area is accessed can be specified in

advance by using a register (DWTR)

Note

. The number of wait cycles that can be set is 1, 3, or 7.

Note This function is not available on the

PD77113A because this DSP does not have an external data area.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

3. CLOCK GENERATOR

The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and

supplies the generated clock to the internal units of the DSP.

For details of how to set the PLL multiple, refer to 4.2 Initializing PLL, and 8.1 Clock Control Options.

Stop mode

PLL control circuit

Output divider

Halt divider

Halt mode

Internal
system clock

CLKOUT

CLKIN

4. RESET FUNCTION

When a low level of a specified width is input to the RESET pin, the device is initialized.

4.1 Hardware Reset

If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized.

If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed

according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the

instruction at address 0x200 of instruction memory (reset entry). In addition, a self-check is performed by the internal

data RAM at the same time as the boot processing. This check takes about 20 ms (at 50 MHz operation, the length

of this period is in inverse proportion to the operating frequency.)

On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with

the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating

voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

4.2 Initializing PLL

Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level).

Initialization takes 1024 clocks and it takes the PLL 100

s to be locked.

After that, the DSP operates with the set value of the PLL specified by a mask option when the RESET pin is

deasserted inactive (high level).

After initializing the PLL, be sure to execute boot-up processing to re-initialize the internal RAM. To initialize the

PLL, the internal memory contents and register status of the DSP are not retained.

If the RESET pin is deasserted inactive before the PLL initialization mode is set, the DSP is normally reset (the

PLL is not initialized).

CLKIN

RESET

PLL initialization
mode

1024

2048

PLL lock time

Approx. 100 s

PLL initialization
(internal status)

Caution Do not deassert the RESET signal inactive in the PLL initialization mode and during PLL lock

period.

5. FUNCTIONS OF BOOT-UP ROM

To rewrite the contents of the instruction memory on power application or from program, boot up the instruction

RAM by using the internal boot-up ROM.

The

PD77113A and 77114 have a function to verify the contents of the internal instruction RAM and a function to

modify the instruction ROM in the boot-up ROM.

5.1 Boot at Reset

After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,

depending on their bit pattern, determines the boot mode (self boot or host boot). After boot processing, processing

is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.

The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for

the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).

If host boot or self boot is specified, a self-check of the internal data RAM is performed at the same time as boot

processing.

Boot Mode

Does not execute boot but branches to address 0x200

Note

Executes host boot and then branches to address 0x200.

Executes self boot and then branches to address 0x200.

Setting prohibited

Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has

been executed once.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

5.1.1 Self boot

The boot-up ROM transfers the instruction code stored in the data memory space to the instruction RAM, based

on the boot parameter written to address 0x4000 of the Y data memory. Generally, with a mask ROM model, this

function is implemented by storing the instructions to be booted in the data ROM.

In addition, the instructions to be booted can be also stored in an external data area in the form of flash ROM, and

self boot can be executed from this external data area.

5.1.2 Host boot

In this boot mode, a boot parameter and instruction code are obtained via the host interface, and transferred to the

instruction RAM.

5.2 Reboot

By calling the next reboot entry from the program, the contents of the instruction RAM can be rewritten.

Reboot Mode

Entry Address

Word reboot

0x2

X memory

Byte reboot

0x4

Word reboot

0x1

Self boot

Y memory

Byte reboot

0x3

Host boot

Host reboot

0x5

5.2.1 Self reboot

The instruction codes stored in the data memory are transferred to the instruction RAM.

Set the following parameters and call the entry address of the corresponding reboot mode to execute self reboot.

R7L : Number of instruction steps for rebooting

DP3: First address of X memory in which instruction codes are stored (in the case of reboot from X memory),

or first address of the instruction memory to be loaded (in the case of reboot from Y memory)

DP7: First address of instruction memory to be loaded (in the case of reboot from X memory), or first address

of X memory in which instruction codes are stored (in the case of reboot from Y memory)

5.2.2 Host reboot

An instruction code is obtained via the host interface and transferred to the instruction RAM.

The entry address of is 0x5. Host reboot is executed by calling this address after setting the following parameter:

R7L : Number of instruction steps for rebooting

DP3: First address of instruction memory to be loaded

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

5.3 Signature Operation

The

PD77113A and 77114 have a signature operation function so that the contents of the internal instruction

RAM can be verified. The signature operation performs a specific arithmetic operation on the data in the instruction

RAM booted up, and returns the result to a register. Perform the signature operation in advance on the device when

it is operating normally, and repeat the signature operation later to check whether the data in RAM is correct by

comparing the operation result with the previous result. If the results are identical, there is no problem.

The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The

operation result is stored in register R7.

R7L: Number of instruction steps for operation

DP3: First address of instruction memory for operation

5.4 Instruction ROM Modification

The

PD77113A and 77114 have a function to modify the contents of the internal instruction mask ROM.

Instructions at up to four addresses can be modified.

The entry address is 0x10D. By calling this address with the following parameters, modification is performed.

R7L

: Address of instruction ROM to be modified

R6H, R6L : Instruction code (32 bits)

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

6. STANDBY MODES

Two standby modes are available. By executing the corresponding instruction, each mode is set and the power

consumption can be reduced.

6.1 HALT Mode

To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are

stopped to reduce the current consumption.

To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an

interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release

the HALT mode when the HALT mode is released using an interrupt.

In the HALT Mode, the clock circuit of the

PD77111 family supplies the following clock as the internal system

clock. The clock output from the CLKOUT pin is also as follows.

The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal

operation (i.e., the duty factor is not 50%).

PD77113A, 77114: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option)

6.2 STOP Mode

To set this mode, execute the STOP instruction. In this mode, all the functions, including the clock circuit and

PLL, are stopped and the power consumption is minimized with only leakage current flowing.

To release the STOP mode, use hardware reset or WAKEUP pin.

When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are

retained, but it takes several 100

s to release the mode.

The WAKEUP pin is multiplexed with the INT4 pin. Usually, this pin functions as an interrupt pin, but functions as

the WAKEUP pin when it is asserted active in the STOP mode. Whether the WAKEUP pin is used to release the

STOP mode is selected by mask option. For details, refer to 8.2 WAKEUP Function.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

7. MEMORY MAP

A Harvard architecture, in which the instruction memory space and data memory space are separated is

employed.

7.1 Instruction Memory

7.1.1 Instruction memory map

The instruction memory space consists of 64K words

32 bits, and the capacity and type of the memory differ

depending on the product.

PD77113A, 77114

0 x F F F F

0
0

x
x

4
3

0
F

Internal instruction
ROM
(48K words)

System

Boot-up ROM

(256 words)

Vector area (64 words)

Internal instruction RAM

(3.5K words)

0
F

0
0

x
x

1
0

0
F

0
0

x
x

0
0

2
2

4
3

0
F

0
0

x
x

0
0

2
1

0
F

0
0

x
x

0
0

1
0

0
F

0 x 0 0 0 0

Caution Programs and data cannot be placed at addresses reserved for the system, nor can these

addresses be accessed. If these addresses are accessed, the normal operation of the device

cannot be guaranteed.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

7.1.2 Interrupt vector table

Addresses 0x200 through 0x23F of the instruction memory are entry points (vectors) of interrupts. Four

instruction addresses are assigned to each interrupt source.

Vector

Interrupt Source

0x200

Reset

0x204

0x208

0x20C

Reserved

0x210

INT1

0x214

INT2

0x218

INT3

0x21C

INT4

0x220

SI1 input

0x224

SO1 output

0x228

SI2 input

0x22C

SO2 output

0x230

HI input

0x234

HO output

0x238

0x23C

Reserved

Cautions

1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector.

2. It is recommended that unused interrupt source vectors be used to branch an error

processing routine.

3. Because a vector area also exists in the internal RAM area of the mask ROM model, this

area must be booted up. In addition, because the entry address after reset is 0x200,

address 0x200 must be booted up even when the internal instruction RAM and interrupts are

not used.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

7.2 Data Memory

7.2.1 Data memory map

The data memory space consists of an X memory space and a Y memory space of 64K words

16 bits each, and

the memory capacity and memory type differ depending on the product.

PD77113A

0 x F F F F

0
0

x
x

E
D

0
F

System

Data RAM

(8K words)

Peripheral

(64 words)

Data ROM

(32K words)

Data RAM

(4K words)

Data RAM

(4K words)

0
F

0
0

x
x

C
B

0
F

0
0

x
x

4
3

0
F

0
0

x
x

3
3

8
8

4
3

0
F

0
0

x
x

1
0

0
F

0
0

x
x

2
1

0
F

0
0

x
x

3
2

0
F

0
0

x
x

3
3

8
7

0
F

0 x 0 0 0 0

PD77114

System

Data RAM

(8K words)

Peripheral

(64 words)

Data ROM

(32K words)

Data RAM

(4K words)

Data RAM

(4K words)

External data
memory
(8K words)

Caution Programs and data cannot be placed at addresses reserved for the system, nor can these

addresses be accessed. If these addresses are accessed, the normal operation of the device

cannot be guaranteed.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

7.2.2 Internal peripherals

The internal peripherals are mapped to the internal data memory space.

X/Y Memory Address

Function

Peripheral Name

0x3800

SDT1

First serial data register

0x3801

SST1

First serial status register

0x3802

SDT2

Second serial data register

0x3803

SST2

Second serial status register

SIO

0x3804

PDT

Port data register

0x3805

PCD

Port command register

PIO

0x3806

HDT

Host data register

0x3807

HST

Host status register

HIO

0x3808

DWTR

Data memory wait cycle register

WTR

0x3809 - 0x383F

Reserved area

Caution Do not access this area.

Cautions

1. The register names listed in this table are not reserved words of the assembler or the C

language. Therefore, when using these names in assembler or C, the user must define

them.

2. The same register is accessed, as long as the address is the same, regardless of whether

the X memory space or Y memory space is accessed.

3. Even different registers cannot be accessed at the same time from both the X and Y memory

spaces.

8. MASK OPTION

The

PD77113A and 77114 have mask options that must be specified when an order for a ROM is placed. This

section explains these mask options. The mask options are specified in the Workbench (WB77016) development

tool. To order a mask ROM, output a mask ROM ordering file format (.msk file) using WB77016.

8.1 Clock Control Options

The following four clock related options must be specified.

PLL multiple

Output division ratio

HALT division ratio

Validity of CLKOUT pin

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each

operation mode and operating clock is as follows:

Operation Mode

Clock Supplied Inside DSP

Normal operation mode

m/n times external input clock

HALT mode

m/n/l times external input clock

STOP mode

Stopped

The PLL control circuit multiplies the input clock by an integer from 1 to 16. Specify the mask option of the PLL

multiple so that the multiplied frequency falls within the specified PLL lock frequency range.

The output divider divides the clock multiplied by the PLL by an integer from 1 to 16. Specify the mask option of

the output division ratio so that the frequency m/n times the external input clock supplied to the DSP falls within the

specified operating frequency range of the DSP.

The HALT divider functions only in the HALT mode. It divides the clock of the output divider by an integer from 1

to 16 and supplies the divided clock to the internal circuitry. Specify the mask option of the HALT division ratio so

that necessary division can be performed.

Whether the clock supplied to the internal circuitry of the DSP (internal system clock) is "output" or "not output"

from the CLKOUT pin can be specified. Specify the mask option as necessary.

If an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from

the CLKOUT pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%).

8.2 WAKEUP Function

The WAKEUP pin can be used to release the STOP mode as well as a hardware reset.

If the STOP mode is released by means of a hardware reset, the status before the STOP mode was set cannot be

restored after the STOP mode has been released. If the WAKEUP pin is used, however, the status before the STOP

mode is set can be retained and program execution can be resumed starting from the instruction after the STOP

instruction.

Whether the WAKEUP pin is used to release the STOP mode can be specified by a mask option.

When the WAKEUP function is specified valid, the WAKEUP pin is multiplexed with the INT4 pin and it usually

functions as an interrupt pin. The pin functions as the WAKEUP pin only in the STOP mode (if this pin is asserted

active in the STOP mode, it is used only to release the STOP mode, and execution does not branch to an interrupt

vector).

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

9. INSTRUCTIONS

9.1 Outline of Instructions

An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are

executed with one system clock. The maximum instruction cycle of the

PD77113A and 77114 is 13.3 ns. The

following nine types of instructions are available:

(1) Trinomial operation instructions

These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be

specified.

(2) Binomial operation instructions

These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose

registers can be specified. An immediate value can be specified for some of these instructions, instead of a

general-purpose register, for one input.

(3) Uninominal operation instructions

These instructions specify an operation by the ALU. As the operands, one general-purpose register can be

specified.

(4) Load/store instructions

These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose

(5) Register-to-register transfer instructions

These instructions transfer data from one general-purpose register to another.

(6) Immediate value setting instructions

These instructions write an immediate value to a general-purpose register and the registers of the address

operation unit.

(7) Branch instructions

These instruction specify branching of program execution.

(8) Hardware loop instructions

These instruction specify repetitive execution of an instruction.

(9) Control instructions

These instructions are used to control the program.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

9.2 Instruction Set and Operation

An operation is written in the operation field for each instruction in accordance with the operation representation

format of that instruction. If two or more parameters can be written, select one of them.

(a) Representation formats and selectable registers

The following table shows the representation formats and selectable registers.

Representation Format

Selectable Register

r0, r0

, r0

R0 - R7

rI, rI

R0L - R7L

rh, rh

R0H - R7H

R0E - R7E

reh

R0EH - R7EH

DP0 - DP7

DN0 - DN7

DMX, DMY

dpx

DP0 - DP3

dpy

DP4 - DP7

dpx_mod

DPn, DPn++, DPn

, DPn##, DPn%%, !DPn## (n = 0 - 3)

dpy_mod

DPn, DPn++, DPn

, DPn##, DPn%%, !DPn## (n = 4 - 7)

dp_imm

DPn##imm (n = 0 - 7)

*xxx

Contents of memory with address xxx

<Example> If the contents of the DP0 register are 1000, *DP0 indicates the contents of

address 1000 of the memory.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

(b) Modifying data pointer

The data pointer is modified after the memory has been accessed. The result of modification becomes valid

starting from the instruction that immediately follows. The data pointer cannot be modified.

Example

Operation

DPn

Nothing is done (value of DPn is not changed.)

DPn++

DPn

DPn + 1

DPn

DPn##

DPn

DPn + DNn

(Adds value of corresponding DN0 to DN7 to DP0 to DP7.)

Example: DP0

DP0 + DN0

(n = 0 - 3) DPn = ((DP

+ DNn) mod (DMX + 1)) + DP

DPn%%

(n = 4 - 7) DPn = ((DP

+ DNn) mod (DMY + 1)) + DP

!DPn##

Reverses bits of DPn and then accesses memory.

After memory access, DPn

DPn + DNn

DPn##imm

DPn

DPn + imm

(c) Instructions that can be simultaneously written

Instructions that can be simultaneously written are indicated by

(d) Status of overflow flag (OV)

The status of the overflow flag is indicated by the following symbol:

: Not affected

: Set to 1 when overflow occurs

Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but

retains the status before the operation.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

Instruction Set

Instructions Simultaneously Written

Flag

Instruc-

tion

Instruction

Name

Mnemonic

Operation

Trino-

mial

Bino-

mial

Unino-

minal

Load/

store

Trans-

fer

Imme-

diate-

value

Bran-

Loop

Cont-

rol

Multiply add

ro = ro + rh * rh

ro + rh * rh

Multiply sub

ro = ro

rh * rh

Sign unsign

multiply add

ro = ro + rh * rl

(rl is in positive integer

format.)

ro + rh * rl

Unsign unsign

multiply add

ro = ro + rl * rl

(rl and rl' are in positive

integer format.)

ro + rl * rl

1-bit shift

multiply add

ro = (ro>>1) + rh * rh

+ rh * rh

Trinomial

operation

16-bit shift

multiply add

ro = (ro>>16) + rh * rh

+ rh * rh

Multiply

ro = rh * rh

rh * rh

Add

= ro + ro

ro + ro

Immediate add

= ro + imm

ro + imm

(where imm

Sub

= ro

Immediate sub

= ro

imm

(where imm

Arithmetic right

shift

= ro SRA rl

ro >> rl

Immediate

arithmetic right

shift

= ro SRA imm

ro >> imm

Logical right

shift

= ro SRL rl

ro >> rl

Immediate

logical right

shift

= ro SRL imm

ro >> imm

Logical left shift ro

= ro SLL rl

ro << rl

Immediate

logical left shift

= ro SLL imm

ro << imm

AND

= ro & ro

ro & ro

Immediate

AND

= ro & imm

ro & imm

= ro

Immediate OR

= ro

imm

Exclusive OR

= ro

Binomial

operation

Immediate

exclusive OR

= ro

imm

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

Instructions Simultaneously Written

Flag

Instruc-

tion

Instruction

Name

Mnemonic

Operation

Trino-

mial

Bino-

mial

Unino-

minal

Load/

store

Trans-

fer

Imme-

diate-

value

Bran-

Loop

Cont-

rol

Binomial

operation

Less than

= LT (ro, ro

)

if (ro < ro

)

{ro

0x0000000001}

else {ro

0x0000000000}

Clear

CLR (ro)

0x0000000000

Increment

= ro + 1

ro + 1

Decrement

= ro

Absolute value

= ABS (ro)

if (ro < 0)

{ro

ro}

else {ro

ro}

1's

complement

= ~ro

~ro

2's

complement

Clip

= CLIP (ro)

if ( ro > 0x007FFFFFFF)

{ro

0x007FFFFFFF}

elseif {ro < 0xFF80000000}

{ro

0xFF80000000}

else {ro

ro}

Round

= ROUND (ro)

if (ro > 0x007FFF0000)

{ro

0x007FFF0000}

elseif {ro < 0xFF80000000}

{ro

0xFF80000000}

else {ro

(ro + 0x8000)

& 0xFFFFFF0000}

Exponent

= EXP (ro)

log

(

)

Substitution

= ro

Accumulated

addition

+ = ro

+ ro

Accumulated

subtraction

= ro

Uninom-

inal

operation

Division

/ = ro

if (sign (ro

) == sign (ro))

{ro

(ro

ro) << 1}

else

{ro

(ro

+ ro)<<1}

if (sign (ro

)==0)

{ro

+ 1}

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

Instructions Simultaneously Written

Flag

Instruc-

tion

Instruction

Name

Mnemonic

Operation

Trino-

mial

Bino-

mial

Unino-

minal

Load/

store

Trans-

fer

Imme-

diate-

value

Bran-

Loop

Cont-

rol

ro = *dpx_mod ro

*dpy_mod

*dpx, ro

*dpy

ro = *dpx_mod

*dpy_mod = rh

*dpx, *dpy

*dpx_mod = rh ro =

*dpy_mod

*dpx

rh, ro

*dpy

Parallel

load/store

Notes 1, 2

*dpx_mod = rh

*dpy_mod = rh

*dpx

rh, *dpy

dest = *dpx_mod

dest

= *dpy_mod

dest

*dpx,

dest

*dpy

dest = *dpx_mod

*dpy_mod = source

dest

*dpx,

*dpy

source

*dpx_mod = source

dest = *dpy_mod

*dpx

source,

dest

*dpy

Partial load/

store

Notes 1, 2, 3

*dpx_mod = source

*dpy_mod = source

*dpx

source,

*dpy

source

dest = *addr

dest

*addr

Direct

addressing

load/store

Note 4

*addr = source

*addr

source

dest = *dp_imm

dest

*dp

Load/

store

Immediate

value index

load/store

Note 5

*dp_imm = source

*dp

source

dest = rl

dest

to-register

transfer

Note 6

rl = source

source

rl = imm

(where imm = 0 to 0xFFFF)

imm

dp = imm

(where imm = 0 to 0xFFFF)

imm

dn = imm

(where imm = 0 to 0xFFFF)

imm

Immediate

value

setting

Immediate

value setting

dm = imm

(where imm = 1 to 0xFFFF)

imm

Notes 1. Of the two mnemonics, either one of them or both can be written.

2. After transfer, modification specified by mod is performed.

3. Select any of dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}.

4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl},

0: X-0xFFF

0: Y-0xFFFF

: X (X memory)

: Y (Y memory)

addr =

5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.

6. Select any register other than general-purpose registers as dest and source.

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

Instructions Simultaneously Written

Flag

Instruc-

tion

Instruction

Name

Mnemonic

Operation

Trino-

mial

Bino-

mial

Unino-

minal

Load/

store

Trans-

fer

Imme-

diate-

value

Bran-

Loop

Cont-

rol

Jump

JMP imm

imm

indirect jump

JMP dp

Subroutine call

CALL imm

SP + 1

STK

PC + 1

imm

indirect

subroutine call

CALL dp

SP + 1

STK

PC + 1

Return

RET

STK

Branch

Interrupt return

RETI

STK

Recovery of interrupt

enable flag

Repeat

REP count

Start

count

During repeat

End

PC + 1

Loop

LOOP count

(instruction of two or

more lines)

Start

count

During repeat

End

PC + 1

Hard-

ware

loop

Loop hop

LPOP

LSR3

LSR2

LSR1

LSP

No operation

NOP

PC + 1

Halt

HALT

CPU stops.

Stop

STOP

CPU, PLL, and

OSC stop.

Condition

IF (ro cond)

Condition test

Control

Forget interrupt

FINT

Discard interrupt

request

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= +25

°
°
°
°

Parameter

Symbol

Condition

Rating

Unit

For DSP core

0.5 to +3.6

Supply voltage

For I/O pins

0.5 to +4.6

Input voltage

0.5 to +4.1

Output voltage

< EV

+ 0.5 V

0.5 to +4.1

Storage temperature

stg

65 to +150

Operating temperature

40 to +85

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on

the verge of suffering physical damage, and therefore the product must be used unber

conditions that ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Conditions

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

For DSP core

1.8

2.7

= 1.8 to 2.7 V

3.3

Operating voltage

For I/O

pins

= 2.3 to 2.7 V

2.7

3.6

Input voltage

Capacitance (T

= +25

°
°
°
°

C, IV

= 0 V, EV

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input capacitance

Output capacitance

I/O capacitance

f = 1 MHz,

Pins other than those

tested: 0 V

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

DC Characteristics (Unless otherwise specified, T

-
-
-
-

40 to +85

°
°
°
°

C, with IV

and EV

within recommended

operating condition range)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

IHN

Pins other than below

0.7 EV

IHS

CLKIN, RESET,

INT1 - INT4, SCK1, SIEN1,

SOEN1, SCK2, SIEN2, SOEN2

0.8 EV

High-level input voltage

IHC

CLKIN

0.5 EV

+0.25

Pins other than below

0.2 EV

Low-level input voltage

CLKIN

0.5 EV

0.25

2.0 mA

0.7 EV

High-level output voltage

100

0.8 EV

Low-level output voltage

= 2.0 mA

0.2 EV

High-level input leakage

current

Other than TDI, TMS, and TRST

= EV

Low-level input leakage

current

Other than TDI, TMS, and TRST

= 0 V

Pull-up pin current

PUI

TDI, TMS, 0 V

250

Pull-down pin current

PDI

TRST, 0 V

250

Note

During operating, 30 ns, IV

2.7 V

TBD

DDH

In halt mode, t

= 30 ns,

divided by eight, IV

= 2.7 V

TBD

Internal supply current

IHN

= V

IHS

= EV

, V

= 0 V,

no load]

DDS

In stop mode, 0

C < T

< 60

100

Note The TYP. values are when an ordinary program is executed.

The MAX. values are when a special program that brings about frequent switching inside the device is

executed.

Data Sheet U14373EJ3V0DS

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µ
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PD77113A, 77114

PD77113A, 77114

AC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, with IV

and EV

within recommended operating condition range)

Clock

Timing requirements

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

= 1.8

to 2.7 V

CLKIN cycle time

Note 1

cCX

PLL lock

range

Note 2

= 2.3

to 2.7 V

CLKIN high-level width

wCXH

12.5

CLKIN low-level width

wCXL

12.5

CLKIN rise/fall time

rfCX

= 1.8 to 2.7 V

Internal clock cycle time

requirements

Note 3

cC (R)

= 2.3 to 2.7 V

13.3

Notes 1. m: Multiple, n: Division ratio

2. This is the range in which the PLL is locked (stably oscillates). Input t

cCX

within this range.

3. Input t

cCX

so that the value of (t

cCX

n) satisfies this condition.

Switching characteristics

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

During normal operation

cCX

Internal clock cycle

Note

In HALT mode

cCX

CLKOUT cycle time

cCO

n = 1, or even number

During

normal

operation

n = odd number

(other than 1)

CLKOUT width

wCO

In HALT mode

CLKOUT rise/fall time

rfCO

= 1.8 to 2.7 V

CLKOUT delay time

dCO

= 2.3 to 2.7 V

Note m: Multiple, n: Division ratio, l: HALT division ratio

Data Sheet U14373EJ3V0DS

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µ
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PD77113A, 77114

PD77113A, 77114

Reset, Interrupt

Timing requirements

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

On power application

Note 1

in STOP mode

100 +

2048t

cCX

RESET low-level width

w (RL)

During normal operation,

in HALT mode

Note 2

Note 3

On power application

Note 4

cCX

RESET recovery time

rec (R)

Note 2

WAKEUP low-level width

w (WAKEUPL)

100

INT1 - INT4 low-level width

w (INTL)

Note 2

INT1 - INT4 recovery time

rec (INT)

Notes 1. The value on power application is the time from when the supply voltages have reached IV

= 1.8 V

and EV

= 2.7 V. A stable clock input is also required.

2. Note that t

is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.

3. If the low-level width of RESET is greater than 1024t

, the PLL initialization mode is triggered. If there

is no need to use the PLL initialization mode, set the width to less than 1024t

4. When the power is turned on, a recovery period of 4t

cCX

is necessary before inputting RESET.

Reset timing

RESET

w(RL)

rec(R)

WAKEUP timing

WAKEUP

w (WAKEUPL)

Interrupt timing

INT1 - INT4

w(INTL)

rec(INT)

Data Sheet U14373EJ3V0DS

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PD77113A, 77114

PD77113A, 77114

Serial Interface

Timing requirements

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

SCK cycle time

cSC

SCK high-/low-level width

wSC

SCK rise/fall time

rfSC

= 1.8 to 2.7 V

SOEN setup time

suSOE

= 2.3 to 2.7 V

= 1.8 to 2.7 V

SOEN hold time

hSOE

= 2.3 to 2.7 V

= 1.8 to 2.7 V

SIEN setup time

suSIE

= 2.3 to 2.7 V

= 1.8 to 2.7 V

SIEN hold time

hSIE

= 2.3 to 2.7 V

= 1.8 to 2.7 V

SI setup time

suSI

= 2.3 to 2.7 V

= 1.8 to 2.7 V

SI hold time

hSI

= 2.3 to 2.7 V

Switching characteristics

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

= 1.8 to 2.7 V

SORQ output delay time

dSOR

= 2.3 to 2.7 V

SORQ hold time

hSOR

= 1.8 to 2.7 V

SO output delay time

dSO

= 2.3 to 2.7 V

SO hold time

hSO

= 1.8 to 2.7 V

SIAK output delay time

dSIA

= 2.3 to 2.7 V

SIAK hold time

hSIA

Data Sheet U14373EJ3V0DS

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µ
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PD77113A, 77114

PD77113A, 77114

Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in

mind the following points when designing your system:

Reinforce the wiring for power supply and ground (if noise is superimposed on the power and

ground lines, it has the same effect as if noise were superimposed on the serial clock).

Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source.

Do not cross the signal lines of the serial clock with any other signal lines. Do not route the

serial clock line in the vicinity of a line through which a high alternating current flows.

Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-to-

one basis. Do not supply clock to several devices from one clock source.

Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure

that the rising and falling of the serial clock waveform are clear.

Make sure that the serial clock
rises and falls linearly.

The serial clock must not bound. Noise
must not be superimposed on the serial clock.

The serial clock must not rise or
fall step-wise.

Data Sheet U14373EJ3V0DS

µ
µ
µ
µ

PD77113A, 77114

PD77113A, 77114

Host Interface

Timing requirements

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

= 1.8 to 2.7 V

HRD delay time

dHR

= 2.3 to 2.7 V

HRD width

wHR

HCS, HA0, HA1, read hold

time

hHCAR

HCS, HA0, HA1 write hold time

hHCAW

HRD, HWR recovery time

recHS

= 1.8 to 2.7 V

HWR delay time

dHW

= 2.3 to 2.7 V

HWR width

wHW

HWR hold time

hHDW

= 1.8 to 2.7 V

HWR setup time

suHDW

= 2.3 to 2.7 V

Switching characteristics

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

= 1.8 to 2.7 V

HRE, HWE output delay time

dHE

= 2.3 to 2.7 V

= 1.8 to 2.7 V

HRE, HWE hold time

hHE

= 2.3 to 2.7 V

= 1.8 to 2.7 V

HRD valid time

vHDR

= 2.3 to 2.7 V

HRD hold time

hHDR

Data Sheet U14373EJ3V0DS

µ
µ
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µ

PD77113A, 77114

PD77113A, 77114

Debugging Interface (JTAG)

Timing requirements

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

TCK cycle time

cTCK

120

TCK high-/low-level width

wTCK

TCK rise/fall time

rfTCK

= 1.8 to 2.7 V

TMS, TDI setup time

suDI

= 2.3 to 2.7 V

= 1.8 to 2.7 V

TMS, TDI hold time

hDI

= 2.3 to 2.7 V

= 1.8 to 2.7 V

Input pin setup time

suJIN

= 2.3 to 2.7 V

= 1.8 to 2.7 V

Input pin hold time

hJIN

= 2.3 to 2.7 V

TRST setup time

suTRST

100

Switching characteristics

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

= 1.8 to 2.7 V

TDO output delay time

dDO

= 2.3 to 2.7 V

= 1.8 to 2.7 V

Output pin output delay time

dJOUT

= 2.3 to 2.7 V

Data Sheet U14373EJ3V0DS

µ
µ
µ
µ

PD77113A, 77114

12. RECOMMENDED SOLDERING CONDITIONS

It is recommended to solder this product under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Surface mount type

µ
µ
µ
µ

PD77113AF1-xxx-CN1: 80-pin plastic fine-pitch BGA (9 x 9)

Soldering

Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 230

C, Time: 30 sec. Max. (at 210

C or higher).

Count: two times or less

Exposure limit: 3 days

Note

(after that prebake at 125

C for 10 hours)

IR30-103-2

Note After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

µ
µ
µ
µ

PD77114GC-xxx-9EU: 100-pin plastic TQFP (fine-pitch) (14 x 14)

Soldering

Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 sec. Max. (at 210

C or higher).

Count: two times or less

Exposure limit: 3 days

Note

(after that prebake at 125

C for 10 hours)

IR35-103-2

VPS

Package peak temperature: 215

C, Time: 40 sec. Max. (at 200

C or higher).

Count: two times or less

Exposure limit: 3 days

Note

(after that prebake at 125

C for 10 hours)

VP15-103-2

Partial heating

Pin temperature: 300

C Max., Time: 3 sec. Max. (per pin row)

Note After opening the dry pack, store is at 25

C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating for pins).

Data Sheet U14373EJ3V0DS

µ
µ
µ
µ

PD77113A, 77114

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet U14373EJ3V0DS

µ
µ
µ
µ

PD77113A, 77114

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829

J00.7

µ
µ
µ
µ

PD77113A, 77114

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

M8E 00. 4

The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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