4-BIT SINGLE-CHIP MICROCOMPUTER
NEC Corporation 1993
DESCRIPTION
The
PD75P336 is a version of the
PD75336 in which the on-chip mask ROM is replaced by one-time
PROM.
As the
PD75P336 is user-programmable, it is suitable for preproduction in system development, and for
short-run and multiple device-production.
Detailed function description, etc. are described in the following User's manual. Be sure to read it when
designing.
PD75336 User's Manual: IEU-725
FEATURES
PD75336 compatible
Memory capacity:
PROM : 16256
8 bits
RAM : 768
4 bits
Operable over same supply voltage range as mask ROM
PD75336
V
DD
= 2.7 to 6.0 V
On-chip 8-bits resolution A/D converter (successive approximation type)
On-chip LCD controller/driver
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
PD75P336GC-3B9
80-pin plastic QFP (
14mm)
Standard
PD75P336GK-BE9
80-pin plastic TQFP (fine pitch)( 12mm)
Standard
Note Pull-up resistor cannot be incorporated by mask option.
The information in this document is subject to change without notice.
MOS INTEGRATED CIRCUIT
PD75P336
DATA SHEET
Document No.
IC-2980A
(O. D. No.
IC-8371A)
Date Published October 1993P
Printed in Japan
The mark
5
shows major revised points.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
5
2
PD75P336
BLOCK DIAGRAM
PROGRAM
COUNTER
(15)
PROGRAM
MEMORY
(ROM)
16256
8 BITS
LCD
CONTROL-
LER
/DRIVER
S12-S23
S24/BP0
S31/BP7
COM0COM3
V
LC0
V
LC2
BIAS
LCDCL/P30
SYNC/P31
f
LCD
PORT 4
4
4
P00-P03
P20-P23
4
P10-P13
4
P30-P33
/MD0-MD3
4
P40-P43
PORT 5
4
P50-P53
PORT 6
4
P60-P63
PORT 7
4
P70-P73
PORT 8
4
P80-P83
GENERAL REG.
DATA
MEMORY
(RAM)
768
4 BITS
BANK
SP(8)
ALU
CY
DECODE
AND
CONTROL
RESET
V
SS
V
DD
CPU
CLOCK
V
PP
STAND BY
CONTROL
SYSTEM CLOCK
GENERATOR
SUB
MAIN
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
X2
X1
XT2
XT1
PCL/P22
f
X
/ 2
N
A/D
CONVERT-
ER
TIMER/EVENT
COUNTER
#0
WATCH
TIMER
CLOCKED
SERIAL
INTERFACE
INTER-
RUPT
CONTROL
BIT SEQ.
BUFFER (16)
INTCSI
INTW
f
LCD
INTT0
KR0/P60
KR3/P63
INT4/P00
INT2/P12
INT1/P11
INT0/P10
SCK/P01
SO/SB0/P02
SI/SB1/P03
BUZ/P23
TI0/P13
PTO0/P20
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#1
INTT1
TI1/P80
PTO1/P21
AV
REF
PORT 3
PORT 2
PORT 1
PORT0
12
8
4
3
AN0-AN7*
AV
SS
KR4/P70
KR7/P73
8
8
*
AN6/P82, AN7/P83
3
PD75P336
PD75P336GC-3B9
PD75P336GK-BE9
PIN CONFIGURATION (Top View)
q
q
80-pin plastic QFP (
s
s
14mm)
q
q
80-pin plastic TQFP (fine pitch) (
s
s
12mm)
*
In normal operation, V
PP
should be connected to V
DD
directly.
5
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
12
S12
8079787776 757473 7271 70696867666564636261
60
59
58
57
56
55
54
53
52
51
50
48
47
46
45
44
43
42
41
49
2122232425 262728 2930 31323334353637383940
S24/BP0
S20
S21
S22
AN2
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
COM0
COM1
COM2
COM3
BIAS
V
LC0
V
LC1
V
LC2
P40
P41
P42
P43
V
SS
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
P73/KR7
X2
RESET
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
X1
V
PP
*
XT2
XT1
V
DD
AV
REF
AV
SS
AN5
AN4
AN3
AN1
AN0
P83/AN7
P82/AN6
P81
P80/TI1
S13
S14
S15
S16
S17
S18
S19
S23
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
4
PD75P336
P00 to 03
: Port 0
P10 to 13
: Port 1
P20 to 23
: Port 2
P30 to 33
: Port 3
P40 to 43
: Port 4
P50 to 53
: Port 5
P60 to 63
: Port 6
P70 to 73
: Port 7
P80 to 83
: Port 8
BP0 to 7
: Bit Port
KR0 to 7
: Key Return
AV
REF
: Analog Reference
AV
SS
: Analog Ground
AN0 to 7
: Analog Input 0 to 7
SCK
: Serial Clock
SI
: Serial Input
SO
: Serial Output
MD0 to 3
: Mode Selection
V
PP
: Programming/Verifying
Power Supply
PIN NAME
SB0, 1
: Serial Bus 0,1
RESET
: Reset Input
S12 to 31
: Segment Output 12 to 31
COM0 to 3 : Common Output 0 to 3
V
LC0 to 2
: LCD Power Supply 0 to 2
BIAS
: LCD Power Supply Bias Control
LCDCL
: LCD Clock
SYNC
: LCD Synchronization
TI0, 1
: Timer Input 0, 1
PTO0, 1
: Programmable Timer Output 0, 1
BUZ
: Buzzer Clock
PCL
: Programmable Clock
INT0, 1, 4
: External Vectored Interrupt 0, 1, 4
INT2
: External Test Interrupt 2
X1, 2
: Main System Clock Oscillation 1, 2
XT1, 2
: Subsystem Clock Oscillation 1, 2
V
DD
: Positive Power Supply
V
SS
: Ground
5
PD75P336
CONTENTS
1.
PIN FUNCTIONS ......................................................................................................................................... 6
1.1
PORT PINS ............................................................................................................................................................. 6
1.2
OTHER PINS .......................................................................................................................................................... 8
1.3
PIN INPUT/OUTPUT CIRCUITS ........................................................................................................................... 10
2.
DIFFERENCES BETWEEN
PD75P336 AND
PD75336 ......................................................................... 13
2.1
PROGRAM MEMORY (PROM) 16256 WORDS
8 BITS .................................................................................. 14
2.2
DATA MEMORY (RAM) 768 WORDS
4 BITS .................................................................................................. 15
3.
INSTRUCTION SET AND INSTRUCTION OPERATIONS ....................................................................... 16
4.
ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS .................................. 25
4.1
PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ........................................................................... 26
4.2
PROGRAM MEMORY WRITE PROCEDURE ....................................................................................................... 27
4.3
PROGRAM MEMORY READ PROCEDURE ......................................................................................................... 28
5.
ELECTRICAL SPECIFICATIONS ................................................................................................................ 29
6.
PACKAGE INFORMATION ........................................................................................................................ 48
7.
RECOMMENDED SOLDERING CONDITIONS ......................................................................................... 50
APPENDIX A. LIST OF FUNCTIONS .............................................................................................................. 51
APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 52
6
PD75P336
Input
Input/output
Input/output
Input/output
Input
Input/output
Input/output
Input/output
Input/output
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30 *2
P31
*2
P32
*2
P33 *2
P40 to P43 *2
P50 to P53 *2
P60
P61
P62
P63
P70
P71
P72
P73
Dual-
Function Pin
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
INT2
TI0
PTO0
PTO1
PCL
BUZ
LCDCL MD0
SYNC MD1
MD2
MD3
--
--
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
I/O Circuit
Type *1
B
F - A
F - B
M - C
B - C
E - B
E - B
M - B
M - B
F - A
F - A
4-bit input port (PORT0)
Internal pull-up resistor specification by
software is possible for P01 to P03 as a 3-bit
unit.
4-bit input port (PORT1)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
4-bit input/output port (PORT2)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Programmable 4-bit input/output port (PORT3)
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
N-ch open-drain 4-bit input/output port (PORT
4).
Data input/output pins for program memory
(PROM) write/verify (low-order 4 bits).
N-ch open-drain 4-bit input/output port (PORT
5)
Data input/output pins for program memory
(PROM) write/verify (high-order 4 bits).
Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
4-bit input/output port (PORT7).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
With noise elimination circuit
Pin Name
Input/Output
Function
8-bit I/O
Input/output
Input/output
* 1.
: Indicates a Schmitt-triggered input.
2.
Direct LED drive capability.
Input
Input
Input
Input
Input
Input
Input
Input
1.
PIN FUNCTIONS
1.1
PORT PINS (1/2)
After Reset
7
PD75P336
1.1
PORT PINS (2/2)
P80
P81
P82
P83
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
Dual-
Function Pin
TI1
--
AN6
AN7
S24
S25
S26
S27
S28
S29
S30
S31
I/O Circuit
Type
E - E
E - B
Y - B
G - C
Input
*
4-bit input/output port (PORT8).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
1-bit output port (BIT PORT)
Dual function as segment output pins.
Input/output
Output
Output
Pin Name
Input/Output
Function
8-bit I/O
After Reset
*
V
LCX
shown below can be selected for the display outputs.
S12 to S31: V
LC1
,
COM0 to COM2: V
LC2
,
COM3: V
LC0
However, display output levels depend on the display outputs and V
LCX
external circuit.
8
PD75P336
B - C
B - E
E - B
E - B
E - B
F - A
F - B
M - C
B
B - C
B - C
F - A
F - A
--
B
E - B
--
--
--
External event pulse input pin for timer/event counter.
Timer/event counter output pin
Clock output pin
Frequency output pin (for buzzer or system clock
trimming)
Serial clock input/output pin
Serial data output pin
Serial bus input/output pin
Serial data input pin
Serial bus input/output pin
Edge-detected vectored interrupt input pin (both rising
and falling edge detection valid).
Edge-detected vectored
interrupt input pin (detected
edge selectable)
Edge-detected testable input pin
(rising edge detection)
Parallel falling edge detected testable input pins.
Parallel falling edge detected testable input pins.
Main system clock oscillation crystal/ceramic resonator
inputs. When an external clock is used, the clock is
input to X1 and the inverted clock to X2.
Subsystem clock oscillation crystal reasonator inputs
When an external clock is used, the clock is input to XT1
and the inverted clock toXT2. XT1 can be used as a 1-
bit input (test) pin.
System reset input pin.
Mode selection pin for program memory (PROM) write/
verify.
Program voltage application pin for program memory
(PROM) write/verify. Applies +12.5 V in program
memory write/verify.
Directly connected to V
DD
in normal operation.
Positive power supply pin
GND potential pin
TI0
TI1
PTO0
PTO1
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 to KR3
KR4 to KR7
X1, X2
XT1, XT2
RESET
MD0 to MD3
V
PP
V
DD
V
SS
Clocked
Asynchronous
Asynchronous
P13
P80
P20
P21
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 to P63
P70 to P73
--
--
--
P30 to P33
--
--
--
Input
output
output
output
Input/output
Input/output
Input/output
Input
Input
Input
Input
Input
--
--
Input
Input/output
--
--
--
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
--
--
--
Input
--
--
--
I/O Circuit
Type *
*
: indicates a Schmitt-triggered input.
Pin Name
Input/Output
Dual-
Function Pin
Function
1.2
OTHER PINS (1/2)
After Reset
9
PD75P336
G - A
G - C
G - B
--
--
E - B
E - B
Y
Y - B
Z
Z
1.2
OTHER PINS (2/2)
Input/Output
Function
S12 to S23
S24 to S31
COM0 to COM3
V
LC0
to V
LC2
BIAS
LCDCL*1
SYNC *1
AN0 to AN5
AN6
AN7
AV
REF
AV
SS
* 1.
Pins provided for future system expansion. Currently used only as pins 30 and 31.
2.
V
LCX
shown below can be selected for the display outputs.
S12 to S31: V
LC1
, COM0 to COM2: V
LC2
, COM3:V
LC0
However, display output levels depend on the display outputs and V
LCX
external circuit.
Output
Output
Output
Input
Output
Output
Output
Input
Input
--
--
BP0 to 7
--
--
--
P30
P31
--
P82
P83
--
--
*2
*2
*2
--
High impedance
Input
Input
Input
--
--
Segment signal output pins
Segment signal output pins
Common signal output pins
LCD drive power supply pins
External split cutting output pin
External extension driver drive clock output pin
External extension driver synchronization drive clock
output pin
A/D converter analog signal input pins
A/D converter reference voltage input pin
A/D converter GND potential pin
Pin Name
Dual-
Function Pin
After Reset
I/O Circuit
Type
10
PD75P336
1.3
PIN INPUT/OUTPUT CIRCUITS
The input/output circuits for each of the pin
PD75P336 are shown below in partially simplified form.
P-ch
V
DD
OUT
N-ch
data
output
disable
CMOS Standard Input Buffer
Push-Pull Output that can be Made High-Impedance
Output (P-ch and N-ch OFF)
TYPE A (For TYPE E-B)
TYPE D (For TYPE E-B, F-A)
TYPE B
TYPE E-B
TYPE B-C
TYPE E-E
Schmitt-Trigger Input with Hysteresis Characteristic
IN
P-ch
P.U.R.
P.U.R.
enable
V
DD
P.U.R. : Pull-Up Resistor
IN
P-ch
V
DD
IN
N-ch
P.U.R.
P-ch
IN/OUT
output
disable
data
output
disable
Type D
Type A
P.U.R.:Pull-Up Resistor
V
DD
Schmitt-Trigger Input with Hysteresis Characteristic
P.U.R.
P-ch
IN/OUT
P.U.R.
enable
data
output
disable
Type D
Type A
V
DD
Type B
P.U.R.:Pull-Up Resistor
11
PD75P336
TYPE F-B
TYPE G-C
TYPE G-A
TYPE M-B
TYPE F-A
TYPE G-B
P.U.R.
P-ch
IN/OUT
P.U.R.
enable
data
output
disable
Type D
Type B
P.U.R.:Pull-Up Resistor
V
DD
P.U.R.
IN/OUT
P.U.R.
enable
output
disable
(P)
output
disable
data
output
disable
(N)
V
DD
V
DD
P-ch
N-ch
P-ch
P.U.R.:Pull-Up Resistor
N-ch
P-ch
OUT
SEG
data
P-ch
V
LC0
V
LC1
V
LC2
N-ch
V
LC0
V
LC1
V
LC2
COM
data
N-ch
P-ch
P-ch
N-ch
OUT
N-ch
P-ch
P-ch
V
LC0
V
LC1
V
LC2
P-ch
N-ch
OUT
SEG
data/Bit Port data
N-ch
V
DD
IN/OUT
N-ch
data
output
disable
Middle-High Voltage Input Buffer
12
PD75P336
TYPE Y
TYPE Z
TYPE M-C
TYPE Y-B
P.U.R.
enable
IN/OUT
P-ch
V
DD
N-ch
data
output
disable
P.U.R.:Pull-Up Resistor
P.U.R.
+
-
V
DD
AV
SS
P-ch
N-ch
IN
V
DD
AV
SS
input
enable
Sampl-
ing C
Reference Voltage
(From Series Resistance
Voltage Tap)
AV
SS
IN
Reference Voltage
Type Y
Type A
IN/OUT
data
output
disable
Type D
P-ch
P.U.R:Pull-Up Resistor
V
DD
P.U.R
enable
13
PD75P336
2. DIFFERENCES BETWEEN
PD75P336 AND
PD75336
Parameter
Program memory
Data memory
Ports 4, 5 pull-up resistor
LCD drive power supply split
resistor
Subsystem clock oscillation
feedback resistor
Pin 69
PD75336
Mask ROM 16256
8 bits
768
4 bits
Incorporation specifiable by mask
option
Incorporation specifiable by mask
option
Incorporation specifiable by mask
option
IC
PD75P336
One-time PROM 16256
8 bits
768
4 bits
No
No
Incorporated
V
PP
14
PD75P336
2.1
PROGRAM MEMORY (PROM) ..... 16256 WORDS
8 BITS
The program memory consists of 16256-byte PROM. The program memory map is shown in Fig. 2-1.
Fig. 2-1 Program Memory Map
MBE
MBE
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
0FFFH
1000H
7
6
0
Internal Reset Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
I
NTBT/INT4 Start Address (High-Order 6 Bits)
INT0 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
(Low-Order 8 Bits)
INT1 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
INTT0 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
!faddr
Instruction
Entry
Address
BRCB !caddr
Instruction
Branch
Address
CALL !addr
Instruction
Branch Address
BR !addr
Instruction
Branch Address
Branch/Call
Address, by
GETI
BRCB !caddr
Instruction
Branch Address
RBE
RBE
MBE
RBE
(Low-Order 8 Bits)
MBE
RBE
INTCSI Start Address (High-Order 6 Bits)
MBE
RBE
INTT1 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
MBE
RBE
MBE
RBE
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
000CH
07FFH
0800H
1FFFH
2000H
2FFFH
3000H
3F7FH
15
PD75P336
Remarks
In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to addresses
with the low-order 8 bits only of the PC modified.
2.2
DATA MEMORY (RAM) .......768 WORDS
4 BITS
The configuration of the data memory is shown in Fig. 2-2. The data memory comprises a data area and peripheral
hardware area, the data area comprises 768
4-bit static RAM.
Fig. 2-2 Data Memory Map
(20
4)
256
4
256
4
128
4
(32
4)
Data Memory
Not On-Chip
Memory Bank 0
Memory Bank 1
Memory Bank 2
256
4
Memory Bank 15
F80H
FFFH
Peripheral Hardware Area
Data Area
Static RAM
768
4
General
Register Area
Stack Area
Display Data
Memory Area
2FFH
200H
1FFH
1ECH
1EBH
100H
0FFH
020H
01FH
000H
16
PD75P336
Description Method
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
XA, BC, DE, HL
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE' HL'
BC, DE, HL, XA', BC', DE', HL'
HL, HL+, HL, DE, DL
DE, DL
4-bit immediate date or label
8-bit immediate date or label
8-bit immediate date or label*
2-bit immediate date or label
0000H to 3F7FH immediate data or label
12-bit immediate date or label
11-bit immediate date or label
20H to 7FH immediate date (bit 0 = 0) or label
PORT0 to PORT8
IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW
RB0 to RB3
MB0, MB1, MB2, MB15
3.
INSTRUCTION SET AND INSTRUCTION OPERATIONS
(1) Operand identifier and description
Operand identifiers and description method operands are written in the operand column for each instruction in
accordance with the description method for the operand identifier for that instruction (refer to "RA75X Assembler
Package User's Manual Language Volume (EEU-730)" for details). Where multiple items are included in the
description method, one of those elements should be selected. Uppercase letters and the symbols + and are
keywords and should be written as they are.
In the case of immediate data, an appropriate number or label is written.
Descriptor
reg
reg1
rp
rp1
rp2
rp'
rp'1
rpa
rpa1
n4
n8
mem
bit
addr
caddr
faddr
taddr
PORTn
IE
RBn
MBn
fmem
pmem
FB0H to FBFH, FF0H to FFFH immediate data or label
FC0H to FFFH immediate data or label
*
In 8-bit data processing, only an even address can be specified.
17
PD75P336
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register; 4-bit accumulator
C
: C register; 4-bit accumulator
D
: D register; 4-bit accumulator
E
: E register; 4-bit accumulator
H
: H register; 4-bit accumulator
L
: L register; 4-bit accumulator
X
: X register; 4-bit accumulator
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC); 8-bit accumulator
DE
: Register pair (DE); 8-bit accumulator
HL
: Register pair (HL); 8-bit accumulator
XA'
: Extended register pair (XA')
BC'
: Extended register pair (BC')
DE'
: Extended register pair (DE')
HL'
: Extended register pair (HL')
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE : Register bank enable flag
PORTn
: Portn (n = 0 to 8)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IE
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Address, bit delimiter
(
)
: Contents addressed by
H
: Hexadecimal data
18
PD75P336
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
MB = MBE MBS MBS = 0, 1, 2, 15
MB = 0
MBE = 0 : MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 2, 15)
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
addr = 0000H to 3F7FH
addr = (Current PC) 15 to (Current PC) 1
(Current PC) + 2 to (Current PC) + 16
caddr = 0000H to 0FFFH (PC
13,12
= 00B) or
1000H to 1FFFH (PC
13,12
= 01B) or
2000H to 2FFFH (PC
13,12
= 10B) or
3000H to 3FFFH (PC
13,12
= 11B)
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
Program Memory
Addressing
(3) Description of addressing area field symbols
Remarks
1.
MB indicates the accessible memory bank.
2.
MB=0 irrespective of MBE and MBS in *2.
3.
MB=15 irrespective of MBE and MBS in *4 and *5.
4.
*6 to *10 indicate accessible area.
(4) Explanation of machine cycle column
"S" indicates the number of machine cycles required when an instruction with a skip function performs a
skip operation. The value of "s" is as follows:
When a skip is not performed ....................................................................................................................... S = 0
When the skipped instruction is a 1-byte or 2-byte instruction ................................................................ S = 1
When the skipped instruction is a 3-byte instruction (BR !addr or CALL !addr) ................................... S = 2
Note
A GETI instruction is skipped in one machine cycle.
One machine cycle is equivalent to one cycle (=t
CY
)of the CPU clock cycle
: any of four times can be
selected according to the PCC setting.
Data Memory
Addressing
19
PD75P336
Mne-
monic
Address-
ing Area
Operand
Operation
Skip Condition
1
2
2
2
2
1
2 + S
2 + S
1
2
1
2
2
2
2
2
2
2
2
2
1
2 + S
2 + S
1
2
2
2
1
2
3
3
A, #n4
reg1, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @HL+
A, @HL
A, @rpa1
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
XA, rp'
reg1, A
rp'1, XA
A, @HL
A, @HL+
A, @HL
A, @rpa1
XA, @HL
A, mem
XA, mem
A,reg1
XA, rp'
XA, @PCDE
XA, @PCXA
A
n4
reg1
n4
XA
n8
HL
n8
rp2
n8
A
(HL)
A
(HL), then L
L + 1
A
(HL), then L
L 1
A
(rpa1)
XA
(HL)
(HL)
A
(HL)
XA
A
(mem)
XA
(mem)
(mem)
A
(mem)
XA
A
reg
XA
rp'
reg1
A
rp'1
XA
A
(HL)
A
(HL), then L
L + 1
A
(HL), then L
L 1
A
(rpa1)
XA
(HL)
A
(mem)
XA
(mem)
A
reg1
XA
rp'
XA
(PC
138
+ DE)
ROM
XA
(PC
138
+ XA)
ROM
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
*1
*1
*1
*2
*1
*3
*3
Transfer
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
Bytes
Machine
Cycles
Stack A
Stack A
Stack B
L = 0
L = FH
L = 0
L = FH
Note 1.
Instruction Group
2.
Table reference
Note 1
Note 2
MOV
XCH
MOVT
20
PD75P336
Address-
ing Area
Operand
Operation
Skip Condition
Bytes
Mne-
monic
*4
*5
*1
*4
*5
*1
*1
*1
*1
*1
*1
*1
*1
carry
carry
carry
carry
carry
borrow
borrow
borrow
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
2
2
2
2
2
2
1 + S
2 + S
1 + S
2 + S
2 + S
1
2
2
1 + S
2 + S
2 + S
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
Machine
Cycles
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
fmem.bit, CY
pmem.@L, CY
@H + mem.bit, CY
A, #n4
XA, #n8
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
A, #n4
A, @HL
XA, rp'
rp'1, XA
CY
(fmem.bit)
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
(H + mem
3-0
.bit)
(fmem.bit)
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
(H + mem
3-0
.bit)
CY
A
A + n4
XA
XA + n8
A
A + (HL)
XA
XA + rp'
rp'1
rp'1 + XA
A, CY
A + (HL) + CY
XA, CY
XA + rp' + CY
rp'1, CY
rp'1 + XA + CY
A
A
-
(HL)
XA
XA
-
rp'
rp'1
rp'1
-
XA
A , CY
A
-
(HL)
-
CY
XA, CY
XA
-
rp'
-
CY
rp'1, CY
rp'1
-
XA
-
CY
A
A
n4
A
A
(HL)
XA
XA
rp'
rp'1
rp'1
XA
A
A
n4
A
A
(HL)
XA
XA
rp'
rp'1
rp'1
XA
A
A
n4
A
A
(HL)
XA
XA
rp'
rp'1
rp'1
XA
MOV1
ADDS
ADDC
SUBS
SBUC
AND
OR
XOR
Note Instruction Group
Note
Bit transfer
Operation
21
PD75P336
Bytes
Operand
Operation
Mne-
monic
Address-
ing Area
Skip Condition
A
A
reg
rp1
@HL
mem
reg
rp'
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp'
CY
CY
CY
CY
CY
A
0
, A
3
CY, A
n1
A
n
A
A
reg
reg + 1
rp1
rp1 + 1
(HL)
(HL) + 1
(mem)
(mem) + 1
reg
reg 1
rp'
rp' 1
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp'
CY
1
CY
0
Skip if CY = 1
CY
CY
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
1
2
1 + S
1 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1
1
1 + S
1
*1
*3
*1
*1
*1
Machine
Cycles
RORC
NOT
INCS
DECS
SKE
SET1
CLR1
SKT
NOT1
reg = 0
rp1 = 00H
(HL) = 0
(mem) = 0
reg = FH
rp' = FFH
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
XA = rp'
CY = 1
Note 1.
Instruction Group
2.
Accumulator operation
3.
Increment and decrement
4.
Carry flag manipulation
Comparison
Note 1
Note 2
Note 3
Note 4
22
PD75P336
Operation
Skip Condition
Operand
Mne-
monic
Address-
ing Area
Bytes
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
fmem.bit
pmem.@L
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
addr
!addr
!caddr
$addr
PCDE
PCXA
(mem.bit)
1
(fmem.bit)
1
(pmem
72
+ L
32
.bit (L
10
))
1
(H + mem
30
.bit)
1
(mem.bit)
0
(fmem.bit)
0
(pmem
72
+ L
32
.bit (L
10
))
0
(H + mem
30
.bit)
0
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (pmem
72
+ L
32
.bit (L
10
)) = 1
Skip if (H + mem
30
.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (pmem
72
+ L
32
.bit (L
10
))= 0
Skip if (H + mem
30
.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
72
+ L
32
.bit (L
10
)) = 1 and clear
Skip if (H + mem
30
.bit) = 1 and clear
CY
CY
(fmem.bit)
CY
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
CY
(H + mem
3-0
.bit)
CY
CY
(fmem.bit)
CY
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
CY
(H + mem
3-0
.bit)
CY
CY
(fmem.bit)
CY
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
CY
(H + mem
3-0
.bit)
PC
130
addr
(The assembler selects the optimum instruction
from among the BRCB !caddr, and BR $addr
instructions.)
PC
130
addr
PC
130
PC
13.12
+ caddr
110
PC
130
addr
PC
130
PC
13-8
+ DE
PC
130
PC
13-8
+ XA
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
--
3
2
1
2
2
2
2
2
2
2
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2
2
2
2
2
2
2
2
2
--
3
2
2
3
3
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
*6
*8
*7
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
Machine
Cycles
SET1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
BR
BR
BRCB
BR
BR
Note Instruction Group
Branch
Note
Memory bit manipulation
23
PD75P336
Operation
Skip Condition
Operand
Mne-
monic
Address-
ing Area
Bytes
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, RBE, PC
13.12
PC
130
addr, SP
SP 4
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, RBE, PC
13.12
PC
130
000 + faddr, SP
SP 4
MBE, RBE, PC
13.12
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
SP
SP + 4
MBE, RBE, PC
13.12
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
SP
SP + 4
the skip unconditionally
,
, PC
13.12
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
PSW
(SP + 4) (SP + 5), SP
SP + 6
(SP 1) (SP 2)
rp, SP
SP 2
(SP 1)
MBS, (SP 2)
RBS, SP
SP 2
rp
(SP + 1) (SP), SP
SP + 2
MBS
(SP + 1), RBS
(SP), SP
SP + 2
IME (IPS.3)
1
IE
1
IME (IPS.3)
0
IE
0
A
PORT
n
(n = 08)
XA
PORT
n+1
, PORT
n
(n = 4, 6)
PORT
n
A
(n = 28)
PORT
n+1
, PORT
n
XA
(n =4, 6)
Set HALT Mode (PCC.2
1)
Set STOP Mode (PCC.3
1)
No Operation
RBS
n
(n = 03)
MBS
n
(n = 0,1,2,15)
TBR Instruction
PC
130
(taddr)
50
+ (taddr + 1)
TCALL Instruction
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, RBE, PC
13, 12
PC
130
(taddr)
50
(taddr + 1)
SP
SP 4
Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
Machine
Cycles
Subroutine stack control
Note 1
3
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
!addr
!faddr
rp
BS
rp
BS
IE
IE
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
RBn
MBn
taddr
CALL
CALLF
RET
RETS
RETI
PUSH
POP
EI
DI
IN*1
OUT*1
HALT
STOP
NOP
SEL
GETI*2
3
2
3
3 + S
3
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
3
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------
-----------------------------
Note 2
Input/Output
Note 3
Special
*6
*9
*10
Unconditional
Conforms to
referenced
instruction.
24
PD75P336
*
1. At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance.
2. TBR and TCALL instructions are assembler pseudo-instructions for table definition.
Note
1. Instruction Group
2. Interruput control
3. CPU control
25
PD75P336
4.
ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS
The program memory incorporated in the
PD75P336 is 32640
8-bit electrically writable one-time PROM.
Write/verify operations on this one-time PROM are executed using the pins shown in the table below.
Address updating is performed by means of clock input from the X1 pin rather than by address input.
Voltage applecation pin for program memory write/verify
(normally V
DD
potential).
Address update clock inputs for program memory write/verify.
Inverse of X1 pin signal is input to X2 pin.
Operating mode selection pin for program memory write/verify.
8-bit data input/output pins for progrm memory write/verify.
Supply voltage application pin.
Applies 2.7 to 6.0 V in normal operation, and 6 V for program
memory write/verify.
V
PP
X1, X2
MD0 to MD3
P40 to P43 (low-order 4 bits)
P50 to P53 (high-order 4 bits)
V
DD
Note
1. Pins not used in a program memory write/verify operation are handled as follows:
Pins other than XT2 .......... Connect to V
SS
with a pull-down resistor
XT2 pins ............................. Leave open
2. Since the
PD75P336 is not provided with an erase window, program memory contents cannot be
erased with ultra-violet light.
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES
When +6 V is applied to the V
DD
pin and +12.5 V to the V
PP
pin, the
PD75P336 enters the program memory write/
verify mode. This mode comprises one of the operating modes shown below according to the setting of pins MD0
to MD3.
V
PP
+12.5 V
V
DD
+6V
MD0
H
L
L
H
MD1
L
H
L
X
MD2
H
H
H
H
MD3
L
H
H
H
Operating Mode
Program memory address zero-clear
Write mode
Verify mode
Program inhibit mode
X: L or H
Operating Mode Setting
Function
Pin Name
26
PD75P336
4.2
PROGRAM MEMORY WRITE PROCEDURE
The procedure for writing to program memory is as shown below, allowing high-speed writing.
(1) Unused pins are connected to V
SS
with a pull-down resistor. The X1 pin is driven low.
(2) 5 V is supplied to the V
DD
and V
PP
pins.
(3) 10
s wait.
(4) Program memory address zero-clear mode.
(5) 6 V is supplied to V
DD
, 12.5 V to V
PP
.
(6) Program inhibit mode.
(7) Data is written in 1 ms write mode.
(8) Program inhibit mode.
(9) Verify mode. If write is successful go to (10), otherwise repeat (7) to (9).
(10) (Number of times written in (7) to (9): X)
1 ms additional writes.
(11) Program inhibit mode.
(12) Program memory address is updated (+1) by inputting 4 pulses to the X1 pin.
(13) Steps (7) to (12) are repeated until the last address.
(14) Program memory address zero-clear mode.
(15) V
DD
/ V
PP
pin voltage is changed to 5 V.
(16) Power-off.
Steps (2) to (12) of this procedure are shown in the figure below.
Data Input
Data Input
Write
Verify
Additional
Write
Address
Increment
Repeated X Times
Data Output
V
PP
V
PP
V
DD
V
DD
V
DD
+ 1
V
DD
X1
P40-P43
P50-P53
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
27
PD75P336
4.3
PROGRAM MEMORY READ PROCEDURE
PD75P336 program memory contents can be read using the following procedure.
(1) Unused pins are connected to V
SS
with a pull-down resistor. The X1 pin is driven low.
(2) 5 V is supplied to the V
DD
and V
PP
pins.
(3) 10
s wait.
(4) Program memory address zero-clear mode.
(5) 6 V supplied to V
DD
, and 12.5 V to V
PP
.
(6) Program inhibit mode.
(7) Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per
4-pulse-input cycle.
(8) Program inhibit mode.
(9) Program memory address zero-clear mode.
(10) V
DD
/ V
PP
pin voltage is changed to 5 V.
(11) Power-off.
Steps (2) to (9) of this procedure are shown in the figure below.
Data Output
Data Output
V
PP
V
PP
V
DD
V
DD
V
DD
+ 1
V
DD
X1
P40-P43
P50-P53
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
PD75P336
28
PD75P336
PD75304B
PD75P336
5.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25
C)
CAPACITANCE (Ta = 25
C, V
DD
= 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
C
IN
15
pF
Output capacitance
C
OUT
15
pF
I/O capacitance
C
IO
15
pF
Peak value
Effective value
Peak value
Effective value
Peak value
Effective value
1 pin
All pins
1 pin
Total of ports 0, 2, 3, 5, 18
Total of ports 4, 6, 7
Output voltage
Output current high
V
O
I
OH
Ports 4, 5
Open-drain
V
I2
V
I1
Except ports 4, 5
Input voltage
Power supply voltage
V
DD
V
PP
15
30
30
15
100
60
100
60
40 to +85
65 to +150
0.3 to +11
0.3 to V
DD
+0.3
0.3 to +7.0
0.3 to +13.5
0.3 to V
DD
+0.3
PARAMETER
SYMBOL
TEST CONDITIONS
RATING
UNIT
V
V
mA
mA
mA
mA
mA
mA
mA
mA
C
C
V
V
V
I
OL
*
Output current low
Operating temperature
Storage temperature
T
opt
T
stg
*
Rms value is calculated from [effective value] = [peak value]
duty
5
f = 1 MHz
Unmeasured pins returned to 0 V.
PD75P336
29
PD75P336
PD75P336
PD75304B
PD75P336
MIN.
TYP.
MAX.
UNIT
After V
DD
reached the
MIN. of the
oscillator
voltage
range.
V
DD
= 4.5
to 6.0 V
X1
X1
C2
C1
V
DD
X1
X1
C2
C1
V
DD
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS
1.0
5.0*3
MHz
4
ms
1.0
4.19
5.0*3
MHz
10
ms
30
ms
1.0
5.0*3
MHz
100 500 ns
ESONATOR
RECOMMENDED
CONSTANT
PARAMETER
TEST
CONDITIONS
Oscillator
frequency (f
x
)*1
Oscillation
stabilization
time*2
Oscillator
frequency (f
x
)*1
Oscillation
stabilization
time*2
X1 input
frequency (f
x
)*1
X1 input
high-/low-level
width (t
XH
, t
XL
)
(Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
Ceramic
resonator
Crystal
resonator
External
clock
*
1. Shows the oscillator characteristics only. For the instruction execution time, see the AC characteristics.
2. Time necessary for oscillation to stabilize after V
DD
applied or STOP mode released.
3. When the oscillator frequency is "4.19 MHz < f
X
5.0 MHz", it is impossible to select of "PCC = 0011" with
1 machine cycle of less than 0.95
s as instruction execution time.
X1
X2
PD74HCU04
PD75P336
30
PD75P336
PD75304B
PD75P336
XT1
XT2
C4
C3
V
DD
R
XT1
XT2
Leave
Open
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS
32 32.768 35 kHz
1.0
2
s
10
s
32
100
kHz
5
15
s
XT1 input high-/
low-level width
(t
XTH
,t
XTL
)
RECOMMENDED
TEST
RESONATOR
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONSTANT
CONDITIONS
Oscillator
frequency (f
XT
)
V
DD
= 4.5
to 6.0 V
Oscillation
stabilization time
XT1 input
frequency (f
XT
)
(Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
Crystal
resonator
External
clock
Note
When the main system clock and subsystem clock oscillation circuit are used, area inside doted lines in
the figure should be wired as follows to prevent influence from the wiring capacitance, etc..
Wiring should be as short as possible.
Do not cross other signal lines, and do not place the oscillator close to line in which varying high
current flows.
Potential at the oscillator capacitor connecting point should always be the same as V
DD
. Do not
connect to the power supply pattern in which high current flows.
Do not fetch signals from the oscillator.
In the subsystem clock oscillator, which is designed to be a circuit with low amplification ratio to suppress
consumption current, misoperation due to noise occurs more often than in the main system clock
oscillator. Therefore, when using the subsystem clock, special care should be taken in the wiring method.
PD75P336
31
PD75P336
PD75P336
PD75304B
PD75P336
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Open-drain
V
DD
= 4.5 to
6.0 V
I
OH
= 1 mA
I
OH
= 100
A
V
DD
= 4.5 to
6.0 V
I
OH
= 100
A
I
OH
= 50
A
Ports 2, 3, 8
Ports 0, 1, 6, 7, RESET
Ports 4 and 5
X1, X2, XT1
Ports 2, 3, 4, 5, 8
Ports 0, 1, 6, 7 RESET
X1, X2, XT1
Ports
0, 2, 3, 6, 7, 8
BIAS
BP0 to BP7
(I
OH
2 outputs)
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V) (1/3)
V
IH1
V
IH2
V
IH3
V
IH4
V
IL1
V
IL2
V
IL3
V
OH1
V
OH2
Input voltage
high
Input voltage
low
Output voltage
high
0.7 V
DD
0.8 V
DD
0.7 V
DD
V
DD
0.5
0
0
0
V
DD
1.0
V
DD
0.5
V
DD
2.0
V
DD
1.0
V
DD
V
DD
10
V
DD
0.3 V
DD
0.2 V
DD
0.4
V
V
V
V
V
V
V
V
V
V
V
PD75P336
32
PD75P336
PD75304B
PD75P336
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V) (2/3)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Ports 3, 4, 5
V
DD
= 4.5 to
0.4
2.0
V
6.0 V
I
OL
= 15 mA
V
DD
= 4.5 to
6.0 V
0.4
V
I
OL
= 1.6 mA
I
OL
= 400
A
0.5
V
Open-drain
pull-up
0.2 V
DD
V
resistor
1 k
V
DD
= 4.5 to
6.0 V
1.0
V
I
OL
= 100
A
I
OL
= 50
A
1.0
V
Other than
below
X1, X2, XT1
20
A
Ports 4, 5
(when open-
20
A
drain)
Other than
below
X1, X2, XT1
20
A
Other than
below
Ports 4 and 5
(when open-
20
A
drain)
Output leakage
current low
V
DD
= 5.0 V
10%
V
DD
= 3.0 V
10%
I
LIL2
3
A
3
A
3
A
3
A
V
LCD
V
OL1
V
OL2
I
LIH1
I
LIH2
I
LIH3
I
LIL1
I
LOH1
I
LOH2
I
LOL
R
L1
Ports
0, 2, 3, 4, 5, 6
7, 8
SB0, 1
BP0 to BP7
(I
OL
2 outputs)
V
IN
= V
DD
V
IN
= 10 V
V
IN
= 0 V
V
OUT
= V
DD
V
OUT
= 10 V
V
OUT
= 0 V
Ports 0, 1, 2, 3, 6
7, 8 (Except P00)
V
IN
= 0 V
Output voltage
low
Input leakage
current high
Input leakage
current low
Output leakage
current high
Built-in Pull-up
resistor
LCD drive voltage
15
40
80 k
30
300 k
2.5 V
DD
V
PD75P336
33
PD75P336
PD75P336
PD75304B
PD75P336
V
LCD0
= V
LCD
V
LCD1
=
V
LCD
2/3
V
LCD2
=
V
LCD
1/3
2.7 V
V
LCD
V
DD
V
DD
= 5 V
10 %*4
V
DD
= 3 V
10 %*5
HALT
mode
Operat-
ing
mode
HALT
mode
V
DD
=
3 V
10 %
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V) (3/3)
PARAMETER
LCD output
voltage
deviation*1
(common)
LCD output
voltage
deviation*1
(segment)
Power supply
current
*2
SYMBOL
V
ODC
V
ODS
I
DD1
I
DD2
I
DD3
I
DD4
I
DD5
TEST CONDITION
I
O
=
5
A
I
O
=
1
A
4.19 MHz
crystal
oscillation
C1= C2 = 22 pF*3
32 kHz
crystal
oscillation*6
XT1 = 0 V
STOP mode
V
DD
= 5 V
10 %
MIN.
0
0
TYP.
5
1
500
300
100
20
0.5
0.1
0.1
MAX.
0.2V
0.2V
15
3
1500
900
300
60
20
10
5
UNIT
V
V
mA
mA
A
A
A
A
A
A
A
*
1. The voltage deviation means a difference between the ideal value of segment or common output (V
LCDn
;
n = 0, 1, 2) and the output voltage.
2. Current flowing in the built-in pull-up resistor and the LCD split resistor is not include.
3. Including the case where the subsystem clock is operating.
4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode.
5. When PCC is set to 0000 and operated in the low-speed mode.
6. The case where the system clock control register (SCC) is set to 1001, the main system clock oscillatio stopped
and the device is operated on the subsystem clock.
V
DD
=
5 V
10 %
V
DD
=
3 V
10 %
V
DD
=
3 V
10 %
V
DD
=
3 V
10 %
T
a
=
25
C
PD75P336
34
PD75P336
PD75304B
PD75P336
TEST CONDITION
2.5 V
AV
REF
V
DD
AV
REF
0.6 V
DD
2.5 V
AV
REF
V
DD
AV
REF
<
0.6 V
DD
*2
*3
A/D CONVERTER CHARACTERISTICS
PARAMETER
Resolution
Absolute
accuracy*1
Conversion time
Sampling time
Analog input
voltage
Analog input
impedance
AV
REF
current
SYMBOL
t
CONV
t
SAMP
V
IAN
R
AN
I
REF
(Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V, AV
SS
= V
SS
= 0 V)
10
Ta
+ 85
o
C
40
Ta <
10
o
C
t
CY
1.91
s
t
CY
<
1.91
s
10
Ta
+ 85
o
C
40
Ta
10
o
C
40
Ta
+ 85
o
C
*
1. Absolute accuracy excluding quantization (
1/2LSB) error.
2. Time up to end of conversion (EOC = 1) after execution of the conversion start instruction.
(40.1
s: f
x = 4.19 MHz operation)
3. Time up to end of sampling after execution of the conversion start instruction.
(10.5
s: f
x = 4.19 MHz operation)
MAX.
8
1.5
2.0
1.5
2.0
3.0
168/fx
44x
AV
REF
2.0
UNIT
bit
LSB
s
s
V
M
mA
TYP.
8
1000
1.0
MIN.
8
AV
SS
PD75P336
35
PD75P336
PD75P336
PD75304B
PD75P336
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operated
V
DD
= 4.5
by main
to 6.0 V
system
clock
3.8
64
s
Operated
by subsystem
114
122
125
s
clock
V
DD
= 4.5 to 6.0 V
0
1
MHz
0
275
kHz
V
DD
= 4.5 to 6.0 V
0.48
s
1.8
s
INT0
*2
s
INT1, 2, 4
10
s
KR0 to KR7
10
s
RESET low
level width
AC CHARACTERISTICS
0.95 64
s
t
CY
f
TI
t
TIH
,
t
TIL
t
INTH
,
t
INTL
t
RSL
(Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
10
s
CPU clock cycle
time (minimum
instruction
execution time = 1
machine cycle)*1
TI0, 1 input
frequency
TI0, 1 input high/
low level width
Interrupt input high/
low level width
* 1.
The CPU clock (
) cycle time is determined by the
oscillator frequency of the connected resonator
and the system clock control register (SCC) and
the processor clock control register (PCC). The
figure below shows the main system clock opera-
tion power supply voltage V
DD
vs cycle time t
CY
characteristics.
2.
Becomes 2
t
CY
or 128/f
X
depending on the
interrupt mode register (IM0) setting.
t
cy
vs V
DD
(Operating on Main System Clock)
Cycle Time t
cy
[ s]
Supply Voltage V
DD
[V]
0
1
2
3
4
5
6
0.5
1
2
3
4
5
30
64
70
6
Operating Guaranteed
Range
PD75P336
36
PD75P336
PD75304B
PD75P336
SERIAL TRANSFER OPERATION
2-wired and 3-wired serial I/O modes (SCK ... Internal clock output)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SI setup time
(to SCK
)
SI hold time
(from SCK
)
V
DD
= 4.5
R
L
= 1 k
,
to 6.0 V
C
L
= 100 pF*
1000
2-wired and 3-wired serial I/O modes (SCK ... External clock input)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
3200
ns
V
DD
= 4.5 to 6.0 V
400
ns
1600
ns
SI setup time
100
ns
(to SCK
)
SI hold time
400
ns
(from SCK
)
V
DD
= 4.5
to 6.0 V
1000
ns
*
R
L
and C
L
are the SO output line load resistance and load capacitance, respectively.
150
400
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
t
KH2
V
DD
= 4.5 to 6.0 V
1600
V
DD
= 4.5 to 6.0 V
3800
t
KCY1
/2-50
t
KCY1
/2-150
250
ns
ns
ns
ns
ns
ns
ns
V
DD
= 4.5 to 6.0 V
800
R
L
= 1 k
,
C
L
= 100 pF*
ns
300 ns
ns
SCK cycle time
SCK high/low
level width
SO output
delay time
from SCK
SCK cycle time
SCK high/low
level width
SO output
delay time
from SCK
t
KCY2
t
KL2
t
SIK2
t
KSI2
t
KSO2
PD75P336
37
PD75P336
PD75P336
PD75304B
PD75P336
SYMBOL
t
KCY3
t
KL3
t
KH3
t
SIK3
t
KSI3
t
KSO3
t
KSB
t
SBK
t
SBL
t
SBH
PARAMETER
SB0,1 setup time
(to SCK
)
SB0,1 hold time
(from SCK
)
SB0,1 output
delay time
from SCK
SB0,1
from SCK
SCK
from SB0, 1
SB0,1 low
level width
SB0,1 high
level width
TEST CONDITIONS
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
R
L
= 1 k
,
C
L
= 100 pF*
V
DD
= 4.5 to 6.0 V
MIN.
1600
3800
t
KCY3
/2-50
t
KCY3
/2-150
150
t
KCY3
/2
0
0
t
KCY3
t
KCY3
t
KCY3
t
KCY3
TYP.
MAX.
250
1000
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
SCK high/low
level width
SBI mode (SCK ... Internal clock output (master))
*
R
L
and C
L
are the SB0 and SB1 output line load resistance and load capacitance, respectively.
PD75P336
38
PD75P336
PD75304B
PD75P336
SBI mode (SCK ... External clock input (slave))
SYMBOL
t
KCY4
t
KL4
t
KH4
t
SIK4
t
KSI4
t
KSO4
t
KSB
t
SBK
t
SBL
t
SBH
PARAMETER
SB0,1 setup time
(to SCK
)
SB0,1 hold time
(from SCK
)
SB0,1 output
delay time
from SCK
SB0,1
from SCK
SCK
from SB0, 1
SB0,1 low
level width
SB0,1 high
level width
TEST CONDITIONS
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
R
L
= 1 k
,
C
L
= 100 pF*
V
DD
= 4.5 to 6.0 V
MIN.
800
3200
400
1600
100
t
KCY4
/2
0
0
t
KCY4
t
KCY4
t
KCY4
t
KCY4
TYP.
MAX.
300
1000
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*
R
L
and C
L
are the SB0 and SB1 output line load resistance and load capacitance, respectively.
SCK cycle time
SCK high/low
level width
PD75P336
39
PD75P336
PD75P336
PD75304B
PD75P336
X1 Input
1/f
X
t
XL
t
XH
V
DD
-0.5 V
0.4 V
XT1 Input
1/f
XT
t
XTL
t
XTH
V
DD
-0.5 V
0.4 V
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Test Points
TI0
1/f
TI
t
TIL
t
TIH
AC Timing Test Point(Exculuding X1 and XT1 Inputs)
Clock Timings
TI0 Timing
PD75P336
40
PD75P336
PD75304B
PD75P336
SCK
t
KCY1
t
KH1
t
KL1
Input Data
Output Data
t
SIK1
t
KSI1
t
KSO1
SI
SO
Serial Transfer Timing
3-wired serial I/O mode:
2-wired serial I/O mode:
t
KSO2
t
KL2
t
KH2
t
KCY2
SCK
SB0,1
t
SIK2
t
KSI2
PD75P336
41
PD75P336
PD75P336
PD75304B
PD75P336
t
INTL
t
INTH
INT0,1,2,4
KR0-7
t
RSL
RESET
t
KSB
t
SBL
t
SBH
t
SBK
t
KSO3,4
t
SIK3,4
t
KSI3,4
t
KL3,4
t
KH3,4
t
KCY3,4
SCK
SB0,1
t
KSB
t
KSO3,4
t
SIK3,4
t
KSI3,4
t
KL3,4
t
KH3,4
t
KCY3,4
SCK
SB0,1
t
SBK
Serial Transfer Timing
Bus release signal transfer:
Command signal transfer:
Interrupt Input Timing
RESET Input Timing
PD75P336
42
PD75P336
PD75304B
PD75P336
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DAT RETENTION CHARACTERISTICS (Ta = 40 to 85
C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention
supply voltage
Data retention
supply current*1
Release signal
set time
Oscillation
Release by RESET
2
17
/fx ms
stabilization
wait time*2
Release by interrupt request
*3 ms
*
1. Current flng in the built-in pull-up resistor is not included.
2. The oscillation stabilization wait time is the time CPU operation is stopped to prevent unstable operation at
start of oscillation.
3. Depends on the basic interval timer mode register (BTM) setting (table below).
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at fxx = 4.19 MHz)
--
0
0
0
2
20
/fxx (approx. 250 ms)
--
0
1
1
2
17
/fxx (approx. 31.3 ms)
--
1
0
1
2
15
/fxx (approx. 7.82 ms)
--
1
1
1
2
13
/fxx (approx. 1.95 ms)
V
DDDR
I
DDDR
t
SREL
t
WAIT
0
s
Waite Time
V
DDDR
= 2.0 V 0.1 10
A
2.0 6.0
V
PD75P336
43
PD75P336
PD75P336
PD75304B
PD75P336
STOP Mode
Data Retention Mode
STOP Instruction Execution
V
DD
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Standby Release Signal
(Interrupt Request)
STOP Mode
Data Retention Mode
STOP Instruction Execution
RESET
V
DD
Internal Reset Operation
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
PD75P336
44
PD75P336
PD75304B
PD75P336
D/C PROGRAMING CHARACTERISTICS (Ta = 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
= 0 V)
PARAMETER
Input voltage
high
Input voltage
low
Input leakage
current
Output voltage
high
Output voltage
low
V
DD
power supply
current
V
PP
power supply
current
SYMBOL
V
IH1
V
IH2
V
IL1
V
IL2
V
L1
V
OH
V
OL
I
DD
I
PP
TEST CONDITION
Except X1, X2
X1, X2
Except X1, X2
X1, X2
V
IN
=
V
IL
or V
IH
I
OH
=
1 mA
I
OL
=
1.6 mA
MD0
=
V
IL
, MD1
=
V
IH
MIN.
0.7V
DD
V
DD
-0.5
0
0
V
DD
-1.0
TYP.
MAX.
V
DD
V
DD
0.3V
DD
0.4
10
0.4
30
30
UNIT
V
V
V
V
A
V
V
mA
mA
* 1.
V
PP
must not exceed +13.5 V including overshoot.
2.
V
DD
should be applied before
V
PP
and cut after V
PP
.
A/D PROGRAMING CHARACTERISTICS (Ta = 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
=
0 V) (1/2)
TYP.
1.0
SYMBOL
t
AS
t
MIS
t
DS
t
AH
t
DH
t
DF
t
VPS
t
VDS
t
PW
*1
t
AS
t
OES
t
DS
t
AH
t
DH
t
DF
t
VPS
t
VCS
t
PW
TEST CONDITION
MIN.
2
2
2
2
2
0
2
2
0.95
MAX.
130
1.05
UNIT
s
s
s
s
s
s
s
s
ms
PARAMETER
Address setup time *2
(to MD0
)
MD1 setup time
(to MD0
)
Data setup time
(to MD0
)
Address hold time *2
(from MD0
)
Data hold time
(from MD0
)
Data output float
delay time from MD0
V
PP
setup time
(to MD3
)
V
DD
setup time
(to MD3
)
Initial program
pulse width
*
1. Symbol of the corresponding
PD27C256.
2. The internal address signal is incremented (+1) at the rising edge of the forth X1 input. The signal is not
connected to pins.
PD75P336
45
PD75P336
PD75P336
PD75304B
PD75P336
A/D PROGRAMING CHARACTERISTICS (Ta = 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
=
0 V) (2/2)
TYP.
SYMBOL
t
OPW
t
MOS
t
DV
t
M1H
t
M1R
t
PCR
t
XH,
t
XL
fx
t
I
t
M3S
t
M3H
t
M3SR
t
DAD
t
HAD
t
M3HR
t
DFR
MIN.
0.95
2
2
2
10
0.125
2
2
2
2
0
2
MAX.
21.0
1
4.19
2
130
2
*1
t
OPW
t
CES
t
DV
t
OEH
t
OR
t
ACC
t
OH
PARAMETER
Additional program
pulse width
MD0 setup time
(to MD1
)
Data output delay time
from MD0
MD1 hold time
(from MD0
)
MD1 recover time
(from MD0
)
Program conuter
reset time
X1
input
high/low width
X1 input frequency
Initial mode set time
MD3 setup time
(to MD1
)
MD3 hold time
(to MD1
)
MD3 setup time
(to MD0
)
Data output delay time
from address *2
Data output hold time
from address *2
MD3 hold time
(from MD0
)
Data output float
delay time from MD3
TEST CONDITION
MD0 = MD1 = V
IL
t
M1H
+ t
M1R
50
s
Program memory read
Program memory read
Program memory read
Program memory read
Program memory read
*
1. Symbol of the corresponding
PD27C256.
2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not
connected to pins.
UNIT
ms
s
s
s
s
s
s
MHz
s
s
s
s
s
s
s
s
PD75P336
46
PD75P336
PD75304B
PD75P336
Program Memory Write Timing mode:
Data Output
Data Output
V
PP
V
PP
V
DD
V
DD
V
DD
+ 1
V
DD
X1
P40-P43
P50-P53
MD0
MD1
MD2
MD3
t
VPS
t
VDS
t
XH
t
XL
t
I
t
DV
t
M3SR
t
HAD
t
DAD
t
M3HR
t
DFR
t
PCR
Program Memory Read Timing mode:
V
PP
V
PP
V
DD
V
DD
V
DD
+ 1
V
DD
X1
P40-P43
P50-P53
MD2
MD3
MD0
MD1
t
VPS
t
VDS
t
I
t
DS
t
OH
t
DV
t
DF
t
PW
t
M1R
t
M0S
t
DS
t
OPW
t
XH
t
XL
t
DH
t
AH
t
AS
t
PCR
t
M1S
t
M1H
t
M3S
t
M3H
Data Input
Data Input
Data Output
Data Input
47
PD75P336
6.
PACKAGE INFORMATION
5
A
M
F
B
60
61
40
K
L
80 PIN PLASTIC QFP ( 14)
80
1
21
20
41
G
D
C
detail of lead end
S
Q
P
M
I
H
J
55
N
S80GC-65-3B9-3
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
17.20.4
14.00.2
0.8
0.300.10
0.13
14.00.2
0.6770.016
0.031
0.031
0.005
0.026 (T.P.)
0.551
NOTE
M
N
0.10
0.15
1.60.2
0.65 (T.P.)
0.004
0.006
+0.004
0.003
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
0.0630.008
0.012
0.551
0.80.2
0.031
P
2.7
0.106
0.6770.016
17.20.4
0.8
+0.009
0.008
Q
0.10.1
0.0040.004
S
3.0 MAX.
0.119 MAX.
+0.10
0.05
+0.009
0.008
+0.004
0.005
+0.009
0.008
48
PD75P336
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
ITEM MILLIMETERS
INCHES
I
J
0.5 (T.P.)
0.10
0.004
0.020 (T.P.)
A
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
S
A
14.00.2
0.551 +0.009
0.008
B
12.00.2
0.472 +0.009
0.008
C
12.00.2
0.472 +0.009
0.008
D
14.00.2
0.551 +0.009
0.008
F
G
1.25
1.25
0.049
0.049
H
0.22
0.0090.002
P80GK-50-BE9-4
S
1.27 MAX.
0.050 MAX.
K
1.00.2
0.039 +0.009
0.008
L
0.50.2
0.020 +0.008
0.009
M
0.145
0.0060.002
N
0.10
0.004
P
1.05
0.041
Q
0.050.05
0.0020.002
R
55
55
+0.05
0.04
+0.055
0.045
B
C
D
J
H
I
G
F
P
N
L
K
M
Q
R
detail of lead end
M
61
60
41
40
21
20
1
80
49
PD75P336
7.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions in the table below.
For detail of recommended soldering conditions, refer to the information document "Surface Mount Technology
Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 7-1 Soldering Conditions
(1)
PD75P336GC-3B9 : 80-pin plastic QFP ( 14mm)
Recommended
Condition Symbol
Solderring Method
Solderring Conditions
Solder bath temperature: 260
C. max., Duration: 10 sec. max.,
Number of times: Once,
Time limit: 2 days* (thereafter 20 hours prebaking required at 125
C)
Preheat temperature: 120
C max. (package surface temperature)
Wave soldering
WS60-202-1
Package Peak temperature: 230
C, Duration: 30 sec. max., (at 210
C or above),
Number of times: Once,
Time limit: 2 days* (thereafter 20 hours prebaking required at 125
C)
Infrared reflow
Package Peak temperature: 215
C, Duration: 40 sec. max., (at 200
C or above),
Number of times: Once,
Time limit: 2 days* (thereafter 20 hours prebaking required at 125
C)
VPS reflow
Pin part temperature: 300
C or below,
Duration: 3 sec. max. (per device side)
Pin part heating
IR30-202-1
VP15-202-1
(2)
PD75P336GK-BE9 : 80-pin plastic TQFP (fine pitch) ( 12mm)
Recommended
Condition Symbol
Solderring Method
Solderring Conditions
Package Peak temperature: 235
C, Duration: 30 sec. max., (at 210
C or above),
Number of times: Once,
Time limit: 1 day* (thereafter 10 hours prebaking required at 125
C)
Infrared reflow
Package Peak temperature: 215
C, Duration: 40 sec. max., (at 200
C or above),
Number of times: Once,
Time limit: 1 day* (thereafter 10 hours prebaking required at 125
C)
VPS reflow
Pin part temperature: 300
C or below,
Duration: 3 sec. max. (per device side)
Pin part heating
IR35-101-1
VP15-101-1
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25
C, 65 % RH.
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
5
PD75P336
50
PD75P336
PD75P336
PD75304B
PD75304B
PD75P336
Item
Name
PD75336
PD75328
APPENDIX A. LIST OF FUNCTIONS
Main system
clock
Subsystem clock
CMOS input
CMOS input/output
CMOS output
N-ch open-drain
input/output
8
20
8
Same as at left
(but no pull-up resistor)
44
75X-High End
16256 (mask ROM) 16256 (PROM)
768
4 bits
8
4 banks
0.95
s, 1.91
s, 3.81
s, 15.3
s
(at 4.19 MHz operation)
122
s (at 32.768 KHz operation)
Internal pull-up resistor specifiable by software
Dual function as segment pins
Max.20
4 segment drive, variable duty: static, 1/2, 1/3, 1/4
8-bit resolution
8-ch (successive approximation
type)
Low-voltage operation capability: V
DD
= 2.7 to 6.0 V
Basic interval timer
1
Timer/event counter
2
Watch timer
1
NEC standard serial interface (SBI)
Clocked serial interface
External: 3 Internal: 4
External: 1 Internal: 1
, 524kHz, 262kHz, 65.5kHz (at 4.19MHz operation)
2kHz, 4kHz, 32kHz
Transfer, addition/subtraction, increment/decrement,
comparison
V
DD
= 2.7 - 6.0 V
80-pin plastic QFP ( 14 mm)
80-pin plastic TQFP (fine pitch) ( 12mm)
PD75P336 --
8 (10 V withstand
voltage, mask option
pull-up capability)
8 (10 V, withstand voltage
mask option pull-up
capability)
75X-Standard
8064 (mask ROM)
512
4 bits
8
1 bank
0.95
s, 1.91
s, 15.3
s
(at 4.19 MHz operation)
8-bit resolution
6-ch
(successive approxima-
tion type)
Low-voltage operation
capability: V
DD
= 3.5 to
6.0 V
Basic interval timer
1
Timer/event counter
1
Watch timer
1
External: 3 Internal: 3
External: 1 Internal: 1
2kHz
Transfer
PD75P328
PD75P336
CPU core
ROM (bytes)
RAM (
4 bits)
General registers
Instruction
cycle
Input/
output
ports
LCD controller/driver
A/D converter
Timer/counter
Serial Interface
Vectored interrupt
Test input
Clock output (PCL)
Buzzer output (BUZ)
8-bit data processing
Operating voltage
Package
On-chip PROM product
5
PD75P336
51
PD75P336
PD75P336
PD75P336
PD75304B
PD75304B
PD75P336
APPENDIX B. DEVELOPMENT TOOLS
The following support tools are available for system development using the
PD75P336.
Language Processor
Ordering Code (Product Name)
S5A13RA75X
S5A10RA75X
S7B10RA75X
Supply Medium
3.5-inch 2HD
5-inch 2HD
5-inch 2HC
Host Machine
PC-9800
series
IBM PC/AT
TM
OS
MS-DOSTM
Ver. 3.30
to
Ver. 5.00A*
PC DOSTM
(Ver. 3.1)
PROM programmer which enables a single-chip microcomputer with on-chip PROM to be
programmed in stand-alone mode or by operations from a host machine by connection of the
supplied board and a separately available programmer adapter.
Typical PROMs from 256K bits to 4M bits can also be programmed.
Ordering Code (Product Name)
S5A13PG1500
S5A10PG1500
S7B10PG1500
Supply Medium
3.5-inch 2HD
5-inch 2HD
5-inch 2HC
Host Machine
PC-9800
series
IBM PC/AT
Soft
ware
Hardware
MS-DOS
Ver. 3.30
to
Ver. 5.00A*
PC DOS
(Ver. 3.1)
OS
PROM Write Tools
Remarks
Assembler operation is only guaranteed for the host machines and operating systems quoted above.
PA-75P328GC
PA-75P336GK
PROM program adapter for the
PD75P336GK, used connect to the PG-1500.
PROM programmer adapter for the
PD75P336GC, used connected to the PG-1500.
Controls the PG-1500 on the host machine, with the PG-1500 and host machine connected via a
serial or parallel interface.
RA75X relocatable
assembler
PG-1500
PG-1500
controller
*
The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software.
Remarks
PG-1500 controller operation is only guaranteed for the host machines and operating systems quoted
above.
5
5
PD75P336
52
PD75P336
PD75P336
PD75304B
PD75304B
PD75P336
Debugging Tools
IE-75000-R*1
IE-75000-R-EM
EP-75338GC-R
The IE-75000-R is an in-circuit emulator which corresponds to the 75X series. For
PD75P336
development the IE-75000-R is used in conjunction with an emulation probe.
Efficient debugging is possible by connection to a host machine and PROM programmer.
Emulation board for the IE-75000-R and IE-75001-R. Incorporated in the IE-75000-R. Used in
conjunction with the IE-75000-R or IE-75001-R to perform
PD75P336 evaluation.
The IE-75001-R is an in-circuit emulator which corresponds to 75X series. For
PD75P336
development the IE-75001-R is used in conjunction with an emulation board IE-75000-R-EM*2
and emulation probe. Efficient debugging is possible by connection to a host machine and
PROM programer.
Emulation probe for
PD75P336GC. Used connect with the IE-75000-R or IE-75001-R, IE-75000-R-
EM.
An 80-pin LCC socket (EV-9200GC-80) is also available to simplify connection to the user system.
IE-75001-R
Emulation probe for
PD75336GK. Used connected with the IE-75000-R or IE-75001-R, IE-75000-R-
EM. An 80-pin conversion adapter (EV-9500GK-80 is also available to simplify connection to the
user system.
Supply Medium
3.5-inch 2HD
5-inch 2HD
5-inch 2HC
Connects the IE-75000-R or IE-75001-R to the host machine via by RS-232-C and contronix I/F and
controls the IE-75000-R or IE-75001-R on the host machine.
EV-9200G-80
EP-75336GK-R
IE control
program
Hardware
Soft
ware
* 1.
Maintenance product
2.
IE-75000-R-EM sold sparately
3.
The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software.
Remarks
Operations of the IE control program is only guaranteed for the host machines and operating systems
quoted above.
OS
MS-DOS
Ver. 3.30
to
Ver. 5.00A*3
PC DOS
(Ver. 3.1)
EV-9500GK-80
Host Machine
PC-9800
series
IBM PC/AT
Ordering Code (Product Name)
S5A13IE75X
S5A10IE75X
S7B10IE75X
5
PD75P336
53
PD75P336
PD75P336
PD75P336
PD75304B
PD75304B
PD75P336
Development Tools Configuration
5
User System
EP-75336GC-R
EP-75336GK-R
Emulation Probe
PD75P336GC
Pruducts
Incorporating
PROM
In-Circuit Emulator
IE-75000-R
PROM Programmer
PG-1500
Programmer Adapter
PA-75P328GC
Relocatable
Assembler
IE
Control
Program
PG-1500
Controller
Host Machine
PC-9800 Series
IBM PC/AT
(Symbolic Debugging
Possible)
Centronics I/F
RS-232-C
+
IE-75001-R*1
IE-75000-R-EM
*2
PD75P336GK
PA-75P336GK
*
1.
The IE-75001-R does not incorporate the IE-75000-R-EM
(Available separately.)
2.
EV-9200GC-80
EV-9500GK-80
PD75P336
54
PD75P336
PD75P336
PD75304B
PD75304B
PD75P336
PD75P336
55
PD75P336
PD75P336
PD75P336
PD75304B
PD75304B
PD75P336
[MEMO]
PD75P336
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard :
Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS
TM
is a trademark of MicroSoft Corporation.
PC DOS
TM
and PC/AT
TM
is a trademark of IBM Corporation.
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