MOS INTEGRATED CIRCUIT

DATA SHEET

PD75P238

4-BIT SINGLE CHIP MICROCOMPUTER

Document No. IC-2596A
(O.D. No. IC-8014A)
Date Published February 1994 P
Printed in Japan

The information in this document is subject to change without notice.

The mark 5 shows major revised points.

DESCRIPTION

The

PD75P238 is a version of the

PD75238 in which the on-chip mask ROM is replaced by one-time PROM or

EPROM.

The one-time PROM version can be written to once only, and is useful for short-run and multiple device-

production of sets and early start-up. Also, the EPROM version allows programs to be written and rewritten, and

is thus ideal for system evaluation.

Functions are described in detail in the following User's Manual, which should be read when carrying out design

work.

PD75238 User's Manual : IEU-731

The

PD75P238 EPROM product does not provide a level of reliability suitable for use as a volume

production product for users' devices. The EPROM product should be used solely for function evaluation

in experiments of preproduction.

FEATURES

PD75238 pin compatible

o On-chip PROM: 32640

o On-chip RAM: 1024

o Drive capability in same supply voltage range as mask version

PD75238 (2.7 to 6.0 V)

o Ports 4 & 5: No pull-up resistor

o Port 7: No pull-down resistor

Note

No internal pull-up and pull-down resistor function by mask option.

USE

VCR, Audio-visual, ECR, Microwave oven

ORDERING INFORMATION

Ordering Code Package On-Chip ROM Quality Grade

PD75P238GJ-5BG

94-pin plastic QFP(

20 mm)

One-time PROM

Standard

PD75P238KF

94-pin ceramic WQFN

EPROM

Standard

o High-voltage display outputs

. S0 to S8 & T0 to T9 : Internal pull-down resistors

. S9, S16 to S23 & T10 to T15: Open-drain

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

This manual describes common parts of One-time PROM and EPROM products as PROM.

PD75P238

PIN CONFIGURATION (TOP VIEW)

PD75P238GJ-

5BG

PD75P238KF

S20/P110

S21/P111

S22/P112

S23/P113

S0/P120

92919089

87 868584 8382 81807978777675747372

AN0

REF

XT2

XT1

S16/P100

S17/P101

S18/P102

S19/P103

P42

P43

P50

P51

P52

P53

P60

P61

P62

P63

P70

P71

P72

P73

P80/PPO

P81/SCK1

P82/SO1

P83/SI1

S4/P130

S5/P131

S6/P132

S7/P133

S8/P140

S9/P141

LOAD

T15/S10/P142

T14/S11/P143

PH0/T13/S12/P150

PH1/T12/S13/P151

PH2/T11/S14/P152

PH3/T10/S15/P153

P21

P22/PCL

P23/BUZ

P30/MD0

P31/MD1

AN4/P90

AN5/P91

AN6/P92

AN7/P93

RESET

P00/INT4

P01/SCK0

P02/SO0/SB0

P03/SI0/SB1

P10 /INT0

P11/INT1

P12/INT2

P13/TI0

P20/PTO0

25262728 293031 3233 343536373839404142 43

S1/P121

S2/P122

S3/P123

P41

P40

P32/MD2
P33/MD3

AN3

AN2

AN1

Remarks

IC (Internally Connected) pins should be connected directly to V

Note

Ensure that power is supplied to the V

and V

pins (pins 4, 11, 30, 48, and 65).

PD75P238

PIN NAME

P00 to P03

Port0

SCK0, SCK1

: Serial Clock I/O 0, 1

P10 to P13

Port1

SO0, SO1

: Serial Data Output 0, 1

P20 to P23

Port2

SI0, SI1

: Serial Data Input 0, 1

P30 to P33

Port3

SB0, SB1

: Serial Bus I/O 0, 1

P40 to P43

Port4

INT0, INT1, INT4 : External Vectored Interrupt Input 0, 1, 4

P50 to P53

Port5

INT2

: External Test Input 2

P60 to P63

Port6

PPO

: Programmable Pulse Output

P70 to P73

Port7

TI0

: Timer Input 0

P80 to P83

Port8

PTO0

: Programmable Timer Output 0

P90 to P93

Port9

BUZ

: Buzzer Clock

P100 to P103 :

Port10

PCL

: Programmable Clock Output

P110 to P113 :

Port11

AN0 to AN7

: Analog Input 0 to 7

P120 to P123 :

Port12

REF

: Analog Reference Voltage

P130 to P133 :

Port13

: Analog V

P140 to P143 :

Port14

: Analog V

P150 to P153 :

Port15

X1, X2

: Main System Clock Oscillation 1, 2

PH0 to PH3

PortH

XT1, XT2

: Subsystem Clock Oscillation 1, 2

T0 to T15

Digit Output

RESET

: Reset

S0 to S23

Segment Output

: Programming Power Supply

Positive Power Supply

MD0 to MD3

: Mode Selection 0 to 3

Ground

: Internally Connected

LOAD

Power Supply for FIP Driver

PD75P238

BLOCK DIAGRAM

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

P00-P03

P10-P13

P20-P23

P30/MD0
-P33/MD3

P40-P43

P50-P53

P60-P63

P70-P73

SP (8)

BANK

GENERAL REG.

RAM

DATA

MEMORY

1024

DECODE

AND

CONTROL

ALU

PROGRAM

COUNTER (15)

ROM

PROGRAM

MEMORY

32640

RESET

STAND BY
CONTROL

CPU CLOCK

CLOCK

GENERATOR

SUB

MAIN

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

PCL/P22

/ 2

BASIC

INTERVAL

TIMER

TIMER/EVENT

COUNTER

WATCH

TIMER

SERIAL

INTERFACE

INTW

INTBT

INTT0

SCK0/P01

SO0/SB0/P02

SI0/SB1/P03

BUZ/P23

TI0/P13

PTO0/P20

SBS (2)

FIP

CONTROLLER/

DRIVER

T0-T9

T10/S15/PH3/P153-
T13/S12/PH0/P150

S0/P120-S9/P141

S16/P100-S23/P113

ORT 0

PORT 8

P80-P83

P90-P93

PORT 9

T14/S11/ P143-
T15/S10/P142

LOAD

PORT 10-15

TIMER/

PULSE

GENELATOR

INTTPG

INTERRUPT

CONTROL

EVENT

COUNTER

INT4/P00

INT2/P12

INT1/P11

INT0/P10

PPO/P80

INTCSI

SERIAL

INTERFACE

SI1/P83

SO1/P82

SCK1/P81

A/D

CONVERTER

BIT SEQ.

BUFFER(16)

AN0-AN3

AN4/P90-AN7/P93

REF

TI0

P100-P153

XT2

XT1

TIO

PD75P238

PIN FUNCTIONS

1.1

PORT PINS (1/2)

Pin Name

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30 to P33 *2

P40 to P43 *2

P50 to P53 *2

P60 to P63

P70 to P73

Function

4-bit input port (PORT0).
Internal pull-up resistor specification by
software is possible for P01 to P03 as a 3-
bit unit.

4-bit input port (PORT1).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

4-bit input/output port (PORT2).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

Programmable 4-bit input/output port (PORT3).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

N-ch open-drain 4-bit input/output port
(PORT4).
Data input/output pins for program memory
write/verify (low-order 4 bits).

N-ch open-drain 4-bit input/output port
(PORT5).
Data input/output pins for program memory
write/verify (high-order 4 bits).

Input/Output

Input

Input/output

With noise elimination

function

Dual-Function

INT4

SCK0

SO0/SB0

SI0/SB1

INT0

INT1

INT2

TI0

PTO0

PCL

BUZ

MD0 to MD3

1. A circle denotes Schmitt-triggerd input.

2. Direct LED drive capability

After Reset

Input

Input/Output

Circuit Type*1

F A

F B

M C

B C

E B

E C

M A

E C

8-Bit I/O

Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

4-bit input/output port (PORT7).

PD75P238

1.1

PORT PINS (2/2)

Dual-

Function Pin

PPO

SCK1

SO1

SI1

AN4 to AN7

S16 to S19

S20 to S23

S0 to S3

S4 to S7

S10/T15

S11/T14

S12/T13/PH0

S13/T12/PH1

S14/T11/PH2

S15/T10/PH3

S12/T13/P150

S13/T12/P151

S14/T11/P152

S15/T10/P153

Input/Output

Input/output

Input

Output

Function

4-bit input port (PORT8).

4-bit input port (PORT9).

P-ch open-drain 4-bit high-voltage output port.

P-ch open-drain 4-bit high-voltage output port.
Internal pull-down resistors.

P-ch open-drain 4-bit high-voltage output port.
Internal pull-down resistor on P140 only.

P-ch open-drain 4-bit high-voltage output port.

Pin Name

P80

P81

P82

P83

P90 to P93

P100 to P103

P110 to P113

P120 to P123

P130 to P133

P140

P141

P142*2

P143*2

P150*2

P151*2

P152*2

P153*2

PH0

PH1

PH2

PH3

1. A circle denotes Schmitt-triggerd input.

2. Direct LED drive capability.

8-Bit I/O

After Reset

Input

High

impedance

LOAD

level

LOAD

level

High

impedance

High

impedance

Input/Output

Circuit Type*1

Y A

I D

I E

I D

Output

PD75P238

1.2

NON-PORT PINS (1/2)

Input/Output

Output

Input

Output

Input/output

Input

Input/output

Output

Input

Pin Name

PPO

TI0

PTO0

PCL

BUZ

SCK0

SO0/SB0

SI0/SB1

INT4

INT0

INT1

INT2

SCK1

SO1

SI1

AN0 to AN3

AN4 to AN7

REF

X1, X2

XT1

XT2

RESET

MD0 to MD3

Function

Timer/pulse generator pulse output pin.

External event pulse input pin for timer/event counter #0
or event counter #1.

Timer/event counter output pin.

Clock output pin.

Fixed-frequency output pin (for buzzer or system clock
trimming use).

Serial clock input/output pin.

Serial data output pin.
Serial bus input/output pin.

Serial data input pin.
Serial bus input/output pin.

Edge-detected vectored interrupt input pin (either rising
or falling edge detection).

Edge-detected vectored
interrupt input pin (detected
edge selectable).

Edge-detection testable input
pin (rising edge detection).

Serial clock input/output pin.

Serial data output pin.

Serial data input pin.

A/D converter analog input pin.

A/D converter reference voltage input pin.

A/D converter power supply pin.

A/D converter reference GND potential pin.

Main system clock oscillation crystal/ceramic resonator
input. When an external clock is used, the clock is input
to X1 and the inverted clock to X2.

Subsystem clock oscillation crystal resonator input.
When an external clock is used, the clock is input to XT1
and XT2 is left open.

System reset input pin.

Mode selection pin for program memory write/verify.

Internally Connected . Connect to V

directly.

Program voltage application pin for program memory
write/verify . Connected to V

in normal operation.

Applies +12.5 V in program memory write/verify.

Clocked

Asynchronous

Dual-

Function Pin

P80

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P81

P82

P83

P90 to P93

P30 to P33

After Reset

Input

Input/Output

Circuit Type*

B C

E B

F A

F B

M C

B C

Y A

E C

A circle denotes Schmitt-triggerd input.

PD75P238

1.2

NON-PORT PINS (2/2)

Pin Name

(3 pins)

(2 pins)

LOAD

T0 to T9 *

T10/S15 to

T13/S12

T14/S11

T15/S10

S0 to S3 *

S4 to S7 *

S8 *

S16 to S19

S20 to S23

Input/Output

After Reset

LOAD

level

High

impedance

High

impedance

LOAD

level

LOAD

level

LOAD

level

High

impedance

High

impedance

High

impedance

Dual-

Function Pin

PH3/P153 to

PH0/P150

P143

P142

P120 to P123

P130 to P133

P140

P141

P100 to P103

P110 to P113

Internal pull-down resistor

Output

Input/Output

Circuit Type

I D

I E

I D

I E

I D

Function

Positive power supply pins. Apply +6 V in PROM
write/verify.

Ground potential pin.

FIP controller/driver pull-down resistor connection/ power
supply pin.

Digit output high-voltage large large-current output pins.

Digit/segment output dual-function high-voltage large-
current output pins. Unused pins usable as Port H.
Usable as Port 15 in static mode.

Digit/segment output dual-function high-voltage large-

current output pin.

Usable as Port 14 in static mode.

Segment high-voltage output pins. Usable as Port 12 to
Port 14 in static mode.

Segment high-voltage output pins. Usable as Port 10 &
Port 11 in static mode.

PD75P238

1.3

PIN INPUT/OUTPUT CIRCUITS

The input/output circuits for each of the pins are shown in Fig. 1-1 in partially simplified form.

Fig. 1-1 Pin Input/Output Circuits (1/3)

P-ch

OUT

N-ch

data

output
disable

CMOS Standard Input Buffer

Push-Pull Output with High Impedance Output

Capability (P-ch and N-ch both OFF)

TYPE A

TYPE D

TYPE B

TYPE E

TYPE B-C

TYPE E-B

Schmitt-Triggered Input with Hysteresis

Characteristics

P-ch

N-ch

Input/Output Circuit Composed of Type D Push-Pull

Output and Type A Input Buffer

IN/OUT

data

output
disable

Type D

Type A

P-ch

P.U.R.

P.U.R.
enable

P.U.R. : Pull-Up Resistor

P.U.R.

P-ch

IN/OUT

output
disable

data

output
disable

Type D

Type A

P.U.R.:Pull-Up Resistor

Schmitt-Triggered Input with Hysteresis

Characteristics

PD75P238

P.U.R.

P-ch

IN/OUT

P.U.R.
enable

data

output
disable

Type D

Type B

P.U.R.:Pull-Up Resistor

IN/OUT

data

output
disable

Type D

Type B

Input /Output Circuit Composed of Type D Push-

Pull Output and Type B Schmitt-Triggered Input

P.U.R.

P-ch

IN/OUT

P.U.R.
enable

data

output
disable

Type D

Type A

P.U.R.:Pull-Up Resistor

P.U.R.

P-ch

IN/OUT

P.U.R.
enable

data

output
disable

Type D

Type B

P.U.R.:Pull-Up Resistor

P-ch

N-ch

data

OUT

P-ch

Fig. 1-1 Pin Input/Output Circuits (2/3)

TYPE F-B

TYPE E-C

TYPE F-C

TYPE F

TYPE F-A

TYPE I-D

P.U.R.

IN/OUT

P.U.R.
enable

output

disable

(P-ch)

output
disable

data

output

disable

(N-ch)

P-ch

N-ch

P-ch

P.U.R.:Pull-Up Resistor

Type B

PD75P238

Fig. 1-1 Pin Input/Output Circuits (3/3)

P-ch

N-ch

data

OUT

P-ch

P.D.R

LOAD

P.U.R.:Pull-Up Resistor

IN/OUT

N-ch

data

output
disable

Middle-High Voltage Input Buffer

P.U.R.
enable

IN/OUT

P-ch

N-ch

data

output
disable

P.U.R.:Pull-Up Resistor

P.U.R.

Type B

Sam-
pling
C

P-ch

N-ch

Reference Voltage
(From Series Resistance
String Voltage Tap)

Sam-
pling
C

P-ch

N-ch

Reference Voltage
(From Series Resistance
String Voltage Tap)

TYPE I-E

TYPE Y

TYPE Y-A

TYPE M-A

TYPE M-C

TYPE Z

P.D.R: Pull-Down Resistor

P.U.R: Pull-Up Resistor

PD75P238

Recommended Connection

P23/BUZ

P40 to P43

P50 to P53

P60 to P63

P70 to P73

P80 to PPO

P81 to SCK1

P30 to P33

P22/PCL

P21

P20/PTO0

P13/TI0

P10/INT0 to P12/INT2

P03/SI1/SB1

P02/SO0/SB0

P00/INT4

P01/SCK0

P82/SO1

P83/SI1

P90/AN4 to P93/AN7

Connect to V

or V

Connect to V

Input state

: Connect to V

or V

Output state :

Leave open.

Connect to V

or V

Connect to V

1.4

DISPOSITION OF UNUSED PIN

Table 1-2 Recommended Commection of Unused Pins (1/2)

PD75P238

DIFFERENCES BETWEEN

PD75P238 AND

PD75238

The

PD75P238 is a product with the program memory of the

PD75238 using on-chip mask ROM replaced by

one-time PROM or EPROM. Table 2-1 shows differences between

PD75P238 and

PD75238. The differences

between these products must be thoroughly checked when, for example, switching from use of PROM for

application system debugging and reproduction to use of a mask ROM product for volume production.

For details of CPU function and on-chip hardware, refer to the document "

PD75238 User's Manual" (IEU-731).

Table 2-1 Differences between

PD75P238 and

PD75238

PD75238

Parameter

ROM

Mask ROM

32K

One-time PROM, EPROM

32K

PD75P238

No. of segments

No. of digits

RAM

FIP controller/

driver

Pull-up resistors

9 to16

9 to 24

Ports 4 & 5

S0 to S8

S16 to S23

T0 to T9

T10 to T15

On-chip

Pull-down
resistors

Pin 5

Pins 70 to 73

P30/MD0 to P33/MD3

P30 to P33

Pin connection

The mask ROM products and PROM products have different consumption

currents, operating temperature range etc. See the Electrical Specifications

section in the relevant Data Sheet for details.

Electrical specifications

2.7 to 6.0 V

Operating supply voltage range

Subsystem clock feedback resistor

Mask option

On-chip

Package

94-pin plastic QFP (

20 mm)

94-pin ceramic WQFN

94-pin plastic QFP (

20 mm)

The mask ROM products and PROM products have different circuit scales and

mask layouts, and therefore differ in terms of noise resistance and noise

radiation.

Others

Note

Noise resistance and noise radiation differs between the PROM products and mask ROM products.

When investigating a switch from preproduction to volume production, throughout evaluation should

be carried out with the mask ROM CS product (not the ES product).

Port 7

Mask option

Product Name

PD75P238

PROGRAM MEMORY (PROM)

The program memory is PROM with a 32640

8-bit configuration wich stores program and table tata etc.

The program memory is addressed by the program counter. In addition, table data can be referenced by a table

referencing instruction (MOVT).

The rage of address to which branch instructions and subroutine call instructions and subroutine call instructions

and subroutine call instructions can branch is shown in Fig. 3-1. The entire space comprising 0000H to 7F7FH can

be directly branched to by the entire-space branch instruction (BRA !addr1) and the entire-space call instruction

(CALLA !addr1). The relative branch instruction (BR $addr) allows branching to addresses [PC contents 15 to 1

and +2 to +16] irrespective of block boundaries.

In addition, the following addresses are specially allocated (except for 0000H and 0001H, the entire area can be

used as ordinary program memory).

· Addresses 0000H & 0001H

Vector table to which the program start address and MBE & RBE set value upon RESET input are written.

Reset servicing can be started from any address in the 16K (000H to 3FFFH).

· Addresses 0002H to 000FH

Vector table to which the program start address and MBE & RBE set value for the various vectore interrupts

are written. Interrupt servicing can be started from any address in the 16K space (0000H to 3FFFH).

· Addresses 0020H to 007FH

Table area referenced by GETI instruction*.

The GETI instruction allows any 2- or 3-byte instruction or any two 1-byte instructions to be implemented as

1 byte, and is used to reduce the number of program steps.

PD75P238

Fig. 3-1 Program Memory Map

MBE RBE

MBE

MBE RBE

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

07FFH

0FFFH

Internal Reset Start Address

(Low-Order 8 Bits)

INT0 Start Address (High-Order 6 Bits)

(Low-Order 8 Bits)

INT1 Start Address (High-Order 6 Bits)

(Low-Order 8 Bits)

INTSO Start Address (High-Order 6 Bits)

(Low-Order 8 Bits)

INTT0 Start Address (High-Order 6 Bits)

GETI Instruction Reference Table

CALLF
! faddr
Instruction
Entry
Address

BRCB
! caddr
Instruction
Branch
Address

BR !addr
Instruction
Branch
Address

CALL !addr
Instruction
Branch Address

Branch/Call
Addresses
by GETI

BRCB !caddr instruction
Branch Address

(High-Order 6 Bits)

RBE

INTBT/INT4 Start Address (High-Order 6 Bits)

(Low-Order 8 Bits)

MBE RBE

INTTPG Start Address (High-Order 6 Bits)

(Low-Order 8 Bits)

000CH

MBE RBE

INTKS Start Address (High-Order 6 Bits)

(Low-Order 8 Bits)

2000H

1FFFH

2FFFH

3000H

3FFFH
4000H

4FFFH
5000H

5FFFH
6000H

6FFFH
7000H

7F7FH

0800H

1000H

BRCB !caddr instruction
Branch Address

BRA !addr
Instruction
Branch
Address

CALLA !addr
Instruction
Branch Address

BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)

000EH

Note

The above interrupt vector start addresses are 14-bit, and thus should be set in the 16K space

(0000H to 3FFFH).

Remarks In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to

addresses with the low-order 8 bits only of the PC modified.

PD75P238

4. STACK BANK SELECTION REGISTER (SBS)

The stack bank selection register specifies one memory bank from memory banks 0 to 3 as the stack area.Its format

is shown in Fig. 4-1.

The stack bank selection register is set by a 4-bit memory manipuration instruction. On RESET input bit only is

set to "1" and the remaining bits are undefined. Therefore this register must always be initialized to 00

××

B* at the

start of a program.

Fig. 4-1 Stack Bank Selection Register Format

3 2 1 0

SBS

Symbol

Stack Area Specification

Note After RESET input a subroutine call instruction and interrupt enabling instruction should be executed

after setting the stack bank selection register.

××

should be set to the desired value.

F84H SBS3 SBS2 SBS1 SBS0

Address

Memory bank 0

Memory bank 1

Memory bank 2

Memory bank 3

Ensure that 0 is written to bits 2 & 3.

PD75P238

PROGRAM MEMORY WRITE AND VERIFY OPERATIONS

The program memory incorporated in the

PD75P238 is 32640

8-bit electrically writable PROM. Write/verify

operations on this PROM are executed using the pins shown in the table below. Address updating is performed by

means of clock input from the X1 pin rather than by address input.

Table 5-1 Pins Used for Program Memory Write/Verify

X1, X2

MD0 to MD3

P40 to P43 (low-order 4 bits)

P50 to P53 (high-order 4 bits)

Pin Name

Function

Voltage applecation pin for program memory write/verify (normally V

potential).

Address update clock input for program memory write/verify.

Inverse of X1 pin signal is input to X2 pin.

Operating mode selection pin for program memory write/verify.

8-bit data input/output pin for progrm memory write/verify.

Supply voltage application pin.

Applies 2.7 to 6.0 V in normal operation, and 6 V for program

memory write/verify.

Note

1. Pins not used in a program memory write/verify operation are handled as follows:

Ports 0 to 2, ports 6 to 15

T0 to T9, AN0 to AN3, XT1 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Connect to GND

LOAD

, AV

REF

RESET

· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Connect to V

XT2 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Leave open

2. On the

PD75P238KF which is equipped with an erase window the shading cover film should be

attached except when performing EPROM erasure.

3. Since the

PD75P238GJ one-time PROM version is not provided with an erase window, program

memory contents cannot be erased.

PD75P238

Operating Mode Setting

Operating Mode

MD0 MD1 MD2 MD3

+ 12.5 V + 6 V

H L H L

L H H H Write mode

L L H H Verify mode

H H Program inhibit mode

Program memory address

zero-clear

Remarks

: L or H

5.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES

When +6 V is applied to the V

pin and +12.5 V to the V

pin, the

PD75P238 enters the program memory write/

verify mode. This mode comprises one of the operating modes shown in Table 5-2 according to the setting of pins

MD0 to MD3.

Table 5-2 Program Memory Write/Verify Operating Modes

PD75P238

5.2

PROGRAM MEMORY WRITE PROCEDURE

The procedure for writing to program memory is as shown below, allowing high-speed writing.

(1)

Unused pins are connected to V

. The X1 pin is driven low.

(2)

5 V is supplied to the V

and V

pins.

(3)

s wait.

(4)

Program memory address zero-clear mode.

(5)

6V is supplied to V

, 12.5 V to V

(6)

Program inhibit mode.

(7) Data is written in 1 ms write mode.

(8) Program inhibit mode.

(9) Verify mode. If write is successful go to (10), otherwise repeat (7) to (9).

(10) (Number of times written in (7) to (9): X)

1 ms additional writes.

(11) Program inhibit mode.

(12) Program memory address is updated (+1) by inputting 4 pulses to the X1 pin.

(13) Steps (7) to (12) are repeated until the last address.

(14) Program memory address zero-clear mode.

(15) V

/ V

pin voltage is changed to 5 V.

(16) Power-off.

Steps (2) to (12) of this procedure are shown in Fig. 5-1.

Fig. 5-1 Program Memory Write Timing

P40 to P43

0 to P53

MD0

(P30)

MD3

(P33)

MD2

(P32)

MD1

(P31)

+ 1

Data Input

Write

Verify

Additional
Write

Address
Increment

Repeated X Times

Data Output

PD75P238

5.3

PROGRAM MEMORY READ PROCEDURE

PD75P238 program memory contents can be read using the following procedure. Reading is performed in

verify mode.

(1) Unused pins are connected to V

. The X1 pin is driven low.

(2) 5 V is supplied to the V

and V

pins.

(3) 10

s wait.

(4) Program memory address zero-clear mode.

(5) 6 V supplied to V

, and 12.5 V to V

(6) Program inhibit mode.

(7) Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per

4-pulse-input cycle.

(8) Program inhibit mode.

(9) Program memory address zero-clear mode.

(10) V

/ V

pin voltage is changed to 5 V.

(11) Power-off.

Steps (2) to (9) of this procedure are shown in Fig. 5-2.

P40 to P43

P50 to P53

MD0

(P30)

MD1

(P31)

MD2

(P32)

MD3

(P33)

Fig. 5-2 Program Memory Read Timing

Data Output

"L"

PD75P238

5.4 ERASURE (

PD75P238KF ONLY)

The Programmed data contents of the

PD75P238KF can be erased by exposure to ultraviolet light through the

window in the top.

The ultraviolet wave length which effects erasure is 250 nm, and the quantity of radiation necesary for complete

erasure is 15 W·s/ cm

(ultraviolet radiation intensity x erasure time). Using a commercially available ultraviolet lamp

(254 nm vavelength, 12 mW/cm

intensity) erasure can be accomplished in approximately 15 to 20 minutes.

Note

1. Memory contents may also be erased by prolonged exposure to direct sunlight fluorescent lighting.

To protect the contents ensure that the top window is masked with the shading cover film. The shading

cover film supplied with NEC's UV EPROM products should be used.

2. When carrying out erasure the distance between the ultraviolet lamp and the

PD75P238KF should

normally be no greater than 2.5 cm.

Remarks

A longer erasure time may be required if there is deterioration of the ultraviolet lamp, or if the

package window is not clean, etc.

PD75P238

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25

PARAMETER

SYMBOL

TEST CONDITIONS

RATING

UNIT

0.3 to +7.0

Supply voltage

LOAD

40 to V

+0.3

0.3 to +13.5

Except ports 4, 5

0.3 to V

+0.3

Input voltage

Ports 4, 5

Open-drain

0.3 to +11

Pins except display output pins

0.3 to V

+0.3

Output voltage

Display output pins

40 to V

+0.3

1 pin except display output pins

S0 to S9, S16 to S23 1 pin

Output current

high

T0 to T15 1 pin

All pins except display output pins

All display output pins

120

Peak value

1 pin

Effective value

Peak value

100

Output current

Total of port 0, 2, 3, 4

low

Effective value

Peak value

100

Total of port 5 to 8

Effective value

Operating

opt

40 to +70

temperature

Storage

stg

65 to +150

temperature

The Effective value should be calculated as follows. [Effective value] = [Peak value]

Duty

Note

Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,

or even momentarily. In other words, the absolute maximum ratings are rated values at which the

product is on the verge of suffering physical damage, and therefore the product must be used under

conditions which ensure that the absolute ratings are not exceeded.

PD75P238

* 1.

Except the system clock oscillator, display controller and timer/pulse generator.

The operating power supply voltage range varies depending on the cycle time. Refer to the section describing

AC characteristics.

OPERATING SUPPLY VOLTAGE RANGE (Ta = 40 to +70

PARAMETER

TEST CONDITIONS

MIN.

MAX.

UNIT

CPU*1

6.0

Display controller

4.5

6.0

Timer/pulse generator

4.5

6.0

Other hardware*1

2.7

6.0

PD75P238

MAIN SYSTEM CLOCK RESONATOR CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V)

RECOMMENDED

TEST

RESONATOR

PARAMETER

MIN.

TYP.

MAX.

UNIT

CHARACTERISTICS

CONDITIONS

Oscillator

2.0

6.2

MHz

frequency (f

)*1

After V

Oscillation

has reached

stabilization

MIN. value of

time*2

oscillator
voltage
range.

Oscillator

2.0

4.19

6.2

MHz

frequency (f

)*1

= 4.5

Oscillation

to 6.0 V

stabilization
time*2

X1 input

2.0

6.2

MHz

frequency (f

)*1

X1 input
high and low level

250

width (t

, t

)

* 1.

Oscillator frequency and input frequency indicate oscillator characteristics only. Refer to the AC character-

istics for the instruction execution time.

Oscillation stability time is time required for oscillation to stabilize after V

has reached the MIN. value in

oscillation voltage range or STOP mode has been released.

Note

When the main system clock oscillator is used, the following should be noted concerning wiring in

the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.

· The wiring should be kept as short as possible.

· No other signal lines should be crossed.

· Keep away from lines caring a high fluctuating current.

· The oscillator capacitor grounding point should always be at the same potential as V

. Do not

connect to a ground pattern carrying a high current.

· A signal should not be taken from the oscillator.

Ceramic

resonator

Crystal

resonator

External

Clock

= Oscillator

voltage range

PD74HCU04

PD75P238

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V)

RECOMMENDED

TEST

RESONATOR

PARAMETER

MIN.

TYP.

MAX.

UNIT

CHARACTERISTICS

CONDITIONS

Oscillator

32.768

kHz

frequency (f

)*1

= 4.5

1.0

to 6.0 V

XT1 input

100

kHz

frequency (f

)*1

* 1.

Oscillator frequency and input frequency indicate oscillator characteristics only. Refer to the AC character-

istics for the instruction execution time.

Oscillation stability time is time required for oscillation to stabilize after V

has reached the MIN. value in

oscillation voltage range.

Note

When subsystem clock oscillator is used, the following should be noted concerning wiring in the area

in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.

· The wiring should be kept as short as possible.

· No other signal lines should be crossed.

· Keep away from lines caring a high fluctuating current.

· The oscillator capacitor grounding point should always be at the same potential as V

. Do not

connect to a ground pattern carrying a high current.

· A signal should not be taken from the oscillator.

The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current,

and is more prone to misoperation due to noise than the main system, clock oscillator. Particular care is

therefore required with the wiring method when the subsystem clock is used.

XT1

XT2

X1 input
high and low level

width (t

XTH

, t

XTL

)

Oscillation
stabilization
time*1

External

Clock

Crystal

resonator

CAPACITANCE (Ta =25

C, V

= 0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Input capacitance

Output capacitance

(Output except display output)

Input/output capacitance

Output capacitance

(Display output)

XT1

XT2

f = 1 MHz
0 V for pins except measured pins

PD75P238

RECOMMENDED OSCILLATOR CONTANTS

MAINSYSTEMCLOCK : CERAMIC RESONATOR (Ta = 40 to + 85

MIN.

2.7

3.0

3.3

4.0

MAX.

6.0

FREQUENCY

(MHz)

--------------------------

REMARKS

On-chip capacitor product

---------------------------------------

MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = 20 to + 70

MIN.

4.0

MAX.

6.0

HC-49/U-S

RECOMMENDED

OSCILLATOR

CONSTANTS(pF)

OSCILLATOR

VOLTAGE

RANGE(V)

3.072 to 6.000

2.0

2.5

4.19

2.5

4.19

6.00

PRODUCT NAME

FREQUENCY

(MHz)

REMARKS

RECOMMENDED

OSCILLATOR

CONSTANTS(pF)

OSCILLATOR

VOLTAGE

RANGE(V)

CSA2.0MG

CST2.0MG

CSA2.5MG093

CST2.5MGW093

CSA4.19MGU

CST4.19MGWU

CSA2.5MG

CST2.5MGW

CSA4.19MG

CST4.19MGW

CSA6.0MG

CST6.0MGW

PRODUCT NAME

Murata Mfg.

MAUNFAC-

TURER

Kinseki, Ltd.

MAUNFAC-

TURER

----------------------------

PD75P238

= 4.5 to

6.0 V

0.7 V

Input voltage
high

Input voltage
low

Output voltage
low

Output voltage
high

IH1

IH4

IL1

Input leakage
current high

LIH1

LIL1

Input leakage
current low

SB0, SB1

All output
pins

Ports 3, 4, 5

DC CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V) (1/3)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

All ports and pins except those
listed below.

IH2

Port 0, 1, RESET, P81, P83

0.8 V

IH3

X1, X2, XT1

0.4

0.65 V

0.7 V

IH5

Port 4, 5

Open-drain

0.7 V

All ports and pins except those
listed below.

IL2

Port 0, 1, RESET, P81, P83

0.2 V

IL3

X1, X2, XT1

0.4

= 4.5

to 6.0 V

= 2.7 I

0.5

to 6.0 V

100

= 4.5

to 6.0 V

= 4.5 I

0.4

to 6.0 V

1.6 mA

= 2.7 I

0.5

to 6.0 V

400

Open-drain

0.2 V

pull-up
resistor

1 k

All ports and

pins except

those listed

below.

LIH2

X1, X2, XT1

LIH3

Ports 4, 5

= 10 V

All ports and

pins except

those listed

below.

LIL2

X1, X2, XT1

All output
pins, except
port 4, 5 and
P03

= 0 V

= V

= 1 mA

1.0

= 15 mA

0.4

2.0

Port 7

0.3 V

PD75P238

DC CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V) (2/3)

Output leakage
current high

Output leakage
current low

Display output
current

On-chip pull-up

resistor

Power supply

current*1

OUT

= V

= 4.5 to 6.0 V

= V

2 V

Display
output

Operat-
ing
mode

HALT
mode

Operat-
ing
mode

HALT
mode

LOH1

LOL2

LOL1

DDI

DD2

DDI

DD2

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

All ports and
pins except
those listed
below.

LOH2

Port 4, 5

OUT

= 10 V

All ports and
pins except

those listed

below.

Display

OUT

= V

LOAD

output

35 V

S0 to S9,

5.5

S16 to S23

T0 to T15

On-chip pull-down

resistor

LOAD

= 35 V

135

(Mask option)

Port 0, 1, 2, 3,

= 5 V

10%

6 (Except P00)

= 0 V

= 3 V

10%

300

= 5V

10%*2

= 3 V

10%*3

= 5 V

900

2700

10%

= 3 V

300

900

10%

= 5 V

10%*2

= 3 V

0.9

2.7

10%*3

= 5 V

600

1800

10%

= 3 V

200

600

10%

* 1.

Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included.

When the processor clock control register (PCC) is set to 0011 and is operated at high-speed mode.

When the PCC register is set to 0000 and is operated in the low-speed mode.

Includes the case where the subsystem clock oscillating.

OUT

= 0 V

6MHz crystal
oscillation
C1 = C2 =
22 pF*4

4.19MHz
crystal
oscillation
C1 = C2 =
22 pF*4

PD75P238

Operat-

DD3

ing

100

300

mode

HALT

= 3 V

mode

10%

= 5 V

10%

0.5

DD5

0.3

Ta = 25

32 kHz
crystal

oscillation*2

DC CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V) (3/3)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Power supply
current*1

DD4

DD6

32 kHz
crystal
oscillation*2

STOP
mode

= 3 V

10%

= 3 V

10%

= 3 V

10%

XT1 = 0 V
STOP mode

* 1.

Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included.

When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with

main system clock oscillation stopped.

* 1.

Absolute accuracy except quantization error (

1/2 LSB).

Time from execution of conversion start instruction to EOC = 1 (28.0

s when f

= 6.0 MHz, 40.1

s when f

= 4.19 MHz)

Time from execution of conversion start instruction to the end of sampling (7.33

s when f

= 6.0 MHz, 10.5

s when f

= 4.19 MHz)

Resolution

bit

+70

1.5

LSB

Ta < 10

2.0

Conversion time

CONV

168/f

Sampling time

SAMP

44/f

Analog input
voltage

Analog input
impedance

REF

current

AREF

1.0

2.0

A/D CONVERTER CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V, AV

= V

= 0 V, 2.7

)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Absolute
accuracy*1

IAN

REF

1000

2.5 V

REF

PD75P238

* 1.

CPU clock (

) cycle time is determined by the

oscillator for frequency of the connected oscil-

lator, the system clock control register (SCC)

and processor clock control register (PCC). The

cycle time t

characteristics for supply voltage

when the main system clock is in operation

is shown on the right.

or 128/f

is set by interrupt mode register

(IM0) setting.

AC CHARACTERISTICS (Ta = 40 to +70

C, V

= 2.7 to 6.0 V)

(1) Basic Operation

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Operation with

= 4.75

0.67

main system

to 6.0 V

clock

2.6

Operation with subsystem clock

114

122

125

= 4.5 to 6.0 V

MHz

275

kHz

= 4.5 to 6.0 V

0.48

1.8

Interrupt input high

INT0

and low-level
widths

INT1, 2, 4

RESET low level

widths

TIH

TIL

RSL

INTH

INTL

TI0 input high and
low-level widths

vs V

(When main system clock is in operation)

Cycle Time t

[ s]

Power Supply Voltage V

[V]

0.5

Operation Guaranteed
Range

TI0 input frequency

CPU clock cycle time

(minimum instruction

execution time

= one machine cycle)*1

PD75P238

(2) Serial Transfer Operation

(a) 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

= 6.0 MHz

1340

= 4.19 MHz

1600

= 6.0 MHz

2680

= 4.19 MHz

3800

KCY1

/2)

-50

KCY1

/2)

-150

150

SI hold time

400

(from SCK

)

= 4.5

250

= 1 k

to 6.0 V

= 100 pF*

1000

* R

and C

denote load resistor and load capacitance of SO output line.

(b) 2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

= 4.5 to 6.0 V

800

3200

= 4.5 to 6.0 V

400

1600

100

400

300

1000

* R

and C

denote load resistor and load capacitance of SO output line.

SCK cycle time

KCY1

= 4.5 to 6.0 V

SCK high and low

KL1

level widths

KH1

SIK1

KSI1

KSO1

SO output
delay time
from SCK

SCK cycle time

KCY2

SCK high and low

KL2

level widths

KH2

SIK2

KSI2

KSO2

SO output
delay time
from SCK

SI setup time
(to SCK

)

SI setup time
(to SCK

)

SI hold time
(from SCK

)

= 1 k

= 100 pF*

= 4.5

to 6.0 V

PD75P238

(c) SBI Mode (SCK ... Internal clock output (Master))

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

= 6.0 MHz

1340

= 4.19 MHz

1600

= 6.0 MHz

2680

= 4.19 MHz

3800

= 4.5 to 6.0 V

KCY3

/2-50

KCY3

/2-150

SB0, 1 setup time

150

(to SCK

)

SB0, 1 hold time
(from SCK

)

SB0, 1 output

= 1 k

= 4.5 to 6.0 V

250

delay time from

= 100 pF*

SCK

1000

SB0, 1

from

SCK

SCK from SB0, 1

SBK

KCY3

SB0, 1 low level
widths

SB0, 1 high level
widths

* R

and C

denote load resistor and load capacitance of SO output lines.

= 4.5 to 6.0 V

SCK cycle time

KCY3

SCK high and low
level widths

KL3

KH3

SIK3

KSI3

KSO3

KSB

KCY3

SBL

KCY3

SBH

KCY3

PD75P238

(d) SBI Mode (SCK ... External clock input (Slave))

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

KCY4

= 4.5 to 6.0 V

800

3200

SCK high and low

KL4

= 4.5 to 6.0 V

400

level widths

KH4

1600

SB0, 1 setup time
(to SCK

)

SB0, 1 hold time
(from SCK

)

SB0, 1 output

= 4.5 to 6.0 V

300

delay time from
SCK

1000

SB0, 1

from SCK

KSB

KCY4

SCK

from SB0, 1

SBK

KCY4

SB0, 1 low level
widths

SB0, 1 high level
widths

* R

and C

denote load resistor and load capacitance of SO output lines.

KSI4

KCY4/

SIK4

100

SBL

KCY4

SBH

KCY4

KSO4

= 1 k

= 100 pF*

PD75P238

DDDR

2.0

6.0

DDDR

= 2.0 V

0.1

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = 40 to 70

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Data retention power
supply voltage

Data retention power
supply current*1

Release signal
set time

Oscillation

Release by RESET

/fx

stabilization
wait time*2

Release by interrupt request

* 1.

Current to the on-chip pull-up resistor and power-on reset circuit (mask option) is not included.

Oscillation stability wait time is time to stop CPU operation to prevent unstable operation upon oscillation start.

According to the setting of the basic interval timer mode register (BTM). (see below)

Wait Time

BTM3

BTM2

BTM1

BTM0

Values at f

= 6.0 MHz in Parentheses

Values at f

= 4.19 MHz in Parentheses

/fx (approx. 175 ms)

/fx (approx. 250 ms)

/fx (approx. 21.8 ms)

/fx (approx. 31.3 ms)

/fx (approx. 5.46 ms)

/fx (approx. 7.82 ms)

/fx (approx. 1.37 ms)

/fx (approx. 1.95 ms)

SREL

WAIT

PD75P238

Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)

Data Retention Timing (STOP mode release by RESET)

STOP Mode

Data Retention Mode

STOP Instruction Execution

RESET

Internal Reset Operation

HALT Mode

Operating
Mode

DDDR

SREL

WAIT

STOP Mode

Data Retention Mode

STOP Instruction Execution

HALT Mode

Operating
Mode

DDDR

SREL

WAIT

Standby Release Signal
(Interrupt Request)

PD75P238

DC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

IH1

Except X1 and X2

0.7 V

IH2

X1, X2

0.5

IL1

Except X1 and X2

0.3 V

IL2

X1, X2

0.4

Input leakage
current

Output voltage
high

Output voltage
low

supply current

MD0 = V

, MDI =V

Note

1. V

, including overshoot, should not exceed +13.5 V.

2. V

should be applied before V

and cut after V

AC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V) (1/2)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Address setup time*2
(to MD0

)

MD1 setup time (to MD0

)

M1S

OES

Data setup time (to MD0

)

Address hold time*2
(from MD0

)

Data hold time
(from MD0

)

Data output float delay
time from MD0

setup time (to MD3

)

VPS

setup time (to MD3

)

VDS

VCS

Initial program pulse widths

0.95

1.0

1.05

Additional program pulse
widths

MD0 setup time (to MD1

)

MOS

CES

Data output delay time
from MD0

* 1.

The corresponding

PD27C256 symbol.

Internal address signal is incremented by one on the rise of fourth X1 input and is not connected to the

pin.

Input voltage
high

Input voltage
low

= V

or V

= 1 mA

1.0

= 1.6 mA

0.4

130

OPW

0.95

21.0

MD0 = MD1 = V

PD75P238

AC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V) (2/2)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

MD1 hold time

(from MD0

)

M1H

+ t

M1R

MD1 recovered time

(to MD0

)

Program counter reset time

PCR

X1 input high and low level
widths

X1 input frequency

4.19

MHz

Initial mode set time

MD3 setup time (to MD1

)

M3S

MD3 hold time
(from MD1

)

MD3 setup time (to MD0

)

M3SR

When reading program memory

Data output delay time from
address*2

Data output hold time from
address*2

MD3 hold time
(from MD0

)

Data output float delay time
from MD3

* 1.

The corresponding

PD27C256 symbol.

Internal address signal is incremented by one on the rise of fourth X1 input and is not connected to the

pin.

M1H

OEH

M1R

, t

0.125

M3H

HAD

When reading program memory

130

DAD

ACC

When reading program memory

M3HR

When reading program memory

DFR

When reading program memory

PD75P238

Read Timing of Program Memory

Write Timing of Program Memory

P40 to P43
P50 to P53

+ 1

MD0

MD1

MD2

MD3

VPS

VDS

DAD

HAD

Output Data

PCR

M3SR

M3HR

DFR

VPS

VDS

+ 1

P40 to P43
P50 to P53

Input Data

Output
Data

Input Data

OPW

MOS

M1R

M1H

M1S

PCR

M3S

M3H

MD0

MD1

MD2

MD3

PD75P238

PACKAGE INFORMATION

94 PIN PLASTIC QFP ( 20)

detail of lead end

5°±5°

S94GJ-80-5BG-2

ITEM

MILLIMETERS

INCHES

23.2±0.4

20.0±0.2

0.8

1.6

0.8

20.0±0.2

0.913

0.063

0.031

0.014

0.787

NOTE

0.8±0.2

1.6±0.2

0.15

0.35±0.10

0.031

0.063±0.008

Each lead centerline is located within
0.15 mm (0.006 inch) of its true position
(T.P.) at maximum material condition.

0.006

0.063

0.787

0.8 (T.P.)

0.031 (T.P.)

0.15

0.006

0.913

23.2±0.4

1.6

0.12

0.005

3.7

0.146

+0.009

0.008

+0.009

0.008

0.1±0.1

0.004±0.004

4.0 MAX.

0.158 MAX.

+0.10

0.05

+0.017

0.016

+0.017

0.016

+0.004

0.005

+0.004

0.003

+0.009

0.008

PD75P238

X94KW-80A-1

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.

20.0±0.4

18.0

20.0±0.4

1.94

2.14

4.064 MAX.

0.51±0.10

0.08

0.8 (T.P.)

1.0±0.2

C 1.0

1.6

R 1.75

11.5

0.75±0.2

0.787

0.709

0.787

0.076

0.084

0.160 MAX.

0.020±0.004

0.003

0.031 (T.P.)

0.039

C 0.039

0.063

0.069

0.453

0.030

+0.017

0.016

+0.009

0.008

+0.008

0.009

94 PIN CERAMIC WQFN

+0.017

0.016

PD75P238

RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended in the table below.

For details of recommended soldering conditions, refer to the information document "Surface Mount Technol-

ogy Manual" (IEI-1207).

For soldering methods and conditions other than those recommended below, contact our salesman.

Table 8-1 Surface Mount Type Soldering Conditions

PD75P238GJ-

×××

-5BG : 94-pin plastic QFP (

20 mm)

Infrared reflow

VPS

Pin part heating

Soldering Method

Soldering Conditions

IR30-107-1

VP15-107-1

Recommended

Condition

Symbol

Package peak temperature: 230

C, Duration: 30 sec. max. (at 210

C or above);

Number of times: Once, Time limit: 7 days* (125

C prebaking requires 10 hours

thereafter)

Package peak temperature: 215

C, Duration: 40 sec. max. (at 200

C or above);

Number of times: Once, Time limit: 7 days* (125

C prebaking requires 10 hours

thereafter)

Pin part temperature: 300

C max.; Duration: 3 sec. max., (per device side)

For the storage period after dry-pack decapsulation, storage conditions are max. 25

C, 65% RH.

Note Use of more than one soldering method should be avoided (except in the case of pin part heating).

PD75P238

APPENDIX A. DEVELOPMENT TOOLS

The following support tools are available for system development using the

PD75P238.

IE-75000-R*1

IE-75001-R

IE-75000-R-EM*2

EP-75238GJ-R

EV-9200G-94

PG-1500

PA-75P238GJ

PA-75P238KF

IE control program

PG-1500 controller

RA75X relocatable assembler

Soft

war

Hardware

IE-75000-R/IE-75001-R emulation board

PD75P238 emulation probe

94-pin conversion socket EV-9200G-94 is provided

PROM programmer

PG-1500 connected with

PD75P238GJ PROM program adapter

PG-1500 connected with

PD75P238KF PROM program adapter

75X series in-circuit emulator

Host machine

PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)

IBM PC/ATTM (PC DOSTM Ver.3.1)

* 1.

Maintenance product

Not incorporated in IE-75001-R

The task swap function, which is provided with Ver.5.00/5.00A. is not available with this software.

Remarks

For development tools manufactured by a third party, see the "75X Series Selection Guide" (IF-151).

PD75P238

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

Document No.

User's Manual

Instruction Application Table

75X Series Selection Guide

Development Tools Related Documents

Document Name

Document No.

IE-75000-R/IE-75001-R User's Manual

IE-75000-R-EM User's Manual

EP-75238GJ-R User's Manual

PG-1500 User's Manual

RA75X Assembler Package User's Manual

Operation Volume

Language Volume

PG-1500 Controller User's Manual

Other Documents

Document Name

Document No.

Package Manual

Surface Mount Technology Manual

Quality Grade on NEC Semiconductor Devices

NEC Semiconductor Device Reliability & Quality Control

Electrostatic Discharge (ESD) Test

Semiconductor Devices Quality Guarantee Guide

Microcomputer Related Products Guide Other Manufactures Volume

Note

The contents of the above related documents are subjected to change without notice. The latest documents

should be used for design, etc.

Hardware

Software

PD75P238

[MEMO]

FIP is a trademark of NEC Corporation.

MS-DOS is a trademark of MicroSoft Corporation.

PC DOS, PC/AT are trademarks of IBM Corporation.

M4 92.6

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights

or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear

reactor control systems and life support systems. If customers intend to use NEC devices for above applications

or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact

our sales people in advance.

Application examples recommended by NEC Corporation

Standard :

Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime systems, etc.

Document Outline

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Document Outline

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