MOS INTEGRATED CIRCUIT

PD75P116

4-BIT SINGLE-CHIP MICROCOMPUTER

DATA SHEET

Document No.

IC-3358

(O. D. No.

IC-7599A)

Date Published February 1994 P
Printed in Japan

The mark 5 shows major revised points.

DESCRIPTION

The

PD75P116 is a version of the

PD75116 in which the on-chip mask ROM is replaced by one-time PROM

which can be written to once only.

Since the

PD75P116 is capable of program write by a user, it is suitable for evaluation in system develop-

ment and limited production.

Detailed functional descriptions are shown in the following User's Manual. Be sure to read for design

purposes.

PD751

××

Series

User's Manual : IEM-922

FEATURES

PD75116 compatible

Program memory (PROM) capacitance : 16256

8 bits

Data memory (RAM) capacitance

: 512

4 bits

Single power supply 5 V

10%

The information in this document is subject to change without notice.

ORDERING INFORMATION

Ordering Code

Package

Quality Grade

PD75P116CW

64-pin plastic shrink DIP (750 mil)

Standard

PD75P116GF-3BE

64-pin plastic QFP (14

20 mm)

Standard

Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

Note

There are no on-chip pull-up resistor and power-on reset function by means of a mask option.

PD75P116

PIN CONFIGURATION (TOP VIEW)

64-pin plastic shrink DIP (750 mil)

P13/INT3

P12/INT2

P11/INT1

P10/INT0

PTH03

PTH02

PTH01

PTH00

TI0

TI1

P23

P22/PCL

P21/PTO1

P20/PTO0

P03/SI

P02/SO

P01/SCK

P00/INT4

P123

P122

P121

P120

P133

P132

P131

P130

P143

P142

P141

P140

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P90
P91
P92
P93
P80
P81
P82
P83
P70
P71
P72
P73
P60
P61
P62
P63
X1
X2
RESET
P50
P51
P52
P53
P40
P41
P42
P43
P30/MD0
P31/MD1
P32/MD2
P33/MD3

PD75P116CW

PD75P116

64-pin plastic QFP (14

20 mm)

SCK

: Serial Clock

: Serial Output

: Serial Input

PTO0, PTO1

: Programmable Timer Output

PCL

: Clock Output

PTH00 to PTH03 : Programmable Threshold Input

INT0, INT1, INT4 : External Vectored Interrupt Input

INT2, INT3

: External Test Input

TI0, TI1

: Timer Input

X1, X2

: Clock Oscillation

RESET

: Reset

: No Connection

: Positive Power Supply

: Ground

: Programming Power Supply

MD0 to MD3

: Mode Selection

Pin Name

P00 to P03

: Port 0

P10 to P13

: Port 1

P20 to P23

: Port 2

P30 to P33

: Port 3

P40 to P43

: Port 4

P50 to P53

: Port 5

P60 to P63

: Port 6

P70 to P73

: Port 7

P80 to P83

: Port 8

P90 to P93

: Port 9

P120 to P123 : Port 12

P130 to P133 : Port 13

P140 to P143 : Port 14

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36

20 21 22 23 24 25 26 27 28 29 30 31 32

P81

P80

P93

P92

P91

P90

P13/INT3

P12/INT2

P11/INT1

P10/INT0

PTH03

PTH02

64 636261605958575655545352

P42

P43

P30/MD0

P31/MD1

P32/MD2

P140

P141

P142

P143

P130

X2
X1

P41
P40
P53
P52
P51
P50

RESET

P63
P62
P61
P60
P73
P72
P71
P70
P83
P82

17
18
19

P131
P132
P133
P120
P121
P122
P123
P00/INT4
P01/SCK
P02/SO
P03/SI
P20/PTO0
P21/PTO1
P22/PCL
P23
T11
T10
PTH00
PTH01

35
34
33

P33/MD3

PD75P116GF-3BE

PD75P116

OVERVIEW OF FUNCTIONS

ROM

RAM

Description

0.95

s, 1.91

s, 15.3

s (4.19 MHz operation)

3-stage switching capability

16256

512

4 bits

4 banks (memory mapping)

3 types of accumulators corresponding to bit length of manipulated data

· 1-bit accumulator (CY),

4-bit accumulator (A),

8-bit accumulator (XA)

Total 58

· CMOS input pins

: 10

· CMOS input/output pins (LED direct drive capability)

: 32

· Middle-high voltage N-ch open-drain input/output pins

(LED direct drive capability)

: 12

· Comparator input pins (4-bit precision)

: 4

· 8-bit timer/event counter

· 8-bit basic interval timer (watchdog timer applicable)

· 8 bits

· LSB-first/MSB-first switchable

· Two transfer modes (transmit-receive/receive-only mode)

External : 3, internal : 4

External : 2

· STOP/HALT mode

· Various bit manipulation instructions (set, reset, test, boolean operation)

· 8-bit data transfer, comparison, operation, increment/decrement instructions

· 1-byte relative branch instruction

· GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1

byte

40 to +85

5 V

10 %

· Bit manipulation memory (bit sequential buffer : 16 bits) on-chip

· 64-pin plastic shrink DIP (750 mil)

· 64-pin plastic QFP (14

20mm)

Item

Basic instructions

Minimum instruction

execution time

Internal memory

General register

Accumulator

Input/output port

Timer/counter

Serial interface

Vectored interrupt

Test input

Standby

Instruction set

Operating temperature range

Operating voltage

Others

Package

PD75P116

ORT 0

PORT 1

P00-P03

P10-P13

PORT 3

PORT 4

PORT 5

PORT 6

PORT 2

P20-P23

P30-P33
/MD0-MD3

P40-P43

P50-P53

P60-P63

PORT 7

P70-P73

SP(8)

BANK

GENERAL REG.

RAM DATA

MEMORY

512

4 BITS

DECODE

AND

CONTROL

ALU

PROGRAM
COUNTER (14)

PROM

PROGRAM

MEMORY

16256

8 BITS

RESET

STAND BY
CONTROL

CPU CLOCK

CLOCK
GENERATOR

CLOCK
DIVIDER

CLOCK
OUTPUT
CONTROL

PCL/P22

/ 2

BASIC
INTERVAL
TIMER

INTER-
RUPT
CONTROL

INTT1

INTBT

PORT 14

P140-P143

PORT 12

P120-P123

TIMER/EVENT
COUNTER

INTT0

TI0

PTO0/P20

TIMER/EVENT
COUNTER

TI1

PTO1/P21

SERIAL
INTERFACE

INTSIO

SCK/P01

SO/P02

SI/P03

PROGRAM-
MABLE
THRESHOLD
PORT #0

PTH00-PTH03

INT4/P00

INT2/P12

INT1/P11

INT0/P10

INT3/P13

PORT 13

P130-P133

PORT 9

P90-P93

PORT 8

P80-P83

BIT SEQ.
BUFFER
(16)

BLOCK DIAGRAM

PD75P116

CONTENTS

PIN FUNCTIONS ....................................................................................................................................

1.1

PORT PINS .....................................................................................................................................................

1.2

OTHER PINS ...................................................................................................................................................

1.3

PIN INPUT/OUTPUT CIRCUITS ...................................................................................................................

1.4

RECOMMENDED CONNECTION OF

PD75P116 UNUSED PINS ...........................................................

1.5

NOTES ON USING P00/INT4 PIN AND RESET PIN ..................................................................................

DIFFERENCES BETWEEN

PD75P116 AND

PD75116 ...................................................................... 11

PROM (PROGRAM MEMORY) WRITE AND VERIFY .......................................................................... 12

3.1

PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ...................................................................

3.2

PROGRAM MEMORY WRITE PROCEDURE ................................................................................................

3.3

PROGRAM MEMORY READ PROCEDURE .................................................................................................

ELECTRICAL SPECIFICATIONS ............................................................................................................ 15

PACKAGE INFORMATION .................................................................................................................... 26

RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 28

APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 29

APPENDIX B. RELATED DOCUMENTATION ............................................................................................ 30

PD75P116

Function

4-bit input port (PORT 0).

4-bit input port (PORT 1).

4-bit input/output port (PORT 2).

Programmable 4-bit input/output port (PORT 3).
Input/output can be specified bit-wise.

4-bit input/output port (PORT 4).
Data input/output pin for program memory
(PROM) write/verify (low-order 4 bits).

4-bit input/output port (PORT 5).
Data input/output pin for program memory
(PROM) write/verify (high-order 4 bits).

Programmable 4-bit input/output port (PORT 6).
Input/output can be specified bit-wise.

4-bit input/output port (PORT 7).

4-bit input/output port (PORT 8).

4-bit input/output port (PORT 9).

N-ch open-drain 4-bit input/output port (PORT
12).
+12 V withstand voltage.

N-ch open-drain 4-bit input/output port (PORT
13).
+12 V withstand voltage.

N-ch open-drain 4-bit input/output port (PORT
14).
+12 V withstand voltage.

PIN FUNCTIONS

1.1

PORT PINS

Dual-

Function Pin

INT4

SCK

INT0

INT1

INT2

INT3

PTO0

PTO1

PCL

MD0 to MD3

I/O Circuit

Type

M-A

indicates Schmitt-triggered input.

LED direct drive capability

Input/Output

Input

Input/output

Input

Input/output

Pin Name

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30 to P33

P40 to P43

P50 to P53

P60 to P63

P70 to P73

P80 to P83

P90 to P93

P120-P123

P130-P133

P140-P143

8-bit I/O

After Reset

Input

PD75P116

1.2

OTHER PINS

Dual-

Function Pin

P20

P21

P01

P02

P03

P00

P10

P11

P12

P13

P22

P30 to P33

I/O Circuit

Type *1

Pin Name

PTH00 to PTH03

TI0

TI1

PTO0

PTO1

SCK

INT4

INT0

INT1

INT2

INT3

PCL

X1, X2

RESET

MD0 to MD3

Input/Output

Input

Input/output

Input

Input/output

Input

Input/output

Function

Variable threshold voltage 4-bit analog input port.

External event pulse input to timer/event counter.
Or edge detection vectored interrupt input pin, or 1-bit input
is also possible.

Timer/event counter output pin.

Serial clock input/output pin.

Serial data output pin.

Serial data input pin.

Edge detection vector interrupt input pin (detection of both
rising and falling edges).

Edge detection vector interrupt input pin (detection edge
selectable).

Edge detection testable input pin (rising edge detection)

Clock output pin

System clock oscillation crystal/ceramic connection pin.
When an external clock is used, the clock is input to X1 and
the inverted clock is input to X2.

System reset input pin (low-level active).

Mode selection pin for program memory (PROM) write/
verify.

Positive power supply pin. Applies +6 V for write/verify.

GND potential pin.

Program voltage impression pin for program memory (PROM)
write/verify.
Connected to V

directly in normal operation.

Applies +12.5 V for PROM write/verify.

After Reset

Input

indicates Schmitt-triggered input.

The device will not operate correctly unless V

is connected to V

directly in normal use.

PD75P116

1.3

PIN INPUT/OUTPUT CIRCUITS

The input/output circuits of each pin of the

PD75P116 are shown by in abbreviated form.

P-ch

N-ch

P-ch

OUT

N-ch

data

output

disable

IN/OUT

data

output

disable

Type D

Type

IN/OUT

data

output

disable

Type D

IN/OUT

N-ch
(+12 V
Withstand
Voltage)

data

output

disable

Middle-High Voltage Input Buffer

(+12 V Withstand Voltage)

Comparator

REF

(Threshold Voltage)

Type A

Type B

Input/output circuit made up to a Type D push-pull output
and Type B Schmitt-triggered input.

Schmitt-triggered input with hysteresis characteristic

Type D

Push-pull output with high impedance output capability
(P-ch and N-ch both OFF)

Type E

This is an input/output circuit made up of a Type D
push-pull output and Type A input buffer.

Type F

Type M-A

Type N

CMOS specification input buffer

Type B

PD75P116

1.4

RECOMMENDED CONNECTION OF

PD75P116 UNUSED PINS

PTH00 to PTH03

TI0

TI1

P00

P01 to P03

P10 to P13

P20 to P23

P30 to P33

P40 to P43

P50 to P53

P60 to P63

P70 to P73

P80 to P83

P90 to P93

P120 to P123

P130 to P133

P140 to P143

Recommended Connection

Connect to V

or V

Connect to V

or V

Connect to V

Input status

: Connect to V

or V

Output status

: Leave open.

P00/INT4, RESET

1.5

NOTES ON USING P00/INT4 PIN AND RESET PIN

The P00/INT4 and RESET pins have a test mode setting function (for IC test) which tests internal operations of

pin of the

PD75P116 in addition to those functions given in 1.1 and 1.2.

The test mode is set when voltage greater than V

is applied to either pin. Therefore, even during normal

operation, the test mode is engaged when noise greater than V

is added, thus causing interference with normal

operation.

For example, this problem may occur if the P00/INT4 and RESET pins wiring is too long, causing line noise.

To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the

exterior add-on components shown in the Figures below.

Connect a Diode with Low V

(0.3 V max.)

Between the V

and the Pin.

Connect a Capacitor Between

the V

and the Pin.

P00/INT4, RESET

Diode with

low V

PD75P116

DIFFERENCES BETWEEN

PD75P116 AND

PD75116

The

PD75P116 is a product in which the program memory (mask ROM) of the

PD75116 is changed to a user

programmable PROM. Other functions of the

PD75P116 and

PD75116 are virtually the same only with the

differences shown in Table 2-1.

For details of CPU functions and on-chip hardware, see the "

PD75116 User's Manual" (IEM-922).

Table 2-1 Differences between

PD75P116 and

PD75116

Item

PD75P116

PD75116

Program memory

One-time PROM

Mask ROM

0000H-3F7FH

(16256

8 bits)

Data memory

0000H-01FFH

(512

4 bits)

Pull-up resistor (ports 12 to 14)

Mask option

Power-on reset function

Operating voltage range

5 V

10 %

2.7 to 6.0 V

31 pins (SDIP)

Pin function

57 pins (QFP)

33 to 36 pins (SDIP)

P33/MD3 to P30/MD0

P33 to P30

59 to 62 pins (QFP)

Electrical specification

Different consumption current, operating temperature range, etc. Refer to the

electrical specifications parameters for each data sheet for details.

Other

Different noise resistance, noise radiation, etc., due to difference in the size of

circuits and mask layout.

Note

The PROM and ROM products differ in noise resistance and noise radiation. If you are considering

replacement of the PROM products by the mask ROM product in the transition from preproduction to

volume production, this should be thoroughly evaluated with the mask ROM CS product (not ES product).

PD75P116

Function

Voltage application pin for program memory write/verify

(normally V

potential).

Address update clock inputs for program memory write/

verify. Inverse of X1 pin signal is input to X2 pin.

Operating mode selection pin for program memory write/

verify.

8-bit data input/output pins for progrm memory write/

verify.

Supply voltage application pin.

Applies 5 V

10 % in normal operation, and 6 V for

program memory write/verify.

Pin Name

X1, X2

MD0 to MD3

P40 to P43 (low-order 4 bits)

P50 to P53 (high-order 4 bits)

Note

Since the

PD75P116 is a one-time PROM version, UV-ray erasure is not possible.

3.1

PROGRAM MEMORY WRITE/VERIFY OPERATING MODES

The

PD75P116 assumes the program memory write/verify mode is +6 V and +12.5 V are applied respec-

tively to the V

and V

pins. The table below shows the operating modes available by the MD0 to MD3 pin

setting in this mode. The rest of pins are all set at the V

potential by the pull-down resistor.

+12.5 V

+6 V

MD0

MD1

MD2

MD3

Operating Mode

Program memory address zero-clear

Write mode

Verify mode

Program inhibit mode

Operating Mode Setting

: L or H

PROM (PROGRAM MEMORY) WRITE AND VERIFY

The ROM built into the

PD75P116 is a 16256

8-bit PROM. The pins shown in the table below are used to

write/verify this PROM. There is no address input; instead, a method to update the address by the clock input

from the X1 pin is adopted.

PD75P116

Data Input

Write

Verify

Additional
Write

Address
Increment

Repeated X Times

Data Output

+ 1

P40-P43
P50-P53

MD0

MD1

MD2

MD3

3.2

PROGRAM MEMORY WRITE PROCEDURE

The program memory writing procedure is shown below. High-speed write is possible.

(1)

Pull down a pin which is not used to V

via the resistor. A low-level signal is input to the X1 pin.

(2)

Supply +5 V to the V

and V

pins.

(3)

s wait.

(4)

The program memory address 0 clear mode.

(5)

Supply +6 V and +12.5 V respectively to V

and V

(6)

The program inhibit mode.

(7)

Write data in the 1-ms write mode.

(8)

The program inhibit mode.

(9)

The verify mode. If written, proceed to (10); if not written, repeat (7) to (9).

(10) (Number of times written in (7) to (9): X)

1-ms additional write.

(11) The program inhibit mode.

(12) Update (+1) the program memory address by inputting 4 pulses to the X1 pin.

(13) Repeat (7) to (12) up to the last address.

(14) The program memory address 0 clear mode.

(15) Change the V

and V

pins voltage to +5 V.

(16) Power off.

The diagram below shows the procedure of the above (2) to (12).

PD75P116

Data Output

+ 1

P40-P43
P50-P53

MD0

MD1

MD2

MD3

"L"

3.3

PROGRAM MEMORY READ PROCEDURE

The

PD75P116 can read the content of the program memory in the following procedure.

(1)

Pull down a pin which is not used to V

via the resistor. A low-level signal is input to the X1 pin.

(2)

Supply +5 V to the V

and V

pins.

(3)

s wait.

(4)

The program memory address 0 clear mode.

(5)

Supply +6 V and +12.5 V respectively to V

and V

(6)

The program inhibit mode.

(7)

The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at

the period of inputting 4 pulses.

(8)

The program inhibit mode.

(9)

The program memory address 0 clear mode.

(10) Change the V

and V

pins voltage to +5 V.

(11) Power off.

The diagram below shows the procedure of the above (2) to (9).

PD75P116

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25

SYMBOL

TEST CONDITIONS

RATING

UNIT

0.3 to + 7.0

0.3 to 13.5

Except ports 12 to 14

0.3 to V

+ 0.3

Ports 12 to 14

0.3 to +13

0.3 to V

+ 0.3

1 pin

Total pins

Peak value

Effective value

Peak value

100

Effective value

Peak value

100

Effective value

opt

40 to +85

stg

65 to +125

1 pin

Ports 0, 2 to 4,

12 to 14 total

Ports 5 to 9

total

PARAMETER

Supply voltage

Input voltage

Output voltage

Output current high

Output current low

Operating
temperature

Storage
temperature

The power supply impedance (pull-up resistor) should be 50 k

or more when the voltage exceeding

10 V applied to ports 12, 13 and 14.

Effective value should be calculated as follows: [Effective value] = [Peak value]

duty

Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter

or even momentarily. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions which ensure that the absolute maximum ratings are not exceeded.

PD75P116

TYP.

4.19

MAX.

5.0

250

UNIT

MHz

RECOMMENDED

CIRCUIT

PARAMETER

Oscillator

frequency (f

) *1

Oscillation

stabilization time *2

Oscillator

frequency (f

) *1

Oscillation

stabilization time *2

X1 input

frequency (f

) *1

X1 input

high/low level width

, t

)

TEST CONDITIONS

After V

reaches 4.5 V.

After V

reaches 4.5 V.

MIN.

2.0

100

RESONATOR

Ceramic

resonator

Crystal

resonator

External

clock

Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execu-

tion time.

Time required to stabilize oscillation after V

reaches oscillation voltage range MIN. or STOP mode

release.

When the oscillator frequency is 4.19 MHz < f

 5.0MHz, PCC = 0011 should not be selected as

instruction execution time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95

s, with

the result that the specified MIN value of 0.95

s cannot be observed.

Note

When the system clock oscillator is used, the following points should be noted concerning wiring in the

section enclosed by dots, in order to prevent the effects of wiring capacitance, etc.

· Keep the wiring as short as possible.

· Do not cross any other signal lines.

· Keep away from lines in which a high fluctuating current flows.

· Ensure that oscillator capacitor connection points are always at the same potential as V

. Do not

ground in a ground pattern in which a high current flows.

· Do not take a signal from the oscillator.

OSCILLATION CIRCUIT CHARACTERISTICS (Ta = 40 to +85

C, V

= 5 V

10 %)

PD74HCU04

PD75P116

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

IH1

Other than below

0.7V

IH2

Ports 0 & 1, TI0 & 1, RESET

0.8V

IH3

Ports 12 to 14

0.7V

IH4

X1, X2

0.5

IL1

Other than below

0.3V

IL2

Ports 0 & 1, TI0 & 1, RESET

0.2V

IL3

X1, X2

0.4

Output voltage high

= 1 mA

1.0

= 15 mA

Ports 0, 2, to 9

0.55

2.0

Output voltage low

= 10 mA

Ports 12 to 14

0.35

2.0

= 1.6 mA

0.4

LIH1

Other than below

LIH2

X1, X2

LIH3

= 12 V

Ports 12 to 14

LIL1

Except X1 & X2

LIL2

X1, X2

LOH1

OUT

= V

Other than below

LOH2

OUT

= 12 V

Ports 12 to 14

LOL

OUT

= 0 V

DD1

= 5 V

5 % *2

DD2

= 5 V

5 %

500

1500

DD3

STOP mode, V

= 5 V

5 %

0.5

Input voltage high

Input voltage low

Input leakage

current high

Input leakage

current low

Output leakage

current high

Output leakage

current low

Power supply

current *1

DC CHARACTERISTICS (Ta = 40 to +85

C, V

= 5 V

10 %)

= V

= 0 V

Not including current flowing in comparator.

When processor clock control register (PCC) is set to 0011 operating in high-speed mode.

When PCC is set to 0100 and CPU is halted in HALT mode.

4.19 MHz
Crystal oscillation
C1 = C2 = 22 pF

HALT
mode*3

PD75P116

CAPACITANCE (Ta = 25

C, V

= 0 V)

TEST CONDITIONS

PARAMETER

Input capacitance

Output capacitance

I/O capacitance

SYMBOL

OUT

UNIT

COMPARATOR CHARACTERISTICS (Ta = 40 to +85

C, V

= 5 V

10 %)

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

100

UNIT

TEST CONDITIONS

PTHM7 set to "1"

PARAMETER

Comparison accuracy

Threshold voltage

PTH input voltage

Comparator circuit

current consumption

SYMBOL

ACOMP

IPTH

f = 1 MHz

Unmeasured pins returned to

0 V.

PD75P116

vs. V

Cycle Time t

[

Supply Voltage V

[V]

Operating

Guaranteed

Range

0.5

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

= 4.75 to 5.5 V

0.95

1.1

MHz

TIH

0.48

TIL

KCY

Input

0.8

Output

0.95

Intput

0.4

Output

KCY

/250

SIK

100

KSI

400

KSO

300

RSL

AC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

CPU clock cycle time*
(minimum instruction
execution time = 1 ma-
chine cycle)

TI input frequency

TI input high/low-level

width

SCK cycle time

SCK high/low-level width

SI setup time (to SCK

)

SI hold time (from SCK

)

SO output delay time

from SCK

INT0 to INT4 high/low-
level width

RESET low level width

INTH

INTL

The cycle time of the CPU clock (

) is determined by the oscillator frequency of the connected resonator

and the processor clock control register (PCC).

The graph on the below shows the cycle time t

characteristics against supply voltage V

Relation between Cycle Time and Supply Voltage

Note t

vs. V

characteristics are different from those of the

PD75P108

PD75P116

STOP Instruction Execution

DDDR

Standby Release Signal

(Interrupt Request)

Operating Mode

HALT Mode

STOP Mode

Data Retention Mode

WAIT

SREL

STOP Instruction Execution

DDDR

RESET

Operating Mode

HALT Mode

Internal RESET Operation

STOP Mode

Data Retention Mode

WAIT

SREL

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta

= 40 to

+85

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Data retention supply voltage

DDDR

2.0 5.5 V

Data retention power supply current *1

DDDR

= 2.0 V

0.1

Release signal set time

SREL

Release by RESET

Release by interrupt request

Oscillation stabilization wait time *2

WAIT

Does not include current flowing in the comparator.

The oscillator stabilization wait time is the time during which CPU operation is halted to prevent

unstable operation when oscillation begins.

Depends on the setting of the basic interval timer mode register (BTM) (table below).

BTM3 BTM2 BTM1 BTM0

WAIT Time (Figure in Parentheses is for f

= 4.19 MHz)

(Approx. 250 ms)

(Approx. 31.3 ms)

(Approx. 7.82 ms)

(Approx. 1.95 ms)

Data Retention Timing (STOP Mode Release by RESET)

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

PD75P116

DC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

PARAMETER

Input voltage high

Input voltage low

Input leakage current

Output voltage high

Output voltage low

supply current

SYMBOL

IH1

IH2

IL1

IL2

UNIT

MAX.

0.3 V

0.4

TEST CONDITIONS

Except X1 & X2

X1, X2

Except X1 & X2

X1, X2

= V

or V

= 1 mA

= 1.6 mA

MD0 = V

, MD1 = V

TYP.

MIN.

0.7V

0.5

1.0

Note 1.

Ensure that V

does not reach +13.5 V or above including overshot.

Ensure that V

is applied before V

and cut off after V

PD75P116

AC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

PARAMETER

Address setup time *2 (to MD0

)

MD1 setup time (to MD0

)

Data setup time (to MD0

)

Address hold time *2 (from MD0

)

Data hold time (from MD0

)

Data output float delay time from MD0

setup time (to MD3

)

setup time (to MD3

)

Initial program pulse width

Additional program pulse width

MD0 setup time (to MD1

)

Data output delay time from MD0

MD1 hold time (from MD0

)

MD1 recovery time (from MD0

)

Program counter reset time

X1 input high-/low-level width

X1 input frequency

Initial mode setting time

MD3 setup time (to MD1

)

MD3 hold time (from MD1

)

MD3 setup time (to MD0

)

Data output delay time from address *2

Data output hold time from address *2

MD3 hold time (from MD0

)

Data output float delay time from MD3

UNIT

MHz

MAX.

130

1.05

21.0

4.19

130

TYP.

1.0

MIN.

0.95

0.125

OES

VPS

VCS

OPW

CES

OEH

ACC

Corresponding to

PD27C256 symbol.

Internal address signal is incremented by 1 on rise of 4th X1 input, and is not connected to a pin.

TEST CONDITIONS

MD0 = MD1 = V

M1H

+ t

M1R

In program memory read

SYMBOL

M1S

VPS

VDS

OPW

MOS

M1H

M1R

PCR

, t

M3S

M3H

M3SR

DAD

HAD

M3HR

DFR

PD75P116

Program Memory Write Timing

Program Memory Read Timing

M1H

MIS

M3S

PCR

M1R

MOS

M3H

VDS

OPW

+ 1

P40-P43
P50-P53

MD0

MD1

MD2

MD3

Data Input

Data Output

Data Input

VPS

DFR

M3HR

DAD

HAD

PCR

VDS

Data Output

M3SR

+ 1

P40-P43
P50-P53

MD0

MD1

MD2

MD3

VPS

"L"

PD75P116

PACKAGE INFORMATION

F
D

NOTE

Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

P64C-70-750A,C-1

ITEM MILLIMETERS

INCHES

58.68 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

1.78 MAX.

0.17

0.25

19.05 (T.P.)

5.08 MAX.

17.0

0~15°

0.50±0.10

0.9 MIN.

2.311 MAX.

0.070 MAX.

0.020

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.010

0.007

0~15°

+0.004

0.003

0.070 (T.P.)

Item "K" to center of leads when formed parallel.

+0.10

0.05

+0.004

0.005

64 PIN PLASTIC SHRINK DIP (750 mil)

PD75P116

64 PIN PLASTIC QFP (14

20)

P64GF-100-3B8,3BE,3BR-2

ITEM

MILLIMETERS

INCHES

23.6±0.4

20.0±0.2

14.0±0.2

0.929±0.016

0.795

0.551

17.6±0.4

0.693±0.016

1.0

0.039

1.0

0.039

0.40±0.10

0.016

0.20

0.008

1.0 (T.P.)

0.039 (T.P)

1.8±0.2

0.071

0.8±0.2

0.031

0.15

0.006

0.10

0.004

2.7

0.106

0.1±0.1

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

+0.008

0.009

+0.009

0.008

+0.004

0.005

+0.008

0.009

+0.009

0.008

+0.004

0.003

NOTE

Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.

detail of lead end

+0.10

0.05

PD75P116

RECOMMENDED SOLDERING CONDITIONS

The

PD75P116 should be mounted under the conditions recommended in the table below.

For details of recommended soldering conditions, refer to the information document "Surface Mount Techno-

logy Manual" (IEI-1207).

For soldering methods and conditions other than those recommended below, contact our salesman.

Table 6-1 Surface Mount Type Soldering Conditions

PD75P116GF-3BE : 64-pin plastic QFP (14

20 mm)

Infrared reflow

Pin part heating

VP15-162-1

WS60-162-1

IR30-162-1

VPS

Recommended

Condition Symbol

Soldering Conditions

Soldering Method

Package peak temperature: 230

C, Duration: 30 sec. max.

(at 210

C or above), Number of times: Once

Time limit: 2 days* (thereafter 16 hours prebaking required

at 125

Package peak temperature: 215

C, Duration: 40 sec. max.

(at 200

C or above), Number of times: Once

Time limit: 2 days* (thereafter 16 hours prebaking required

at 125

Solder bath temperature: 260

C max., Duration: 10 sec. max

Number of times: Once

Preheating temperature: 120

C max. (package surface

temperature),

Time limit: 2 days* (thereafter 16 hours prebaking required

at 125

Pin part temperature: 300

C max., Duration: 3 sec. max.

(per device side)

Wave soldering

For the storage period after dry-pack decapsulation, storage conditions are max. 25

C, 65% 1H.

Note

Use of more than one soldering method should be avoided (except in the case of pin part heating).

Note

Ensure that the application of (wave soldering) is limited to the lead part and no solder touches

the main unit directly.

Table 6-2 Insertion Type Soldering Conditions

PD75P116CW : 64-pin plastic shrink DIP (750 mil)

Soldering Method

Soldering Conditions

Wave Soldering (lead part only)

Pin part heating

Solder bath temperature: 260

C max., Duration: 10sec. max.

Pin part temperature: 260

C max., Duration: 10sec. max.

Notice

A version of this product with improved recommended soldering conditions is available. For details

(improvements such as infrared reflow peak temperature extension (230

C), number of times: twice,

relaxation of time limit, etc.), contact NEC sales personnel.

PD75P116

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD75P116.

Hardware

In-circuit emulator for 75X series

IE-75000-R *1

IE-75001-R

IE-75000-R-EM *2

EP-75108CW-R

EP-75108GF-R

EV-9200G-64

PG-1500

Emulation board for IE-75000-R and IE-75001-R

Emulation probe for

PD75P116CW

PROM programmar

This is a PROM programmar adapter for

PD75P116CW and connects to PG-1500.

This is a PROM programmar adapter for

PD75P116GF and connects to PG-1500.

Emulation probe for

PD75P116GF

A 64-pin conversion socket EV-9200G-64 is provided.

PA-75P116GF

IE control program

PG-1500 controller

RA75X relocatable assembler

Soft

ware

Host machine

· PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A *3)

· IBM PC/ATTM series (PC DOSTM Ver.3.1)

PA-75P108CW

Maintenance product

This is not incorporated in the IE-75001-R.

A task swap function is provided with Ver.5.00/5.00A; however, a task swap function cannot be used

with this software.

Remarks

For development tools manufactured by a third pary, see the "75X Series Selection Guide" (IF-151).

PD75P116

Document Name

Document No.

User's Manual

Instruction Application Table

(I) Introductory Volume

(II) Remote-Controlled Reception Volume

(III) Bar-Code Reader-Volume

(IV) IC Control for MSK Transmission/Reception Volume

75X Series Selection Guide

Application Note

Document Name

Document No.

IE-75000-R/IE-75001-R User's Manual

IE-75000-R-EM User's Manual

EP-75108CW-R User's Manual

EP-75108GF-R User's Manual

PG-1500 User's Manual

Operation Volume

Language Volume

PG-1500 Controller User's Manual

Hardware

Soft

ware

RA75X Assembler Package User's Manual

Document Name

Document No.

Package Manual

Surface Mount Technology Manual

Quality Grade on NEC Semiconductor Devices

NEC Semiconductor Device Reliability Quality Control

Electrostatic Discharge (ESD) Test

Semiconductor Device Quality Guarantee Guide

Microcomputer Related Product Guide Other Manufacturer Volume

Note

The above related documents may be changed without notice. Be sure to use the latest documents for

design purposes.

APPENDIX B. RELATED DOCUMENTATION

List of Device-Related Documents

List of Development Tool Related Documents

Other Documents

[MEMO]

PD75P108B

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights

or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear

reactor control systems and life support systems. If customers intend to use NEC devices for above applications

or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact

our sales people in advance.

Application examples recommended by NEC Corporation

Standard :

Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime systems, etc.

M4 92.6

MS-DOS is a trademark of Microsoft Corporation.

PC DOS and PC/AT are trademarks of IBM Corporation.

Document Outline

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Document Outline

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