Document No.
IC-2913C
(O. D. No.
IC-8082D)
Date Published January 1994 P
Printed in Japan
NEC Corporation 1991
The information in this document is subject to change without notice.
DESCRIPTION
The
PD75308B is a 75X Series 4-bit single-chip microcomputer capable of the same data processing as an
8-bit microcomputer.
It is a low voltage operation version of the
PD75308 with on-chip LCD controller/driver. Operation at an
ultra-low voltage of 2.0 V is possible. An ultra small-sized plastic QFP (12
12 mm) is also provided and it is
perfect for small-sized set that uses an LCD panel.
Functions, etc., are described in detail in the User's Manual. Please be sure to read this manual when
carrying out design work.
PD75308 User's Manual: IEM-5016
FEATURES
Ultra-low-voltage operation possible: V
DD
= 2.0 to 6.0 V
Can be driven by two 1.5 V manganese batteries.
On-chip memory
Program memory (ROM) : 8064
8 bit (
PD75308B)
: 6016
8 bit (
PD75306B)
: 4096
8 bit (
PD75304B)
Data memory (RAM)
: 512
4 bit
Instruction execution time adjustment function convenient in high-speed operation and power saving
0.95
s, 1.91
s, 15.3
s (4.19 MHz operation)
122
s (32.768 kHz operation)
Built-in programmable LCD controller/driver
LCD drive voltage: 2.0 V to V
DD
An ultra small-sized plastic QFP (12
12 mm) is provided.
Suitable for small-sized set, such as a camera.
On-chip PROM products available
On-chip one-time PROM products :
PD75P308, 75P316A
On-chip EPROM products
:
PD75P308, 75P316B
APPLICATIONS
Remote control, integrated camera type VCR, camera, gas meter, etc.
Unless there are any particular functional differences, the
PD75308B is described in this document as a
representative product.
The mark 5 shows major revised points.
4-BIT SINGLE-CHIP MICROCOMPUTER
PD75304B,75306B,75308B
MOS INTEGRATED CIRCUIT
DATA SHEET
2
PD75304B,75306B,75308B
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
PD75304BGC-
-3B9
80-pin plastic QFP (
s
s
14 mm)
Standard
PD75304BGF-
-3B9
80-pin plastic QFP (14
20 mm)
Standard
PD75304BGK-
-BE9
80-pin plastic TQFP(fine pitch)(
s
s
12 mm)
Standard
PD75306BGC-
-3B9
80-pin plastic QFP (
s
s
14 mm)
Standard
PD75306BGF-
-3B9
80-pin plastic QFP (14
20 mm)
Standard
PD75306BGK-
-BE9
80-pin plastic TQFP(fine pitch)(
s
s
12 mm))
Standard
PD75308BGC-
-3B9
80-pin plastic QFP (
s
s
14 mm)
Standard
PD75308BGF-
-3B9
80-pin plastic QFP (14
20 mm)
Standard
PD75308BGK-
-BE9
80-pin plastic TQFP(fine pitch)(
s
s
12 mm)
Standard
Remarks
is the ROM code number.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
PD75304B,75306B,75308B
3
Function
41
0.95
s, 1.91
s, 15.3
s (main system clock: 4.19 MHz operation)
122
s (subsystem clock: 32.768 kHz operation)
8064
8 bits (
PD75308B), 6016
8 bits (
PD75306B), 4096
8 bits (
PD75304B)
512
4 bits
4-bit manipulation: 8 (B, C, D, E, H, L, X, A)
8-bit manipulation: 4 (BC, DE, HL, XA)
Bit accumulator (CY)
4-bit accumulator (A)
8-bit accumulator (XA)
Various bit manipulation instructions
Efficient 4-bit data manipulation instructions
8-bit data transfer instructions
GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1
byte
Number of segments selection: 24/28/32 segments (4/8 can be switched at bit
port output.)
Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty
LCD drive division resistor can be incorporated by mask option
V
DD
= 2.0 to 6.0 V
8-bit timer/event counter
Clock source: 4 stages
Event count possible
8-bit basic interval timer
Standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms
(4.19 MHz operation)
Watchdog timer application possible
FUNCTION OUTLINE (1/2)
Item
Number of basic instructions
Instruction cycle
On-chip memory
General register
Accumulators
Instruction set
I/O lines
LCD controller/driver
Supply voltage range
Timer
8
CMOS input
Pull-up by software possible : 23
16
CMOS input/output
40
8
CMOS output
Used with segment pin
8
10 V withstand voltage, pull-up by mask option
possible : 8
3 channels
ROM
RAM
N-ch open-drain
input/output
4
PD75304B,75306B,75308B
FUNCTION OUTLINE (2/2)
Function
Watch timer
0.5 seconds time interval generation
Count clock source: Main system clock and subsystem clock
switchable
Fast watch mode (3.9 ms time interval generation)
Buzzer output possible (2 kHz)
Three modes application possible
3-wire serial I/O mode
2-wire serial I/O mode
SBI mode
LSB top/MSB top switchable
Special bit manipulation memory: 16 bits
Perfect for remote control application
Timer/event counter output (PTO0): Arbitrary frequency square wave output
Clock output (PCL):
, 524, 262, 65.5 kHz (4.19 MHz operation)
Buzzer output (BUZ): 2 kHz (4.19 MHz or 32.768 kHz operation)
External: 3
Internal: 3
External: 1
Internal: 1
Main system clock oscillation ceramic/crystal oscillation circuit: 4.194304 MHz
Subsystem clock oscillation crystal oscillation circuit: 32.768 kHz
STOP/HALT mode
80-pin plastic QFP (14
20 mm)
80-pin plastic QFP (
s
s
14 mm)
80-pin plastic TQFP (fine pitch) (
s
s
12 mm)
Item
Timer
8-bit serial interface
Bit sequential buffer
Clock output function
Vectored interrupt
Test input
System clock oscillator
Standby
Package
3 channels
PD75304B,75306B,75308B
5
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW)...............................................................................................
6
2.
BLOCK DIAGRAM............................................................................................................................
8
3. PIN FUNCTIONS ..............................................................................................................................
9
3.1
PORT PINS ..............................................................................................................................................
9
3.2
NON-PORT PINS ..................................................................................................................................... 11
3.3
PIN INPUT/OUTPUT CIRCUITS .............................................................................................................. 13
3.4
RECOMMENDED CONNECTION OF UNUSED PINS ............................................................................. 15
3.5
PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ........................................................... 16
4.
MEMORY CONFIGURATION .......................................................................................................... 16
5.
PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 21
5.1
PORTS ..................................................................................................................................................... 21
5.2
CLOCK GENERATOR ............................................................................................................................... 22
5.3
CLOCK OUTPUT CIRCUIT ....................................................................................................................... 23
5.4
BASIC INTERVAL TIMER ........................................................................................................................ 24
5.5
WATCH TIMER ........................................................................................................................................ 25
5.6
TIMER/EVENT COUNTER ....................................................................................................................... 26
5.7
SERIAL INTERFACE ................................................................................................................................. 28
5.8
LCD CONTROLLER/DRIVER .................................................................................................................... 30
5.9
BIT SEQUENTIAL BUFFER ...................................................................................................................... 32
6.
INTERRUPT FUNCTION ................................................................................................................. 32
7.
STANDBY FUNCTION .................................................................................................................... 34
8.
RESET FUNCTION .......................................................................................................................... 35
9.
INSTRUCTION SET ......................................................................................................................... 37
10. MASK OPTION SELECTION ............................................................................................................ 45
11. ELECTRICAL SPECIFICATIONS ...................................................................................................... 46
12. PACKAGE INFORMATION .............................................................................................................. 64
13. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 67
APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS .............................................................. 70
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 72
APPENDIX C. RELATED DOCUMENTS .............................................................................................. 73
6
PD75304B,75306B,75308B
1. PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
12
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
8079787776 757473 7271 70696867666564636261
60
59
58
57
56
55
54
53
52
51
50
48
47
46
45
44
43
42
41
49
2122232425 262728 2930 31323334353637383940
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
P60/KR0
X2
X1
NC
XT2
XT1
V
DD
P33
P32
P31/SYNC
P30/LCDCL
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
COM0
COM1
COM2
COM3
BIAS
V
LC0
V
LC1
V
LC2
P40
P41
P42
P43
V
SS
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
RESET
P73/KR7
P72/KR6
PD75304BGC-
-3B9
PD75304BGK-
-BE9
PD75306BGC-
-3B9
PD75306BGK-
-BE9
PD75308BGC-
-3B9
PD75308BGK-
-BE9
PD75304B,75306B,75308B
7
P00 to 03
: Port 0
P10 to 13
: Port 1
P20 to 23
: Port 2
P30 to 33
: Port 3
P40 to 43
: Port 4
P50 to 53
: Port 5
P60 to 63
: Port 6
P70 to 73
: Port 7
BP0 to 7
: Bit Port
KR0 to 7
: Key Return
SCK
: Serial Clock
SI
: Serial Input
SO
: Serial Output
SB0,1
: Serial Bus 0, 1
RESET
: Reset Input
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
COM0
COM1
COM2
COM3
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
X2
X1
NC
XT2
XT1
V
DD
P33
P32
P31/SYNC
P30/LCDCL
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
RESET
P73/KR7
P72/KR6
P71/KR5
BIAS
V
LC0
V
LC1
V
LC2
P40
P41
P42
P43
V
SS
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80797877767574737271706968676665
25262728293031323334353637383940
S0 to 31
: Segment Output 0 to 31
COM0 to 3
: Common Output 0 to 3
V
LC0-2
: LCD Power Supply 0 to 2
BIAS
: LCD Power Supply Bias Control
LCDCL
: LCD Clock
SYNC
: LCD Synchronization
TI0
: Timer Input 0
PTO0
: Programmable Timer Output 0
BUZ
: Buzzer Clock
PCL
: Programmable Clock
INT0, 1, 4
: External Vectored Interrupt 0, 1, 4
INT2
: External Test Input 2
X1, 2
: Main System Clock Oscillation 1, 2
XT1, 2
: Subsystem Clock Oscillation 1, 2
NC
: No Connection
PD75304BGF-
-3B9
PD75306BGF-
-3B9
PD75308BGF-
-3B9
8
PD75304B,75306B,75308B
P
ORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
LCD
CONTROL-
LER
/DRIVER
4
4
4
4
4
4
4
4
24
8
4
3
P00-P03
P10-P13
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63
P70-P73
S0-S23
S24/BP0
S31/BP7
COM0COM3
V
LC0
V
LC2
BIAS
LCDCL/P30
SYNC/P31
f
LCD
SP(8)
BANK
GENERAL REG.
DATA
MEMORY
(RAM)
512
4 BITS
DECODE
AND
CONTROL
CY
ALU
PROGRAM
COUNTER *
RESET
V
SS
STAND BY
CONTROL
V
DD
CPU
CLOCK
SYSTEM CLOCK
GENERATOR
SUB
MAIN
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
X2
X1
XT2
XT1
PCL/P22
f
X
/ 2
N
BASIC
INTERVAL
TIMER
TIMER/EVENT
COUNTER
#0
WATCH
TIMER
CLOCKED
SERIAL
INTERFACE
INTER-
RUPT
CONTROL
BIT SEQ.
BUFFER (16)
INTCSI
INTW
f
LCD
INTBT
INTT0
KR0/P60
KR7/P73
INT4/P00
INT2/P12
INT1/P11
INT0/P10
SCK/P01
SO/SB0/P02
SI/SB1/P03
BUZ/P23
TI0/P13
PTO0/P20
8
2. BLOCK DIAGRAM
*
13bits :
PD75306B, 75308B
12bits :
PD75304B
PROGRAM
MEMORY
(ROM)
8064
8BITS
:
PD75308B
6016
8BITS
:
PD75306B
4096
8BITS
:
PD75304B
PD75304B,75306B,75308B
9
3.
PIN FUNCTIONS
3.1
PORT PINS (1/2)
Dual-
Function Pin
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
INT2
TI0
PTO0
--
PCL
BUZ
LCDCL
SYNC
--
--
--
--
I/O Circuit
Type
*1
B
F - A
F - B
M - C
B - C
E - B
E - B
M
M
*
1.
: Schmitt trigger input
2. LED direct drive possible
With noise elimination function
Pin Name
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30 *2
P31
*2
P32 *2
P33 *2
P40 to P43 *2
P50 to P53 *2
Input/Output
Input
Input/output
Input/output
Input/output
Input
Input/output
Input/output
Input/output
Input/output
Function
4-bit input port (PORT 0)
On-chip pull-up resistor can be specified for
P01 to P03 as a 3-bit unit by software.
4-bit input port (PORT 1)
On-chip pull-up resistor can be specified as a
4-bit unit by software.
4-bit input/output port (PORT 2)
On-chip pull-up resistor can be specified as a
4-bit unit by software.
Programmable 4-bit input/output port (PORT 3)
Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified as a
4-bit unit by software.
N-ch open-drain 4-bit input/output port (PORT
4)
On-chip pull-up resistor can be specified bit-
wise (mask option).
Open-drain: 10 V withstand voltage
N-ch open-drain 4-bit input/output port (PORT
5)
On-chip pull-up resistor can be specified bit-
wise (mask option).
Open-drain: 10 V withstand voltage
Input
Input
Input
Input
High level (on-
chip pull-up
resistor) or high-
impedance
High level (on-
chip pull-up
resistor) or high-
impedance
8-bit I/O
After
Reset
10
PD75304B,75306B,75308B
3.1
PORT PINS (2/2)
Dual-
Function Pin
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
S24
S25
S26
S27
S28
S29
S30
S31
*
1.
: Schmitt trigger input
2. BP0 to BP7 select V
LC1
as the input source.
However, the output level depends on BP0 to BP7 and V
LC1
external circuit.
Example
BP0 to BP7 are connected mutually within the
PD75308B. Therefore, the output level of BP0 to BP7
is determined by the value of R
1
, R
2
and R
3
.
PD75308B
ON
ON
V
LC1
R
1
R
3
BP0
BP1
R
2
V
DD
Pin Name
P60
P61
P62
P63
P70
P71
P72
P73
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
Input/Output
Input/output
Input/output
Output
Output
Function
Programmable 4-bit input/output port (PORT 6)
Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified as a
4-bit unit by software.
4-bit input/output port (PORT 7)
On-chip pull-up resistor can be specified as a
4-bit unit by software.
1-bit output port (BIT PORT)
Also used as segment output pin.
8-bit I/O
Input
Input
* 2
I/O Circuit
Type
*1
F - A
F - A
G - C
After
Reset
PD75304B,75306B,75308B
11
XT1
XT2
RESET
NC *5
V
DD
V
SS
Function
External event pulse input pin to timer/event counter
Timer/event counter output pin
Clock output pin
Fixed frequency output pin (for buzzer or system clock
trimming)
Serial clock input/output pin
Serial data output pin
Serial bus input/output pin
Serial data input pin
Serial bus input/output pin
Edge detection vectored interrupt input pin (both rising
edge and falling edge detection effective)
Edge detection vectored
interrupt input pin (detection
edge selectable)
Edge detection testable input
pin (rising edge detection)
Parallel falling edge detection testable input pin
Parallel falling edge detection testable input pin
Segment signal output pin
Segment signal output pin
Common signal output pin
LCD drive power supply pin
On-chip split resistor (mask option)
External split resistor cut output pin
External expansion driver drive clock output pin
External expansion driver synchronization clock output
pin
Main system clock oscillation crystal/ceramic connection
pin. For external clock, the external clock signal is input
to X1 and its opposite phase is input to X2.
Subsystem clock oscillation crystal connection pin. For
external clock, the external clock signal is input to XT1
and XT2 is opened. XT1 can be used as a 1-bit input
(test) pin.
System reset input pin
NO CONNECTION
Positive power supply pin
GND potential pin
Pin Name
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 to KR3
KR4 to KR7
S0 to S23
S24 to S31
COM0 to COM3
V
LC0
to V
LC2
BIAS
LCDCL *4
3.2
NON-PORT PINS
Dual-
Function Pin
P13
P20
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 to P63
P70 to P73
--
BP0 to BP7
--
--
--
P30
P31
--
--
--
--
--
--
--
Clock synchronous
system
Asynchronous
Asynchronous
*
1.
: Schmitt trigger input
2. Display outputs are selected with V
LCX
shown below as the input source.
S0 to S31: V
LC1
, COM0 to COM2: V
LC2
, COM3: V
LC0
However, the level of each display output depends on the display output and V
LCX
external circuit.
Input/Output
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input
Input
Input/output
Input/output
Output
Output
Output
--
Output
Input/output
Input/output
Input
Input
--
Input
--
--
--
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
*2
*2
*2
--
*3
Input
Input
--
--
--
--
--
--
SYNC *4
X1, X2
After
Reset
I/O Circuit
Type
*1
B - C
E - B
E - B
E - B
F - A
F - B
M - C
B
B - C
B - C
F - A
F - A
G - A
G - C
G - B
--
--
E - B
E - B
--
--
B
--
--
--
12
PD75304B,75306B,75308B
*
3. On-chip split resistor ........ Low level
No on-chip split resistor ... High-impedance
4. Pins provided for system expansion. Currently, only used as P30 and P31.
5. If a printed wiring board is shared with the
PD75P316A/75P316B, the NC pin should be connected to
V
DD
.
PD75304B,75306B,75308B
13
3.3
PIN INPUT/OUTPUT CIRCUITS
The input/output circuits of each pin of the
PD75308B are shown by in abbreviated form.
P-ch
V
DD
OUT
N-ch
data
output
disable
Schmitt-Trigger Input with Hysteresis Characteristic
P-ch
V
DD
IN
N-ch
P.U.R.
P-ch
IN/OUT
P.U.R.
enable
data
output
disable
Type D
Type A
P.U.R.:Pull-Up Resistor
V
DD
P.U.R.
P-ch
IN/OUT
P.U.R.
enable
data
output
disable
Type D
Type B
P.U.R.:Pull-Up Resistor
V
DD
CMOS Standard Input Buffer
Push-pull output that can be made high-impedance output
(P-ch and N-ch OFF)
TYPE A (For TYPE E-B)
TYPE D (For TYPE E-B, F-A)
TYPE B
TYPE E-B
TYPE F-A
TYPE B-C
IN
IN
P-ch
P.U.R.
P.U.R.
enable
V
DD
P.U.R. : Pull-Up Resistor
14
PD75304B,75306B,75308B
P-ch
V
LC0
V
LC1
V
LC2
P-ch
N-ch
OUT
SEG
data/Bit Port data
N-ch
V
DD
N-ch
P-ch
OUT
SEG
data
P-ch
V
LC0
V
LC1
V
LC2
N-ch
V
LC0
V
LC1
V
LC2
COM
data
N-ch
P-ch
P-ch
N-ch
OUT
N-ch
P-ch
TYPE F-B
TYPE G-C
TYPE M
TYPE G-A
TYPE G-B
TYPE M-C
P.U.R.
enable
P.U.R.:Pull-Up Resistor
V
DD
IN/OUT
N-ch
data
output
disable
(Mask Option)
Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)
P.U.R.
enable
IN/OUT
P-ch
V
DD
N-ch
data
output
disable
P.U.R.:Pull-Up Resistor
P.U.R.
P.U.R.
IN/OUT
P.U.R.
enable
output
disable
(P)
output
disable
data
output
disable
(N)
V
DD
V
DD
P-ch
N-ch
P-ch
P.U.R.:Pull-Up Resistor
PD75304B,75306B,75308B
15
3.4
RECPMMENDED CONNECTION OF UNUSED PINS
Table 3-1 Connection of Unused Pins
Pin
Recommended Connection
P00/INT4
Connect to V
SS
P01/SCK
P02/SO/SB0
Connect to V
SS
or V
DD
P03/SI/SB1
P10/INT0-P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30/LCDCL
P31/SYNC
P32
P33
P40 to P43
P50 to P53
P60/KR0 to P63/KR3
P70/KR4 to P73/KR7
S0 to S23
S24/BP0 to S31/BP7
Leave open
COM0 to COM3
V
LC0
to V
LC2
Connect to V
SS
BIAS
Connect to V
SS
only when V
LC0
to V
LC2
are all unused; otherwise leave open
XT1
Connect to V
SS
or V
DD
XT2
Leave open
Connect to V
SS
5
Input state
:
Connect to V
SS
or V
DD
Outputstate :
Leave open
16
PD75304B,75306B,75308B
3.5
PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN
In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the
test mode for testing internal
PD75308B operation (for IC testing).
The test mode is set when a voltage greater than V
DD
is applied to either of these pins. Consequently, if
noise exceeding V
DD
is applied during normal operation, the test mode may be entered, making it impossible
for normal operation to continue.
For example, misoperation may result if inter-wiring noise is applied to the P00/INT4 or RESET pin due to
the length of the wiring from these pins, and the pin voltage exceeds V
DD
.
Wiring should therefore be carried out so that inter-wiring noise is suppressed as far as possible. If it is
completely impossible to suppress noise, noise prevention measures should be taken using an external compo-
nent as shown below.
o Diode connected between
P00/INT4 or RESET and V
DD
o Capacitor connected between
P00/INT4 or RESET and V
DD
Diode with
Small V
F
V
DD
V
DD
V
DD
P00/INT4, RESET
V
DD
P00/INT4, RESET
4. MEMORY CONFIGURATION
Program memory (ROM) ... 8064
8 bits (0000H to 1F7FH):
PD75308B
6016
8 bits (0000H to 177FH):
PD75306B
4096
8 bits (0000H to 0FFFH):
PD75304B
0000H to 0001H: Vector table in which the program start address after a reset is written.
0002H to 000BH: Vector table in which program start addresses in case of interrupts are written.
0020H to 007FH: Table area referenced by the GETI instruction.
Data memory
Data area ... 512
4 bits (000H to 1FFH)
Peripheral hardware area ... 128
4 bits (F80H to FFFH)
5
PD75304B,75306B,75308B
17
Fig. 4-1 Program Memory Map
(a)
PD75308B
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1F7FH
7
6
5
0
Address
Internal Reset Start Address (High-Order 5 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 5 Bits)
INT0 Start Address (High-Order 5 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0 Start Address (Low-Order 8 Bits)
INT1 Start Address (High-Order 5 Bits)
INT1 Start Address (Low-Order 8 Bits)
INTCSI Start Address (High-Order 5 Bits)
INTCSI Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 5 Bits)
INTT0 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL !addr
Instruction
Subroutine
Entry Address
BR !addr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
Branch Destination
Address and
Subroutine Entry Address
by GETI Instruction
BRCB
! caddr
Instruction
Branch
Address
18
PD75304B,75306B,75308B
(b)
PD75306B
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
177FH
7
6
5
0
Address
Internal Reset Start Address (High-Order 5 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 5 Bits)
INT0 Start Address (High-Order 5 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0 Start Address (Low-Order 8 Bits)
INT1 Start Address (High-Order 5 Bits)
INT1 Start Address (Low-Order 8 Bits)
INTCSI Start Address (High-Order 5 Bits)
INTCSI Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 5 Bits)
INTT0 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL !addr
Instruction
Subroutine
Entry Address
BR !addr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
Branch Destination
Address and
Subroutine Entry Address
by GETI Instruction
BRCB
! caddr
Instruction
Branch
Address
PD75304B,75306B,75308B
19
(c)
PD75304B
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
MBE
0
0
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
7
6
5
0
Address
Internal Reset Start Address (High-Order 4 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 4 Bits)
INT0 Start Address (High-Order 4 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0 Start Address (Low-Order 8 Bits)
INT1 Start Address (High-Order 4 Bits)
INT1 Start Address (Low-Order 8 Bits)
INTCSI Start Address (High-Order 4 Bits)
INTCSI Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 4 Bits)
INTT0 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
CALL !addr
Instruction
Subroutine
Entry Address
BR !caddr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
Branch Destination
Address and
Subroutine Entry Address
by GETI Instruction
20
PD75304B,75306B,75308B
Fig. 4-2 Data Memory Map
(32
4)
256
4
(248
4)
256
4
(224
4)
128
4
(8
4)
0
1
15
000H
007H
008H
0FFH
100H
1DFH
1E0H
1FFH
F80H
FFFH
General
Register Area
Stack Area
Data Area
Static RAM
(512
4)
Display Data Memory Area
Peripheral Hardware Area
Data Memory
Memory Bank
Not On-Chip
PD75304B,75306B,75308B
21
5.
PERIPHERAL HARDWARE FUNCTIONS
5.1
PORTS
There are four kinds of I/O ports, as follows.
CMOS input (PORT0, 1)
: 8
CMOS input/output (PORT2, 3, 6, 7)
: 16
N-ch open drain (PORT4, 5)
: 8
CMOS output (BP0 to BP7)
: 8
Total
40
Fig. 5-1 Port Functions
Port (Symbol)
Function
Operation/Features
Remarks
Dual function as INT4, SCK, SO/
SB0 & SI/SB1 pins
Dual function as pins INT0 to
INT2 & TI0
Dual function as PTO0, PCL &
BUZ pins
Dual function as pins KR4 to
KR7
Dual function as LCDCL & SYNC
pins
Dual function as pins KR0 to
KR3
Incorporation of pull-up resistor
can be specified bit-wise by
mask option.
Small drive capability.
For CMOS load drive.
PORT 0
PORT 1
PORT 2
PORT 7
PORT 3 *
PORT 6
PORT 4 *
PORT 5 *
BP0 to BP7
4-bit input
4-bit input/output
4-bit input/output
(N-ch open-drain
10 V withstand
voltage)
1-bit output
Always readable or testable irrespective of
dual-function pin operating mode.
Can be set to input or output mode as 4-bit
unit. Ports 6 & 7 can be paired for 8-bit data
input/output.
Can be set to input or output mode bit-wise.
Can be set to input or output mode as 4-bit
unit. Ports 4 & 5 can be paired for 8-bit data
input/output.
Outputs data bit-wise. Switchable by
software with LCD drive segment outputs
S24 to S31.
*
Direct LED drive capability
22
PD75304B,75306B,75308B
5.2
CLOCK GENERATOR
The operation of the clock generator is determined by the processor clock control register (PCC) and system
clock control register (SCC).
There are two kinds of clock, the main system clock and subsystem clock, and the instruction execution time
can be changed.
0.95
s/1.91
s/15.3
s (4.19 MHz main system clock operation)
122
s (32.768 kHz subsystem clock operation)
Fig. 5-1 Clock Generator Block Diagram
Remarks
1.
f
X
= Main system clock frequency
2.
f
XT
= Subsystem clock frequency
3.
PCC: Processor clock control register
4.
SCC: System clock control register
5.
* indicates instruction execution.
6.
One
clock cycle (t
CY
) is one machine cycle. See "AC CHARACTERISTICS" in 11. "ELECTRICAL
SPECIFICATIONS" for details of t
CY
.
5
Subsystem
Clock Oscil-
lation Circuit
XT1
XT2
X1
X2
V
DD
V
DD
f
XT
f
X
LCD Controller/
Driver
Watch Timer
Basic Interval Timer (BT)
Timer/Event Counter
Serial Interface
Watch Timer
LCD Controller/Driver
INT0 Noise Elimination Circuit
Clock Output Circuit
1/8 to 1/4096
Frequency Divider
1/2
Selector
Selector
Frequency
Divider
1/4
CPU
INT0 Noise
Elimination Circuit
Clock Output Circuit
HALT F/F
Wait Release Signal from BT
RESET Signal
Standby Release Signal from
Interrupt Control Circuit
STOP F/F
S
R
Q
PCC2,
PCC3
Clear
Oscil-
lation
Stop
WM. 3
SCC
PCC
4
Internal Bus
Main System
Clock Oscil-
lation Circuit
S
R
Q
PCC0
PCC1
PCC2
PCC3
SCC3
SCC0
HALT *
STOP *
1/16
PD75304B,75306B,75308B
23
Remarks
Consideration is given so that a low amplitude pulse is not output when switching between clock
output enable and disable.
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL pin and is used to supply clock
pulses to remote control outputs or peripheral LSI's.
Clock output (PCL) :
524, 262, 65.5 kHz (at 4.19 MHz operation)
Buzzer output (BUZ): 2 kHz (at 4.19 MHz or 32.768 kHz operation)
The configuration of the clock output circuit is shown below.
Fig. 5-2 Clock Output Circuit Configuration
CLOM3
CLOM1CLOM0
0
Internal Bus
CLOM
P22
Output Latch
PORT2.2
Bit 2 of PMGB
Bit Specified
In Port 2
Input/Output
Mode
Output Buffer
PCL/P22
f
X
/2
3
f
X
/2
4
f
X
/2
6
4
Selector
From Clock
Generator
24
PD75304B,75306B,75308B
5.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions.
It operates as an interval timer which generates reference time interrupts.
It can be applied as a watchdog timer which detects when a program is out of control.
Selects and counts wait times when the standby mode is released.
It reads count contents.
Fig. 5-3 Basic Interval Timer Configuration
Remarks
* indicates instruction execution.
Internal Bus
f
X
/2
5
f
X
/2
7
f
X
/2
12
From Clock
Generator
4
BTM3
BTM2
BTM1
BTM0
BTM
MPX
BT
IRQBT
Set
BT Interrupt
Request Flag
Clear
Clear
Basic Interval Timer
(8-Bit Frequency Divider)
Wait Release
Signal During
Standby Release
8
3
Vectored
Interrupt
Request
Signal
f
X
/2
9
*SET1
PD75304B,75306B,75308B
25
5.5
WATCH TIMER
The
PD75308B incorporates a single watch timer channel. The watch timer has the following functions.
Sets test flags (IRQW) at 0.5 second intervals. The standby mode can be released with IRQW.
0.5 sec. time intervals can be created in either the main system clock or the subsystem clock.
In the fast watch mode, time intervals which are 128 times normal (3.91 ms) can be set, making this
function convenient for program debugging and testing.
A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and
trimming system clock oscillation frequencies.
The frequency divider can be cleared, so this clock can be started at 0 second.
Fig. 5-4 Watch Timer Block Diagram
Remarks
Values in parentheses are when f
X
= 4.194304 MHz and f
XT
= 32.768 kHz.
8
Internal Bus
WM7
0
0
0
WM3 WM2 WM1 WM0
Bit Test Instruction
P23
Output
Latch
Port 2
Input/Output
Mode
PORT2.3
Bit 2 of PMGB
P23/BUZ
Output Buffer
Selector
Frequency Divider
Clear
(2.048 kHz)
f
LCD
2
14
f
W
2
6
f
W
(512 Hz : 1.95 ms)
2
7
f
W
(256 Hz : 3.91 ms)
f
W
(32.768 kHz)
Selector
WM
From
Clock
Generator
16
f
W
128
f
W
(32.768 kHz)
f
XT
(32.768 kHz)
INTW
IRQW
Set Signal
2Hz
0.5 sec
26
PD75304B,75306B,75308B
5.6
TIMER/EVENT COUNTER
The
PD75308B incorporates a single timer/event counter channel. The timer/event counter has the following
functions.
Operates as a programmable interval timer.
Outputs square waves in the desired frequency to the PTO0 pin.
Operates as an event counter.
Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation).
Supplies a serial shift clock to the serial interface circuit.
Count status read function.
PD75304B,75306B,75308B
27
Fig. 5-5 Timer/Event Counter Block Diagram
*
1
SET1: Instruction execution
2
For detail, see Fig. 5-1.
P13/TI0
PORT1.3
Input Buffer
From Clock
Generator
*2
MPX
TM06 TM05 TM04 TM03 TM02
SET1
*1
TM0
Timer Operation Start
CP
Count Register (8)
Clear
8
Comparator (8)
8
8
Modulo Register (8)
8
8
Internal Bus
TMOD0
Match
Reset
TOUT
F/F
TOE0
TO
Enable
Flag
P20
Output
Latch
PORT2.0
Bit 2 of PGMB
Port 2
Input/
Output
Mode
To Serial
Interface
P20/PTO0
Output
Buffer
INTT0
IRQT0
Set Signal
RESET
IRQT0
Clear Signal
T0
28
PD75304B,75306B,75308B
5.7
SERIAL INTERFACE
The
PD75308B incorporates a clocked 8-bit serial interface. The serial interface has the following three
modes.
3-wire serial I/O mode
2-wire serial I/O mode
SBI mode (serial bus interface mode)
PD75304B,75306B,75308B
29
Fig. 5-6 Serial Interface Block Diagram
f
X
/2
3
(From Timer/
Event Counter)
INTCSI
IRQCSI
Set Signal
Serial
Clock
Slector
INTCSI Control
Circuit
RELD
Serial Clock
Counter
Serial Clock
Control Circuit
P01/SCK
P03/SI/SB1
P02/SO/SB0
Selector
8/4
CSIM
Bit
Test
8 8
Internal Bus
8
Slave Address Register (SVA)
Addres Comparator
Shift Register (SIO)
Match
Signal
RELT
Bit Manipulation
CMDT
SO
Latch
SET CLR
Q
D
SBIC
Bit Test
Busy/
Acknowledge
Output Circuit
ACKT
(8)
(8)
(8)
CMDD
ACKD
ACKE
BSYE
Bus Release/
Command/
Acknowledge
Detection Circuit
Selector
f
X
/2
4
f
X
/2
6
TOUT F/F
External
SCK
P01
Output
Latch
30
PD75304B,75306B,75308B
5.8
LCD CONTROLLER/DRIVER
The
PD75308B has an on-chip display controller which generates segment signals and common signals in
accordance with data in display data memory as well as a segment driver and common driver capable of
directly driving the LCD panel.
The configuration of the LCD controller/driver is shown in Fig. 5-7
The functions of the on-chip LCD controller/driver of the
PD75308B are as follows.
Display data memory are read automatically through DMA operations and segment signals and common
signals are generated.
5 different display modes can be selected.
Static
1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
In each of the display modes, 4 types of frame frequency can be selected.
The segment signal output is a maximum of 32 segments (S0 to S31) and 4 common outputs (COM0 to
COM3).
Segment signal outputs (S24 to S27, S28 to S31) are in 4-segment units and they can be switched for use
as output ports (BP0 to BP3, BP4 to BP7).
Split resistors can be built-in for the LCD driver power supply (mask option).
Conformity to various bias methods and LCD driver voltages is possible.
When the display is OFF, the current flowing to the split resistors is cut.
Display data memory not used for the display can be used as ordinary data memory.
Operation by the subsystem clock is also possible.
.
4
PD75304B,75306B,75308B
31
Fig. 5-7 LCD Controller/Driver Block Diagram
8
Port Mode
Register
Group A
Port 3
Output
Latch
Display
Control
Register
4
4
0
1E0H
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
2
3
1E8H
1E9H
1FEH
1FFH
Display Data
Memory
Multi-
plexer
S30/PB6
S24/PB0
S23
S0
Common Driver
COM3 COM2COM1COM0 V
LC2
V
LC1
V
LC0
P31/
SYNC
P30/
LCDCL
f
LCD
0
1
0
1
Segment Driver
Display Mode
Register
Timing
Controller
8
4
1
Selector
LCD Driver Voltage
Control
S31/PB7
32
PD75304B,75306B,75308B
5.9
BIT SEQUENTIAL BUFFER ..... 16 BITS
The bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for
bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for
processing data with long bit lengths bit-wise.
Fig. 5-8 Bit Sequential Buffer Format
Remarks
In pmem.@L addressing, the specified bit corresponding to the L register is moved.
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
L = 0
L = 3
L = 4
DECS L
L = 7
L = 8
INCS L
L = B
L = C
L = F
FC3H
FC2H
FC1H
FC0H
Symbol
Address
Bit
L Register
BSB3
BSB2
BSB1
BSB0
6.
INTERRUPT FUNCTION
The
PD75218has 8 interrupt sources, and prioritized multiple interrupts are possible.
There are also two test sources, of which INT2 is an edge-detected testable input.
The
PD75218 interrupt control circuit has the following functions
Hardware control vectored interrupt function that can control interrupt acceptance by interrupt flag
(IE
) and interrupt master enable flag (IME).
Arbitrary setting of interrupt start address.
Multiple interrupt function with priority specifiable by the interrupt priority selection register (IPS).
Interrupt request flag (IRQ
) test function (interrupt generation confirmation by software possible).
Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag
possible).
PD75304B,75306B,75308B
33
Fig. 6-1 Interrupt Control Circuit Block Diagram
*
Noise elimination circuit
2
1
3
IM2
IM1
IM0
IRQBT
INT4
/P00
INT0
/P10
INT1
/P11
INT2
/P12
KR0/P60
KR7/P73
IRQ4
IRQ0
IRQ1
IRQCSI
IRQT0
IRQW
IRQ2
INT
BT
INTCSI
INTT0
INTW
IM2
IME
IST0
VRQn
Internal Bus
Vector
Table
Address
Generator
Priority Control
Circuit
Standby Release
Signal
Interrupt Enable Flag (IE
XXX
)
Rising Edge
Detection
Circuit
Falling Edge
Detection
Circuit
Edge
Detection
Circuit
Edge
Detection
Circuit
Both Edges
Detection
Circuit
Decoder
Selector
*
34
PD75304B,75306B,75308B
7.
STANDBY FUNCTION
To reduce the power consumption during program wait, the
PD75308B has two standby modes: STOP
mode and HALT mode.
Table 7-1 Operation Status at Standby Mode
STOP Mode
STOP instruction
Only main system clock settable
Only main system clock oscillation
stopped
Stopped
Operable only when external SCK
input selected as serial clock
Operable only when TI0 pin input
specified as count clock
Operable only when f
XT
selected as
count clock
Operable only when f
XT
selected as
LCDCL
INT1, 2, 4: Operable
Only INT0 inoperable
Stopped
Interrupt request signal from operable
hardware enabled by interrupt enable
flag, or RESET input
Setting instruction
System clock at setting
Clock oscillator
Basic interval timer
Serial interface
Timer/event counter
Watch timer
LCD controller
External interrupt
CPU
Release signal
O
peration Status
HALT Mode
HALT instruction
Main system clock or subsystem
clock settable
Only CPU clock
stopped
(oscillation continued)
Operating (IRQBT set at reference time
intervals)*
Operable*
Operable*
Operable
Operable
Interrupt request signal from operable
hardware enabled by interrupt enable
flag, or RESET input
*
In-operable only with main system clock oscillation stopped.
PD75304B,75306B,75308B
35
8.
RESET FUNCTION
The
PD75308B is reset and the hardware is initialized as shown in Table 8-1 by RESET input. The reset
operation timing is shown in Fig. 8-1.
Fig. 8-1 Reset Operation by RESET Input
Wait
(31.3 ms/4.19 MHz)
HALT Mode
Operating Mode
Internal Reset Operation
Operating Mode or Standby
Mode
RESET Input
Table 8-1 Status of Each Hardware after Resetting (1/2)
Hardware
Program counter (PC)
Carry flag (CY)
Skip flag (SK0 to 2)
PSW
Interrupt status flag (IST0)
Bank enable flag (MBE)
Stack pointer (SP)
Data memory (RAM)
General register
(X, A, H, L, D, E, B, C)
Bank selection register (MBS)
*
1. Figures in parentheses apply to the
PD75304B.
2. Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
RESET Input in Standby
Mode
Low-order 5(4)*1 bits of
program memory address
0000H are set in PC12(11)*1
to 8 and the contents of
address 0001H are set in
PC7 to 0.
Held
0
0
Bit 7 of program memory
address 0000H is set in
MBE.
Undefined
Held*2
Held
0
RESET Input during
Operation
Low-order 5(4)*1 bits of
program memory address
0000H are set in
PC12(11)*1 to 8 and the
contents of address 0001H
are set in PC7 to 0.
Undefined
0
0
Bit 7 of program memory
address 0000H is set in
MBE.
Undefined
Undefined
Undefined
0
36
PD75304B,75306B,75308B
Table 8-1 Status of Each Hardware after Resetting (2/2)
RESET Input during
Operation
Hardware
Counter (BT)
Mode register (BTM)
Counter (To)
Modulo register (TMOD0)
Mode Register (TM0)
TOE0, TOUT F/F
Mode register (WM)
Shift register (SIO)
Operating mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Processor clock control register (PCC)
System clock control register (SCC)
Clock output mode register (CLOM)
Display mode register (LCDM)
Display control register (LCDC)
Interrupt request flag (IRQ
)
Interrupt enable flag (IE
)
Interrupt master enable flag (IME)
INT0, 1, 2 mode registers (IM0, 1, 2)
Output buffer
Output latch
I/O mode register (PMGA, B)
Pull-up resistor specification register
(POGA)
RESET Input in Standby
Mode
Undefined
0
0
FFH
0
0,0
0
Held
0
0
Held
0
0
0
0
0
Reset (0)
0
0
0, 0, 0
OFF
Clear (0)
0
0
Held
Undefined
0
0
FFH
0
0,0
0
Undefined
0
0
Undefined
0
0
0
0
0
Reset (0)
0
0
0, 0, 0
OFF
Clear (0)
0
0
Undefined
Basic interval
timer
Timer/event
counter
Watch timer
Serial interface
Clock generator,
clock output
circuit
LCD controller
Interrupt function
Digital port
Bit sequential buffer (BSB0 to 3)
PD75304B,75306B,75308B
37
9.
INSTRUCTION SET
(1) Operand identifier and description
The operand is described in the operand field of each instruction in accordance with the description for the
operand identifier of the instruction. (See the RA75X Assembler Package User's Manual Language Volume
(EEU-730) for details.) When there are multiple elements in the description, one of the elements is selected.
Upper case letters and symbols (+,) are keywords and are described unchanged.
For immediate data, a suitable value or label is described.
Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (See the
PD75308 User's Manual (IEM-5016) for details). However, there are restrictions on the labels for which fmem
and pmem can be used (see the table on the previous page).
Identifier
Description
reg
X, A, B, C, D, E, H, L
regl
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rpl
BC, DE, HL
rp2
BC, DE
rpa
HL, DE, DL
rpal
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem*
8-bit immediate data or label
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
PD75304B
0000H to 0FFFH immediate data or lebel
addr
PD75306B
0000H to 177FH immediate data or lebel
PD75308B
0000H to 1F7FH immediate data or lebel
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT 0 to PORT 7
IE
IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW
MBn
MB0, MB1, MB15
*
Only an even address can be written for mem in the case of 8-bit data processing.
38
PD75304B,75306B,75308B
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register;
C
: C register;
D
: D register;
E
: E register;
H
: H register;
L
: L register;
X
: X register; 4-bit accumulator
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
PORTn
: Portn (n = 0 to 7)
IME
: Interrupt master enable flag
IE
: Interrupt enable flag
MBS
: Memory bank selection register
PCC
: Processor clock control register
: Address, bit delimiter
(
)
: Contents addressed by
H
: Hexadecimal data
PD75304B,75306B,75308B
39
Data memory
addressing
(3) Description of addressing area field symbols
Remarks
1. MB indicates the accessible memory bank.
2. For *2, MB = 0 without regard to MBE and MBS.
3. For *4 and *5, MB = 15 without regard to MBE and MBS.
4. *6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field
S shows the number of machine cycles required when skip is performed by an instruction with skip. The
value of S changes as follows:
No skip ....................................................................................................................................................................... S = 0
When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1
When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction) ............................. S = 2
Note
One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (=t
CY
) of the CPU clock
. Three times can be selected by PCC
setting.
Program memory
addressing
MB = MBE MBS (MBS = 0, 1, 15)
MB = 0
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
PD75304B
addr=0000H to 0FFFH
PD75306B
addr=0000H to 177FH
PD75308B
addr=0000H to 1F7FH
addr = (Current PC) 15 to (Current PC) 1
(Current PC) + 2 to (Current PC) + 16
PD75304B
caddr= 0000H to 0FFFH
PD75306B
caddr= 0000H to 0FFFH (PC
12
=0) or
1000H to 177FH (PC
12
=1)
PD75308B
caddr=0000H to 0FFFH (PC
12
=0) or
1000H to 1F7FH (PC
12
=1)
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
40
PD75304B,75306B,75308B
Stack A
Stack A
Stack B
carry
carry
borrow
Address-
ing Area
Operand
Skip Condition
A, #n4
regl, #n4
XA, #n8
HL, #n8
rp2, #n8
A, @HL
A, @rpal
XA, @HL
@HL, A
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
XA, rp
regl, A
rpl, XA
A, @HL
A, @rpal
XA, @HL
A, mem
XA, mem
A,regl
XA, rp
XA, @PCDE
XA, @PCXA
A, #n4
A, @HL
A, @HL
A, @HL
A, @HL
*1
*2
*1
*1
*1
*3
*3
*3
*3
*1
*2
*1
*3
*3
*1
*1
*1
*1
Note
Instruction Group
Mne-
monic
MOV
XCH
MOVT
ADDS
ADDC
SUBS
SUBC
Operation
Table reference
Transfer
Note
Bytes
Machine
Cycles
A
n4
regl
n4
XA
n8
HL
n8
rp2
n8
A
(HL)
A
(rpal)
XA
(HL)
(HL)
A
(HL)
XA
A
(mem)
XA
(mem)
(mem)
A
(mem)
XA
A
reg
XA
rp
regl
A
rpl
XA
A
(HL)
A
(rpal)
XA
(HL)
A
(mem)
XA
(mem)
A
regl
XA
rp
q
PD75304B
XA
(PC
118
+ DE)
ROM
q
PD75306B, 75308B
XA
(PC
128
+ DE)
ROM
q
PD75304B
XA
(PC
118
+ XA)
ROM
q
PD75306B, 75308B
XA
(PC
128
+ XA)
ROM
A
A + n4
A
A + (HL)
A, CY
A + (HL) + CY
A
A (HL)
A, CY
A (HL) CY
Operation
1
2
2
2
2
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
2
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
2
2
2
1
2
3
3
1 + S
1 + S
1
1 + S
1
PD75304B,75306B,75308B
41
Operand
Operation
Address-
ing Area
Skip Condition
A, #n4
A, @HL
A, #n4
A, @HL
A, #n4
A, @HL
A
A
reg
@HL
mem
reg
reg, #n4
@HL, #n4
A, @HL
A, reg
CY
CY
CY
CY
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
2
1
2
1
2
1
1
2
1
2
2
1
2
2
1
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*3
*1
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
reg = 0
(HL) = 0
(mem) = 0
reg = FH
reg = n4
(HL) = n4
A = (HL)
A = reg
CY = 1
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H + mem.bit) = 0
Note
1. Instruction Group
2. Accumulator operation
3. Increment and decrement
4. Carry flag operation
Mne-
monic
AND
OR
XOR
RORC
NOT
INCS
DECS
SKE
SET1
CLR1
SKT
NOT1
SET1
CLR1
SKT
SKF
Bytes
Machine
Cycles
2
1
2
1
2
1
1
2
1 + S
2 + S
2 + S
1 + S
2 + S
2 + S
1 + S
2 + S
1
1
1 + S
1
2
2
2
2
2
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
A
A
n4
A
A
(HL)
A
A
n4
A
A
(HL)
A
A
n4
A
A
(HL)
CY
A
0
, A
3
CY, A
n1
A
n
A
A
reg
reg + 1
(HL)
(HL) + 1
(mem)
(mem) + 1
reg
reg 1
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if A = reg
CY
1
CY
0
Skip if CY = 1
CY
CY
(mem.bit)
1
(fmem.bit)
1
(pmem
72
+ L
32
.bit (L
10
))
1
(H + mem
30
.bit)
1
(mem.bit)
0
(fmem.bit)
0
(pmem
72
+ L
32
.bit (L
10
))
0
(H + mem
30
.bit)
0
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (pmem
72
+ L
32
.bit (L
10
)) = 1
Skip if (H + mem
30
.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (pmem
72
+ L
32
.bit (L
10
)) = 0
Skip if (H + mem
30
.bit) = 0
Note 2
Note 3
Comparison
Note 4
Memory bit manipulation
Operation
Note
1
42
PD75304B,75306B,75308B
Operation
Skip Condition
Operand
Mne-
monic
Address-
ing Area
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
*6
*7
*8
*6
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
2
2
2
2
2
2
2
2
2
2
2
2
--
3
1
2
3
fmem.bit
pmem.@L
@H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
addr
!addr
$addr
!caddr
!addr
Note
Instruction Group
Note
SKTCLR
AND1
OR1
XOR1
BR
BRCB
CALL
Bytes
Machine
Cycles
2 + S
2 + S
2 + S
2
2
2
2
2
2
2
2
2
--
3
2
2
3
Subroutine stack control
Branch
Memory bit manipulation
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
72
+ L
32
.bit (L
10
)) = 1 and clear
Skip if (H + mem
30
.bit) = 1 and clear
CY
CY
(fmem.bit)
CY
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
CY
(H + mem
3-0
.bit)
CY
CY
(fmem.bit)
CY
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
CY
(H + mem
3-0
.bit)
CY
CY
(fmem.bit)
CY
CY
(pmem
72
+ L
32
.bit (L
10
))
CY
CY
(H + mem
3-0
.bit)
q
PD75304B
PC
110
addr
(The assembler selects the optimum
instruction from among the BRCB !caddr,
and BR $addr instructions.)
q
PD75306B, 75308B
PC
120
addr
(The assembler selects the optimum
instruction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
q
PD75306B, 75308B
PC
120
addr
q
PD75304B
PC
110
addr
q
PD75306B, 75308B
PC
120
addr
q
PD75304B
PC
110
caddr
110
q
PD75306B, 75308B
PC
120
PC
12
+ caddr
110
q
PD75304B
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, 0, 0, 0
PC
110
addr, SP
SP 4
q
PD75306B, 75308B
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, 0, 0, PC
12
PC
120
addr, SP
SP 4
PD75304B,75306B,75308B
43
Operation
Skip Condition
Operand
Mne-
monic
Address-
ing Area
q
PD75304B
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, 0, 0, 0
PC
110
0, faddr, SP
SP 4
q
PD75306B, 75308B
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, 0, 0, PC
12
PC
120
00, faddr, SP
SP 4
q
PD75304B
MBE,
,
,
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
SP
SP + 4
q
PD75306B, 75308B
MBE,
,
, PC
12
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
SP
SP + 4
q
PD75304B
MBE,
,
,
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
SP
SP + 4 the skip unconditionally
q
PD75306B, 75308B
MBE,
,
, PC
12
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
SP
SP + 4 the skip unconditionally
q
PD75304B
MBE,
,
,
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
PSW
(SP + 4) (SP + 5), SP
SP + 6
q
PD75306B, 75308B
MBE,
,
, PC
12
(SP + 1)
PC
110
(SP) (SP + 3) (SP + 2)
PSW
(SP + 4) (SP + 5), SP
SP + 6
(SP 1) (SP 2)
rp, SP
SP 2
(SP 1)
MBS, (SP 2)
0, SP
SP 2
rp
(SP + 1) (SP), SP
SP + 2
MBS
(SP + 1), SP
SP + 2
IME
1
IE
1
IME
0
IE
0
!faddr
*9
2
1
1
1
1
2
1
2
2
2
2
2
rp
BS
rp
BS
IE
IE
Unconditional
Note
1. Instruction Group
2. Interrupt control
Note
1
CALLF
RET
RETS
RETI
PUSH
POP
EI
DI
Note 2
Subroutine stack control
Bytes
Machine
Cycles
2
3
3+S
3
1
2
1
2
2
2
2
2
44
PD75304B,75306B,75308B
Operation
Skip Condition
Operand
Address-
ing Area
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
MBn
taddr
2
2
2
2
2
2
1
2
1
-----------------------------------------------------------------
-----------------------------------------------------------------
-----------------------------
Conforms to
referenced
instruction.
Conforms to
referenced
instruction.
-----------------------------------------------------------------
-----------------------------------------------------------------
-----------------------------
-----------------------------
*
At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance.
*10
Note
1. Instruction Group
2. CPU control
Remarks
The TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table
definition.
Note
1
Mne-
monic
IN*
OUT*
HALT
STOP
NOP
SEL
GETI
Special
Input/output
Note 2
Bytes
Machine
Cycles
2
2
2
2
2
2
1
2
3
A
PORT
n
(n = 07)
XA
PORT
n+1
, PORT
n
(n = 4, 6)
PORT
n
A
(n = 27)
PORT
n+1
, PORT
n
XA
(n =4, 6)
Set HALT Mode (PCC.2
1)
Set STOP Mode (PCC.3
1)
No Operation
MBS
n (n = 0, 1, 15)
q
PD75304B
TBR Instruction
PC
11-0
(taddr)
30
+ (taddr + 1)
TCALL Instruction
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, 0, 0, 0
PC
110
(taddr)
30
(taddr + 1)
SP
SP 4
Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
q
PD75306, 75308BB
TBR Instruction
PC
12-0
(taddr)
40
+ (taddr + 1)
TCALL Instruction
(SP 4) (SP 1) (SP 2)
PC
110
(SP 3)
MBE, 0, 0, PC
12
PC
120
(taddr)
40
(taddr + 1)
SP
SP 4
Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
-----------------------------
PD75304B,75306B,75308B
45
10. MASK OPTION SELECTION
The following pin mask options are available.
Pin Functions
Mask Options
P40 to P43,
q Pull-up resistor incorporated (specifiable bit-wise)
P50 to P53
q No pull-up resistor (specifiable bit-wise)
V
LC0
to V
LC2
,
q LCD drive power supply split resistor incorporated (specifiable as 4-bit unit)
BIAS
q No LCD drive power supply split resistor (specifiable as 4-bit unit)
46
PD75304B,75306B,75308B
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25
C)
PARAMETER
SYMBOL
TEST CONDITIONS
RATING
UNIT
Power supply
voltage
Except ports 4 and 5
0.3 to V
DD
+0.3
V
Input voltage
On-chip pull-up resistor
0.3 to V
DD
+0.3
V
Ports 4 and 5
Opendrain
0.3 to +11
V
Output voltage
0.3 to V
DD
+0.3
V
Output current
One pin
15
mA
high
All pins
30
mA
Peak value
30
mA
One pin
rms
15
mA
Peak value
100
mA
Output current low
Total of ports 0, 2, 3 and 5
rms
60
mA
Peak value
100
mA
Total of ports 4, 6, and 7
rms
60
mA
Operating
temperature
Storage
temperature
*
Rms is calculated using the following expression: [rms] = [peak value]
duty
CAPACITANCE (Ta = 25
C, V
DD
= 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
C
IN
15
pF
Output capacitance
C
OUT
15
pF
I/O capacitance
C
IO
15
pF
V
DD
V
I1
V
12
V
O
I
OH
I
OL
*
T
opt
T
stg
0.3 to +7.0
V
40 to +85
C
65 to +150
C
f = 1 MHz
Unmeasured pins returned to 0 V.
PD75304B,75306B,75308B
47
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
RECOMMENDED
TEST
RESONATOR
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONSTANT
CONDITIONS
Oscillator
frequency (f
x
)*1
After V
DD
reached the
Oscillation
MIN. of the
stabilization time*2
oscillation
voltage
range
Oscillator
frequency (f
x
)*1
V
DD
= 4.5
to 6.0 V
Oscillation
stabilization time*2
30
ms
X1 input
frequency (f
x
)*1
X1 input
high-/low-level
100
500
ns
width (t
XH
, t
XL
)
4
ms
1.0
5.0*3
MHz
1.0
4.19
5.0*3
MHz
1.0
5.0*3
MHz
*
1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the
instruction execution time refer to the AC characteristics.
2. The oscillation stabilization time is necessary for oscillation to stabilize after applying V
DD
or releasing the
STOP mode.
3. When the oscillation frequency is 4.19 MHz < f
X
5.0 MHz, PCC = 0011 should not be selected as the
instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s, and the
specification MIN. value of 0.95
s will not be achieved.
10
ms
Ceramic
resonator*3
Crystal
resonator*3
External
clock
5
X1
X2
C2
C1
V
DD
X1
X2
PD74HCU04
X1
X2
C2
C1
V
DD
48
PD75304B,75306B,75308B
32
32.768
35
kHz
1.0
2
s
XT1
XT2
Leave
Open
10
s
5
15
s
External
clock
Crystal
resonator
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
RECOMMENDED
TEST
MIN.
TYP.
MAX.
UNIT
RESONATOR
PARAMETER
CONSTANT
CONDITIONS
Oscillator
frequency (f
XT
)
V
DD
= 4.5
to 6.0 V
Oscillation
stabilization time*
XT1 input
32
100
kHz
frequency (f
XT
)
XT1 input high-/
low-level width
(t
XTH
,t
XTL
)
*
This is the time required for oscillation to stabilize after V
DD
reaches the MIN. value of the oscillation voltage
range.
Note
When the main system clock and subsystem clock oscillators are used, the following should be noted
concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring
capacitance, etc.
The wiring should be kept as short as possible.
No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.
The oscillator capacitor grounding point should be at the same potential as V
DD
. Do not ground to a
ground pattern carrying a high current.
A signal should not be taken from the oscillator.
The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption
current, and is more prone to misoperation due to noise than the main system clock oscillator. Particu-
lar care is therefore required with the wiring method when the subsystem clock is used.
XT1
XT2
C4
C3
V
DD
R
5
PD75304B,75306B,75308B
49
1.0
V
V
OH1
V
OH2
V
DD
1.0
V
V
DD
2.0
V
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V) (1/2)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IH1
Ports 2 and 3
0.7 V
DD
V
DD
V
V
IH2
Ports 0,1,6,7, RESET
0.8 V
DD
V
DD
V
On-chip pull-up resistor
0.7 V
DD
V
DD
V
V
IH3
Ports 4 and 5
Opendrain
0.7 V
DD
10
V
V
IH4
X1, X2, XT1
V
DD
0.5
V
DD
V
V
IL1
Ports 2, 3, 4 and 5
0
0.3 V
DD
V
V
IL2
Ports 0, 1, 6, 7 RESET
0
0.2 V
DD
V
V
IL3
X1, X2, XT1
0
0.4
V
V
DD
= 4.5 to 6.0 V
Ports 0, 2,3, 6, 7,
I
OH
= 1 mA
BIAS
I
OH
= -100
A
V
DD
0.5
V
V
DD
= 4.5 to 6.0 V
BP0 to BP7
I
OH
= 100
A
(with 2 I
OH
outputs)
I
OH
= 30
A
V
DD
1.0
V
Ports 3, 4 and 5
V
DD
= 4.5 to 6.0 V
0.5
2.0
V
I
OL
= 15 mA
Ports
0, 2, 3, 4, 5, 6 and 7
V
DD
= 4.5 to 6.0 V
V
OL1
I
OL
= 1.6 mA
I
OL
= 400
A
0.5
V
Opendrain
pull-up resistor
1 k
V
DD
= 4.5 to 6.0 V
BP0 to BP7
I
OL
= 100
A
(with 2 I
OL
outputs)
I
OL
= 50
A
1.0
V
I
L1H1
Other than below
3
A
V
IN
= V
DD
I
LIH2
X1, X2, XT1
20
A
Ports 4 and 5
(when opendrain)
Input leakage
I
LIL1
Other than below
3
A
current low
V
IN
= 0 V
I
LIL2
X1, X2, XT1
20
A
Output leakage
I
LOH1
V
OUT
= V
DD
Other than below
3
A
current high
Ports 4 and 5
(when opendrain)
Output leakage
current low
SB0, 1
0.2 V
DD
V
0.4
V
I
LIH3
V
IN
= 10 V
20
A
I
LOH2
V
OUT
= 10 V
20
A
V
OL2
I
LOL
V
OUT
= 0 V
3
A
Input voltage
low
Input voltage
high
Output voltage
high
Output voltage
low
Input leakage
current high
50
PD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V) (2/2)
Ports 4 and 5
V
OUT
= V
DD
2.0 V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Ports 0, 1, 2, 3, 6
V
DD
= 5.0 V
10%
15
40
80
k
R
L1
and 7 (Except P00)
V
IN
= 0 V
V
DD
= 3.0 V
10%
30
300
k
V
DD
= 5.0 V
10%
15
40
70
k
R
L2
V
DD
= 3.0 V
10%
10
60
k
LCD drive voltage
V
LCD
2.0
V
DD
V
LCD split resistor
R
LCD
60
100
150
k
LCD output voltage
deviation*1
V
ODC
I
O
=
5
A
0
0.2
V
(common)
LCD output voltage
deviation
V
ODS
I
O
=
1
A
0
0.2
V
(segment)
V
DD
= 5 V
10%*4
3.0
9
mA
I
DDI
4.19 MHz*3
V
DD
= 3 V
10%*5
0.4
1.2
mA
crystal oscillation
C1 = C2 = 22 pF
HALT
V
DD
= 5 V
10%
600
1800
A
I
DD2
mode
V
DD
= 3 V
10%
180
540
A
I
DD3
V
DD
= 3 V
10%
40
120
A
32 kHz*6
crystal oscillation
HALT
V
DD
= 3 V
10%
mode
V
DD
= 5 V
10%
1
25
A
I
DD5
0.5
15
A
Ta = 25
C
0.5
5
A
*
1. The voltage deviation is the difference between the output voltage and the segment or common output
desired value (V
LCDn
; n= 0, 1, 2).
2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.
3. Including oscillation of the subsystem clock.
4. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-
speed mode.
5. When PCC is set to 0000 and the device is operated in the low-speed mode.
6. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem
clock, with main system clock oscillation stopped.
I
DD4
12
36
A
V
DD
=
3 V
10%
XT1 = 0 V
STOP mode
V
LCD0
= V
LCD
V
LCD1
= V
LCD
2/3
V
LCD2
= V
LCD
1/3
2.7 V
V
LCD
V
DD
On-chip pull-up
resistor
Supply current*2
PD75304B,75306B,75308B
51
t
CY
t
TIH
,
t
TIL
t
INTH
,
t
INTL
t
CY
vs V
DD
(Operating on Main System Clock)
Cycle Time t
CY
[
s]
Supply Voltage V
DD
[V]
0
1
2
3
4
5
6
0.5
1
2
3
4
5
30
64
70
6
Guaranteed
Operation Range
CPU clock
cycle time
(minimum
instruction
execution time)*1
Interrupt input
width high/low
AC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operating on main
V
DD
= 4.5 to 6.0 V
0.95
64
s
system clock
3.8
64
s
Operating on
subsystem clock
TI0 input
V
DD
= 4.5 to 6.0 V
0
1
MHz
frequency
f
TI
0
275
kHz
TI0 input width
V
DD
= 4.5 to 6.0 V
0.48
s
high/low
1.8
s
INT0
*2
s
INT1, 2, 4
10
s
KR0 to KR7
10
s
RESET width low
t
RSL
10
s
114
122
125
s
*
1. The CPU clock (
) cycle time (minimum
instruction execution time) is determined by
the oscillatior frequency of the connected
resonator, the system clock control register
(SCC) and the processor clock control register
(PCC). The figure at the right indicates the
cycle time t
CY
versus supply voltage V
DD
characteristic with the main system clock
operating.
2. 2t
CY
or 128/f
X
is set by setting the interrupt
mode register (IM0).
52
PD75304B,75306B,75308B
t
SIK2
100
ns
SERIAL TRANSFER OPERATION
2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
= 4.5 to 6.0 V
1600
ns
SCK cycle time
t
KCY1
3800
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
t
KCY1
/2-50
ns
low
t
KCY1
/2-150
ns
SI setup time
(to SCK
)
SI hold time
(from SCK
)
SO output
V
DD
= 4.5 to 6.0 V
250
ns
delay time
t
KSO1
from SCK
1000
ns
2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85
C, V
DD
= 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
800
ns
t
KCY2
3200
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
400
ns
low
1600
ns
SI setup time
(to SCK
)
SI hold time
(from SCK
)
SO output
V
DD
= 4.5 to 6.0 V
300
ns
delay time
t
KSO2
from SCK
1000
ns
*
R
L
and C
L
are load resistor and load capacitance of the SO output line.
t
SIK1
150
ns
t
KSI1
400
ns
t
KL1
t
KH1
R
L
= 1 k
,
C
L
= 100 pF*
t
KSI2
400
ns
t
KL2
t
KH2
R
L
= 1 k
,
C
L
= 100 pF*
PD75304B,75306B,75308B
53
SBI Mode (SCK ... Internal clock output (Master)): (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
1600
ns
t
KCY3
3800
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
t
KCY3
/2-50
ns
low
t
KCY3
/2-150
ns
SB0, 1 setup time
(to SCK
)
SB0, 1 hold time
(from SCK
)
SB0, 1 output
V
DD
= 4.5 to 6.0 V
0
250
ns
delay time from
t
KSO3
SCK
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY3
ns
SCK from SB0, 1
t
SBK
t
KCY3
ns
SB0, 1 width low
t
SBL
t
KCY3
ns
SB0, 1 width high
t
SBH
t
KCY3
ns
SBI Mode (SCK ... External clock input (Slave)): (Ta = 40 to +85
C, V
DD
= 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
800
ns
t
KCY4
3200
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
400
ns
low
1600
ns
SB0, 1 setup time
(to SCK
)
SB0, 1 hold time
(from SCK
)
SB0, 1 output
V
DD
= 4.5 to 6.0 V
0
300
ns
delay time from
t
KSO4
SCK
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY4
ns
SCK
from SB0, 1
t
SBK
t
KCY4
ns
SB0, 1 width low
t
SBL
t
KCY4
ns
SB0, 1 width high
t
SBH
t
KCY4
ns
*
R
L
and C
L
are load resistor and load capacitance of the SB0, 1 output lines.
t
KSI4
t
KCY4
/2
ns
t
SIK3
150
ns
t
KSI3
t
KCY3
/2
ns
t
KL3
t
KH3
R
L
= 1 k
,
C
L
= 100 pF*
t
SIK4
100
ns
t
KL4
t
KH4
R
L
= 1 k
,
C
L
= 100 pF*
54
PD75304B,75306B,75308B
I
OL
= 400
A
0.5
V
V
OH1
I
OH
= 100
A
V
DD
0.5
V
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V) (1/2)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IH1
Ports 2 and 3
0.8 V
DD
V
DD
V
V
IH2
Ports 0, 1, 6, 7, RESET
0.8 V
DD
V
DD
V
On-chip pull-up resistor
0.8 V
DD
V
DD
V
V
IH3
Ports 4 and 5
Opendrain
0.8 V
DD
10
V
V
IH4
X1, X2, XT1
V
DD
0.3
V
DD
V
V
IL1
Ports 2, 3, 4 and 5
0
0.2 V
DD
V
V
IL2
Ports 0, 1, 6, 7, RESET
0
0.2 V
DD
V
V
IL3
X1, X2, XT1
0
0.3
V
Ports 0, 2, 3, 6,
7, BIAS
BP0 to BP7 (with
2 I
OH
outputs)
Ports 0, 2, 3, 4, 5
6, and 7
V
OL1
Opendrain,
pull-up resistor
1 k
BP0 to BP7
(with 2 I
OL
outputs)
I
LIH1
Other than below
3
A
V
IN
= V
DD
I
LIH2
X1, X2, XT1
20
A
Ports 4 and 5
(with opendrain)
Input leakage
I
LIL1
Other than below
3
A
current low
V
IN
= 0 V
I
LIL2
X1, X2, XT1
20
A
Output leakage
I
LOH1
V
OUT
= V
DD
Other than below
3
A
current high
Ports 4 and 5
(with opendrain)
Output leakage
current low
V
OH2
I
OH
= 10
A
V
DD
0.4
V
SB0, 1
0.2 V
DD
V
V
OL2
I
OL
= 10
A
0.4
V
I
LIH3
V
IN
= 10 V
20
A
I
LOH2
V
OUT
= 10 V
20
A
I
LOL
V
OUT
= 0 V
3
A
Input voltage
high
Input voltage
low
Output voltage
high
Output voltage
low
Input leakage
current high
PD75304B,75306B,75308B
55
DC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V) (2/2)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Ports 0, 1, 2, 3, 6
R
L1
and 7 (Except P00)
V
DD
= 2.5 V
10%
50
600
k
V
IN
= 0 V
Ports 4 and 5
V
OUT
= V
DD
1.0 V
LCD drive voltage
V
LCD
2.0
V
DD
V
LCD split resistor
R
LCD
60
100
150
k
LCD output voltage
deviation *1
V
ODC
I
O
=
5
A
0
0.2
V
(common)
LCD output
voltage deviation
V
ODS
I
O
=
1
A
0
0.2
V
(segment)
V
DD
= 3 V
10%*4
0.4
1.2
mA
I
DDI
V
DD
= 2.5 V
10%*4
0.3
0.9
mA
HALT
V
DD
= 3 V
10%
180
540
A
I
DD2
mode
V
DD
= 2.5 V
10%
120
360
A
V
DD
= 3 V
10%
40
120
A
I
DD3
Supply current*2
V
DD
= 2.5 V
10%
25
75
A
HALT
V
DD
= 3 V
10%
12
36
A
I
DD4
mode
V
DD
= 2.5 V
10%
9
27
A
0.5
15
A
V
DD
= 3 V
10%
Ta = 25
C
0.5
5
A
I
DD5
0.4
15
A
Ta = 25
C
0.4
5
A
*
1. The voltage deviation is the difference between the output voltage and the segment or common output
desired value (V
LCDn
; n = 0, 1, 2).
2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.
3. Including oscillation of the subsystem clock.
4. When PCC is set to 0000 and the device is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem
clock, with main system clock oscillation stopped.
R
L2
V
DD
= 2.5 V
10%
10
60
k
V
LCDO
= V
LCD
V
LCD1
= V
LCD
2/3
V
LCD2
= V
LCD
1/3
2.0 V
V
LCD
V
DD
4.19 MHz*3
crystal oscillation
C1 = C2 = 22 pF
low-speed mode
32 kHz*5
crystal oscillation
XT1 = 0 V
STOP mode
V
DD
= 2.5 V
10%
On-chip pull-up
resistor
56
PD75304B,75306B,75308B
3.4
64
s
AC CHARACTERISTICS (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
= 2.7 to 6.0 V
3.8
64
s
Operation on main
V
DD
= 2.0 to 6.0 V
5
64
s
system clock
t
CY
Ta = 40 to + 60
C
V
DD
= 2.2 to 6.0 V
Operation on
subsystem clock
TI0 input
frequency
TI0 input width
t
TIH
,
high/low
t
TIL
INT0
*2
s
INT1, 2, 4
10
s
KR0 to KR7
10
s
RESET width low
t
RSL
10
s
114
122
125
s
f
TI
0
275
kHz
1.8
s
t
INTH
,
t
INTL
*
1. The CPU clock (
) cycle time (minimum
instruction execution time) is determined by
the oscillatior frequency of the connected
resonator, the system clock control register
(SCC) and the processor clock control register
(PCC). The figure at the right indicates the
cycle time t
CY
versus supply voltage V
DD
characteristic with the main system clock
operating.
2. 2t
CY
or 128/f
X
is set by setting the interrupt
mode register (IM0).
Interrupt input
width high/low
t
CY
vs V
DD
(Operating on Main System Clock)
Cycle Time t
CY
[
s]
Supply Voltage V
DD
[V]
0
1
2
3
4
5
6
0.5
1
2
3
4
5
30
64
70
6
Guaranteed
Operation Range
CPU clock
cycle time
(minimum
instruction
execution time)*1
PD75304B,75306B,75308B
57
SERIAL TRANSFER OPERATION
2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
1600
ns
t
KCY1
3800
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
t
KCY1
/2-50
ns
low
t
KCY1
/2-150
ns
SI setup time
(to SCK
)
SI hold time
(from SCK
)
SO output
V
DD
= 4.5 to 6.0 V
250
ns
delay time
t
KSO1
from SCK
1000
ns
2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
800
ns
t
KCY2
3200
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
400
ns
low
1600
ns
SI setup time
(to SCK
)
SI hold time
(from SCK
)
SO output
V
DD
= 4.5 to 6.0 V
300
ns
delay time
t
KSO2
from SCK
1000
ns
*
R
L
and C
L
are load resistor and load capacitance of the SO output line.
t
KSI2
400
ns
t
SIK2
100
ns
t
KL1
t
KH1
t
KSI1
400
ns
t
SIK1
250
ns
R
L
= 1 k
,
C
L
= 100 pF*
t
KL2
t
KH2
R
L
= 1 k
,
C
L
= 100 pF*
58
PD75304B,75306B,75308B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
1600
ns
t
KCY3
3800
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
t
KCY3
/2-50
ns
low
t
KCY3
/2-150
ns
SB0, 1 setup
time (to SCK
)
SB0, 1 hold
time (from SCK
)
SB0, 1 output
V
DD
= 4.5 to 6.0 V
0
250
ns
delay time
t
KSO3
from SCK
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY3
ns
SCK from SB0, 1
t
SBK
t
KCY3
ns
SB0, 1 width low
t
SBL
t
KCY3
ns
SB0, 1 width high
t
SBH
t
KCY3
ns
SBI Mode (SCK ... External clock input (Slave)): (Ta = 40 to +85
C, V
DD
= 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
SCK cycle time
V
DD
= 4.5 to 6.0 V
800
ns
t
KCY4
3200
ns
SCK width high/
V
DD
= 4.5 to 6.0 V
400
ns
low
1600
ns
SB0, 1 setup
time (to SCK
)
SB0, 1 hold
time (from SCK
)
SB0, 1
V
DD
= 4.5 to 6.0 V
0
300
ns
output delay
t
KSO4
time from SCK
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY4
ns
SCK
from SB0, 1
t
SBK
t
KCY4
ns
SB0, 1 width low
t
SBL
t
KCY4
ns
SB0, 1 width high
t
SBH
t
KCY4
ns
*
R
L
and C
L
are load resistor and load capacitance of the SB0, 1 output lines.
t
KSI3
t
KCY3
/2
ns
t
SIK3
250
ns
t
SIK4
100
ns
t
KSI4
t
KCY4
/2
ns
t
KL4
t
KH4
t
KL3
t
KH3
R
L
= 1 k
,
C
L
= 100 pF*
R
L
= 1 k
,
C
L
= 100 pF*
PD75304B,75306B,75308B
59
X1 Input
1/f
X
t
XL
t
XH
V
DD
-0.5 V
0.4 V
XT1 Input
1/f
XT
t
XTL
t
XTH
V
DD
-0.5 V
0.4 V
TI0
1/f
TI
t
TIL
t
TIH
AC Timing Test Point (Excluding X1 and XT1 inputs)
Clock Timings
TI0 Timing
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Test Points
60
PD75304B,75306B,75308B
SCK
t
KCY1
t
KH1
t
KL1
Input Data
Output Data
t
SIK1
t
KSI1
t
KSO1
SI
SO
Serial Transfer Timing
3-wired serial I/O mode:
2-wired serial I/O mode:
t
KSO2
t
KL2
t
KH2
t
KCY2
SCK
SB0,1
t
SIK2
t
KSI2
PD75304B,75306B,75308B
61
t
INTL
t
INTH
INT0,1,2,4
KR0-7
t
RSL
RESET
t
KSB
t
KSO3,4
t
SIK3,4
t
KSI3,4
t
KL3,4
t
KH3,4
t
KCY3,4
SCK
SB0,1
t
SBK
Serial Transfer Timing
Bus release signal transfer:
Command signal transfer:
Interrupt Input Timing
RESET Input Timing
t
KSB
t
SBL
t
SBH
t
SBK
t
KSO3,4
t
SIK3,4
t
KSI3,4
t
KL3,4
t
KH3,4
t
KCY3,4
SCK
SB0,1
62
PD75304B,75306B,75308B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = 40 to 85
C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention supply voltage
V
DDDR
2.0
6.0
V
Data retention supply current*1
I
DDDR
V
DDDR
= 2.0 V
0.3
15
A
Release signal setup time
t
SREL
0
s
Oscillation stabilization
Release by RESET
2
17
/fx
ms
wait time*2
t
WAIT
Release by interrupt request
*3
ms
*
1. Current which flows in the on-chip pull-up resistor is not included.
2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
3. Depends on the basic interval timer mode register (BTM) setting (table below).
WAIT TIME
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at fx = 4.19 MHz)
--
0
0
0
2
20
/fx (approx. 250 ms)
--
0
1
1
2
17
/fx (approx. 31.3 ms)
--
1
0
1
2
15
/fx (approx. 7.82 ms)
--
1
1
1
2
13
/fx (approx. 1.95 ms)
PD75304B,75306B,75308B
63
Data Retention Timing (STOP mode release by RESET)
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
STOP Mode
Data Retention Mode
STOP Instruction Execution
V
DD
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Standby Release Signal
(Interrupt Request)
STOP Mode
Data Retention Mode
STOP Instruction Execution
RESET
V
DD
Internal Reset Operation
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
64
PD75304B,75306B,75308B
12. PACKAGE INFORMATION
A
M
F
B
60
61
40
K
L
80 PIN PLASTIC QFP ( 14)
80
1
21
20
41
G
D
C
detail of lead end
S
Q
P
M
I
H
J
55
N
S80GC-65-3B9-3
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
17.20.4
14.00.2
0.8
0.300.10
0.13
14.00.2
0.6770.016
0.031
0.031
0.005
0.026 (T.P.)
0.551
NOTE
M
N
0.10
0.15
1.60.2
0.65 (T.P.)
0.004
0.006
+0.004
0.003
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
0.0630.008
0.012
0.551
0.80.2
0.031
P
2.7
0.106
0.6770.016
17.20.4
0.8
+0.009
0.008
Q
0.10.1
0.0040.004
S
3.0 MAX.
0.119 MAX.
+0.10
0.05
+0.009
0.008
+0.004
0.005
+0.009
0.008
PD75304B,75306B,75308B
65
N
A
M
F
B
64
65
40
K
L
80 PIN PLASTIC QFP (14
20)
80
1
25
24
41
G
D
C
P
detail of lead end
S
Q
55
M
I
H
J
P80GF-80-3B9-2
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
23.60.4
14.00.2
0.8
0.350.10
0.15
20.00.2
0.9290.016
0.039
0.031
0.006
0.031 (T.P.)
0.795
NOTE
M
N
0.15
0.15
1.80.2
0.8 (T.P.)
0.006
0.006
+0.004
0.003
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
0.071
0.014
0.551
0.80.2
0.031
P
2.7
0.106
0.6930.016
17.60.4
1.0
+0.009
0.008
Q
0.10.1
0.0040.004
S
3.0 MAX.
0.119 MAX.
+0.10
0.05
+0.009
0.008
+0.004
0.005
+0.009
0.008
+0.008
0.009
66
PD75304B,75306B,75308B
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
ITEM MILLIMETERS
INCHES
I
J
0.5 (T.P.)
0.10
0.004
0.020 (T.P.)
A
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
S
A
14.00.2
0.551 +0.009
0.008
B
12.00.2
0.472 +0.009
0.008
C
12.00.2
0.472 +0.009
0.008
D
14.00.2
0.551 +0.009
0.008
F
G
1.25
1.25
0.049
0.049
H
0.22
0.0090.002
P80GK-50-BE9-4
S
1.27 MAX.
0.050 MAX.
K
1.00.2
0.039 +0.009
0.008
L
0.50.2
0.020 +0.008
0.009
M
0.145
0.0060.002
N
0.10
0.004
P
1.05
0.041
Q
0.050.05
0.0020.002
R
55
55
+0.05
0.04
+0.055
0.045
B
C
D
J
H
I
G
F
P
N
L
K
M
Q
R
detail of lead end
M
61
60
41
40
21
20
1
80
PD75304B,75306B,75308B
67
13. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below.
For details of recommended soldering conditions, refer to the information document "Surface Mount
Technology Manual (IEI 1207)".
For soldering methods and conditions other than those recommended, please contact our salesman.
Table 13-1 Surface Mount Type Soldering Conditions
5
(1)
PD75304BGC-
-3B9: 80-Pin Plastic QFP (
s
s
14 mm)
PD75306BGC-
-3B9: 80-Pin Plastic QFP (
s
s
14 mm)
PD75308BGC-
-3B9: 80-Pin Plastic QFP (
s
s
14 mm)
Soldering Method
Soldering ConditionsRecommended
Condition Symbol
Package peak temperature: 230
C Duration: 30 sec. max. (210
C or above)
Infrared reflow
Number of applications: one
Time limit: 7 days* (thereafter 20 hours 125
C prebaking required)
Package peak temperature: 215
C Duration: 40 sec. max. (200
C or above)
VPS
Number of applications: one
Time limit: 7 days* (thereafter 20 hours 125
C prebaking required)
Pin part heating
Pin part temperature: 300
C or less
Duration: 3 sec. max. (per side of device)
IR30-207-1
VP15-207-1
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25
C, 65% RH.
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
IR30-00-1
VP15-00-1
WS60-00-1
Soldering Method
Soldering ConditionsRecommended
Condition Symbol
Infrared reflow
Package peak temperature: 230
C Duration: 30 sec. max. (210
C or above)
Number of applications: one
VPS
Package peak temperature: 215
C Duration: 40 sec. max. (200
C or above)
Number of applications: one
Solder bath temperature: 260
C or less Duration: 10 sec. max.
Wave soldering
Number of applications: one
Preparatory heating temperature: 120
C max. (package surface temperature)
Pin part heating
Pin part temperature: 300
C or less
Duration: 3 sec. max. (per side of device)
(2)
PD75304BGF-
-3B9: 80-Pin Plastic QFP (14
20 mm)
PD75306BGF-
-3B9: 80-Pin Plastic QFP (14
20 mm)
PD75308BGF-
-3B9: 80-Pin Plastic QFP (14
20 mm)
68
PD75304B,75306B,75308B
(3)
PD75304BGK-
-3B9: 80-Pin Plastic TQFP (
s
s
12 mm)
PD75306BGK-
-3B9: 80-Pin Plastic TQFP (
s
s
12 mm)
PD75308BGK-
-3B9: 80-Pin Plastic TQFP (
s
s
12 mm)
Soldering Method
Soldering ConditionsRecommended
Condition Symbol
Package peak temperature: 230
C Duration: 30 sec. max. (210
C or above)
Infrared reflow
Number of applications: one
Time limit: 1 day* (thereafter 16 hours 125
C prebaking required)
Package peak temperature: 215
C Duration: 40 sec. max. (200
C or above)
VPS
Number of applications: one
Time limit: 1 day* (thereafter 16 hours 125
C prebaking required)
Pin part heating
Pin part temperature: 300
C or less
Duration: 3 sec. max. (per side of device)
IR30-161-1
VP15-161-1
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25
C, 65% RH.
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
NOTICE
Recommended soldering conditions have been improved for some of these products.
(Improvements: Relaxation of infrared reflow peak temperature (235
C, number of applications (two),
time limit, etc.)
Please contact your NEC sales representative for details.
PD75304B,75306B,75308B
69
[MEMO]
70
PD75304B,75306B,75308B
APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS
5
Item
Supply voltage range
ROM configuration
Program memory (bytes)
Data memory (
4 bits)
Instruction cycle
CMOS input
CMOS input/output
Input/output
ports
CMOS output
N-ch opendrain
input/output
LCD controller/driver
LCD drive voltage
Timer/counter
Serial interface
Vectored interrupt
Test input
Clock output (PCL)
Buzzer output (BUZ)
Package
On-chip PROM product
0.95
s, 1.91
s, 15.3
s (main system clock: 4.19 MHz operation)
122
s (subsystem clock: 32.768 kHz operation)
8
Pull-up resistor incorporation spesifiable by software: 23
16
40
8
Used with segment pin
8
Common output: Static 1/4 duty selected
Segment output: Max. 32
LCD drive split resistor can be incorporated by
No LCD drive split resistor.
mask option.
2.0 to V
DD
8-bit timer/event counter
8-bit basic interval timer
Watch timer
NEC standard serial bus interface (SBI)
Clock synchronous serial interface
External: 3
Internal: 3
External: 1
Internal: 1
, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation)
2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz
operation)
PD75P308
PD75P316
PD75P316A
PD75304/75306/75308
PD75312/75316
PD75P308
PD75P316
2.0 to 6.0 V
5V
5%
Mask ROM
4096/6016/8064
12160/16256
8064
16256
512
EPROM/One-
time
One-time
PROM
Product Name
10 V withstand voltage. Pull-up
resistor incorporation spesifiable by
mask option.
(without pull-up resistor)
10 V withstand voltage. Pull-up
resistor incorporation spesifiable
by mask option
80-pin plastic QFP (14
20 mm)
80-pin plastic QFP
(14
20 mm)
80-pin plastic QFP
(14
20 mm)
80-pin ceramic
WQFN (LCC with
window)
PD75304B,75306B,75308B
71
Item
Supply voltage range
ROM configuration
Program memory (bytes)
Data memory (
4 bits)
Instruction cycle
CMOS input
CMOS input/output
Input/output
ports
CMOS output
N-ch opendrain
input/output
LCD controller/driver
LCD drive voltage
Timer/counter
Serial interface
Vectored interrupt
Test input
Clock output (PCL)
Buzzer output (BUZ)
Package
On-chip PROM product
80-pin
ceramic
WQFN
80-pin plastic
QFP
(14
20 mm)
0.95
s, 1.91
s, 15.3
s (main system clock: 4.19 MHz operation)
122
s (subsystem clock: 32.768 kHz operation)
8
Pull-up resistor incorporation spesifiable by software: 23
16
40
8
Used with segment pin
8
Common output: Static 1/4 duty selected
Segment output: Max. 32
LCD drive split resistor can be incorporat-
No LCD drive split resistor.
ed by mask option.
2.0 to V
DD
8-bit timer/event counter
8-bit basic interval timer
Watch timer
NEC standard serial bus interface (SBI)
Clock synchronous serial interface
External: 3
Internal: 3
External: 1
Internal: 1
, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation)
2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz
operation)
GF package:
PD75P316A
PD75P316B
GC/GK package:
PD75P316B
Product Name
PD75304B/75306B/75308B
PD75312B
PD75316B
PD75P316B*
PD75P316A
2.0 to 6.0 V
Mask ROM
4096/6016/8064
12160
16256
512
1024
10 V withstand voltage. Pull-
up resistor incorporation
spesifiable by mask option
10 V withstand voltage. Pull-up resistor
incorporation spesifiable by mask option.
(without pull-up resistor)
One-time
PROM
EPROM/One-
time
80-pin plastic QFP (
s
s
14mm)
80-pin plastic TQFP(
s
s
12mm)
80-pin plastic QFP
(14
20 mm)
(
s
s
14mm)
80-pin
plastic TQFP(
s
s
12mm)
*
Under development
72
PD75304B,75306B,75308B
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the
PD75304B/75306B/
75308B.
IE-75000-R*1
IE-75001-R
IE-75000-R-EM*2
EP-75308GF-R
EV-9200G-80
EP-75308BGC-R
EV-9200GC-80
EP-75308BGK-R
EV-9500GK-80
PG-1500
PA-75P308GF
PA-75P316BGC
PA-75P316BGK
IE Control Program
PG-1500 Controller
RA75X Relocatable Assembler
75X series in-circuit emulator
Emulation board for the IE-75000-R or IE-75001-R
Emulation probe for the
PD75304BGF, 75306BGF and 75308BGF.
An 80-pin conversion socket (EV-9200G-80) is also provided.
Emulation probe for the
PD75304BGC, 75306BGC and 75308BGC.
An 80-pin conversion socket (EV-9200GC-80) is also provided.
Emulation probe for the
PD75304BGK, 75306BGK and 75308BGK.
An 80-pin conversion adapter (EV-9200GK-80) is also provided.
PROM programmer
PROM programmer adapter for the
PD75P316AGF, connected to the
PG-1500.
PROM programmer adapter for the
PD75P316BGC, connected to the
PG-1500.
PROM programmer adapter for the
PD75P316BGK, connected to the
PG-1500.
Host machines
PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3)
IBM PC/ATTM(PC DOSTM Ver. 3.1)
*
1. Maintenance product
2. Not incorporated in the IE-75001-R.
3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this
software.
Remarks
Please refer to the 75X Series Selection Guide (IF-151) for third party development tools.
Hardware
Soft
ware
PD75304B,75306B,75308B
73
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
Document Name
Document Number
User's Manual
IEM-5016
Instruction Application Table
IEM-994
Application Note
IEM-5035
IEM-5041
75X Series Selection Guide
IF-151
Development Tools Documents
Document Name
Document Number
IE-75000-R/IE-75001-R User's Manual
EEU-846
IE-75000-R-EM User's Manual
EEU-673
EP-75308GF-R User's Manual
EEU-689
EP-75308BGC-R User's Manual
EEU-825
EP-75308BGK-R User's Manual
EEU-838
PG-1500 User's Manual
EEU-651
RA75X Assembler Package User's Manual
Operation
EEU-731
Language
EEU-730
PG-1500 Controller User's Manual
EEU-704
Hardware
Other Documents
Document Name
Document Number
Package Manual
IEI-635
Surface Mount Technology Manual
IEI-1207
Quality Grande on NEC Semiconductor Device
IEI-1209
NEC Semiconductor Device Reliability & Quality Control
IEM-5068
Electrostatic Discharge(ESD) Test
MEM-539
Semiconductor Devices Quality Guarantee Guide
MEI-603
Microcomputer Related Products Guide Other Manufacturers Volume
MEI-604
*
The contents of the above related documents are subject to change without notice. The latest documents
should be used for design, etc.
Soft
ware
74
PD75304B,75306B,75308B
[MEMO]
PD75304B,75306B,75308B
75
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard :
Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
MS-DOS is a trademark of MicroSoft Corporation.
PC DOS, PC/AT is a trademark of IBM Corporation.
M4 92.6
PD75304B,75306B,75308B
PDF 
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