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Электронный компонент: UPD720130GC-9EU-SIN

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MOS INTEGRATED CIRCUIT



PD720130
USB2.0 to IDE Bridge
Document No.
S16302EJ3V0DS00 (3rd edition)
Date Published
June 2003 NS CP (K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2002
The
PD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The PD720130 complies
with the Universal Serial Bus Specification Revision 2.0
full-/high-speed signaling and works up to 480 Mbps. The
PD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine
(SIE), and USB2.0 transceiver into a single chip. The USB2.0 protocol and class specific protocol (bulk only
protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC
processor which is in the
PD720130. The software to control the PD720130 is located in an embedded ROM. In
the future, the
PD720130 will be released to support external Flash Memory / EEPROMTM option to update function
by firmware.
Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.



PD720130 User's Manual: S16412E
FEATURES
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
USB2.0 high-speed bus powered device capability
Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)
One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
Automatic chirp assertion and full-/high-speed mode change
USB Reset, Suspend and Resume signaling detection
Supports power control functionality for IDE device as CD-ROM and HDD
Supports set feature (TEST_MODE) functionality
System Clock is generated by 30 MHz X'tal
2.5 V and 3.3 V power supply
ORDERING INFORMATION
Part Number
Package
PD720130GC-9EU
100-pin plastic TQFP (fine pitch) (14
14)
PD720130GC-9EU-SIN
100-pin plastic TQFP (fine pitch) (14
14)
Data Sheet S16302EJ3V0DS
2



PD720130
BLOCK DIAGRAM
RAM
4 Kbytes
2
CPU Core
(V30MZ)
Bus Bridge
ROM
8 Kbytes
DMAC
INTC
Direct Bus
16-bit Bus
PIO
FSIO
Timer
IDEC_V2
EPC2_V2
DCC
PHY_V2
GPIO
Direct Command Bus
Ext. Bus (Data 8-bit Bus) or PIO
IDE Bus
Serial
ROM
8-bit Bus
GPIO
or
FSIO
USB Bus
16-bit Bus
V30MZ
: CISC CPU core
RAM
: 8-Kbyte work RAM for firmware
ROM
: 8-Kbyte ROM for built-in firmware
PHY_V2
: USB2.0 transceiver with serial interface engine
EPC_V2
: Endpoint controller
IDEC_V2
: IDE controller
DCC
: ATA direct command controller
Bus Bridge
: Internal / external bus controller and DMA controller
INTC
: Interrupt controller (82C59 like)
GPIO
: General purpose 8-bit I/O controller
PIO
: Multipurpose 14-bit I/O controller
FSIO
: Flexible serial I/O
Data Sheet S16302EJ3V0DS
3



PD720130
PIN CONFIGURATION (TOP VIEW)
100-pin plastic TQFP (fine pitch) (14 14)
PD720130GC-9EU
PD720130GC-9EU-SIN
V
DD25
V
DD33
GPIO1
DV0
GPIO2
PIO15
GPIO0
GPIO3
IDEA2
GPIO7
IDEA0
IDEA1
V
SS
IDEIORDY
IDEDAKB
IDEINT
IDEIORB
TEST0
TEST1
TEST3
V
DD33
V
DD25
SCL
V
SS
DPC
SDA
TEST2
V
DD25
RPU
V
DD25
V
SS
RSDP
DP
V
DD33
DM
RSDM
V
SS
AV
DD25
AV
SS
RREF
V
SS
SMC
IDED5
V
SS
V
DD33
IDERSTB
IDED7
IDED8
IDED6
IDED10
IDED9
IDED4
IDED11
IDED3
IDED12
V
SS
V
DD25
IDED2
IDED13
IDED14
IDED1
V
DD33
IDED0
IDED15
GPIO4
IDEDRQ
IDEIOWB
V
SS
V
DD25
CLC
CMB_STATE
PWR
V
DD25
V
DD33
PIO5
V
DD33
CMB_BSY
VBUS
V
DD25
AV
SS
AV
DD25
AV
SS
(R)
V
SS
IDECS0B
GPIO5
MD1
IRQ0
RESETB
SPD
V
SS
V
DD33
GPIO6
MD0
V
SS
IDECS1B
XOUT
XIN
DCC
PIO14
DV1
1
5
10
15
20
25
30
40
45
35
50
55
60
65
70
75
85
90
100
80
95
Data Sheet S16302EJ3V0DS
4



PD720130
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
V
DD25
26
V
SS
51
V
DD25
76
V
SS
2
V
DD33
27
IDEIOWB
52
V
DD33
77
DPC
3
XIN
28
IDEDRQ
53
GPIO7
78
SDA
4
XOUT
29
IDED15
54
GPIO6
79
SCL
5
V
SS
30
IDED0
55
GPIO5
80
TEST2
6
RESETB
31
V
DD33
56
GPIO4
81
V
DD25
7
V
DD33
32
IDED14
57
GPIO3
82
RPU
8
IRQ0
33
IDED1
58
GPIO2
83
V
DD25
9
MD0
34
IDED13
59
GPIO1
84
V
SS
10
MD1
35
IDED2
60
V
SS
85
RSDP
11
IDECS1B
36
V
DD25
61
GPIO0
86
DP
12
IDECS0B
37
V
SS
62
PIO15
87
V
DD33
13
IDEA2
38
IDED12
63
PIO14
88
DM
14
IDEA0
39
IDED3
64
DCC
89
RSDM
15
IDEA1
40
IDED11
65
DV1
90
V
SS
16
V
SS
41
IDED4
66
DV0
91
AV
DD25
17
IDEINT
42
IDED10
67
V
SS
92
AV
SS
18
IDEDAKB
43
V
DD33
68
SPD
93
RREF
19
IDEIORDY
44
IDED5
69
CLC
94
AV
SS
(R)
20
IDEIORB
45
IDED9
70
PWR
95
AV
DD25
21
TEST0
46
IDED6
71
CMB_BSY
96
AV
SS
22
TEST1
47
IDED8
72
PIO5
97
V
DD25
23
TEST3
48
IDED7
73
CMB_STATE
98
VBUS
24
V
DD33
49
IDERSTB
74
V
DD33
99
SMC
25
V
DD25
50
V
SS
75
V
DD25
100
V
SS
Remark AV
SS
(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 k
.
Data Sheet S16302EJ3V0DS
5



PD720130
1.
PIN INFORMATION
(1/2)
Pin Name
I/O
Buffer Type
Active
Level
Function
XIN
I
2.5 V Input
System clock input or oscillator In
XOUT
O
2.5 V Output
Oscillator out
RESETB
I
3.3 V Schmitt Input
Low
Asynchronous reset signaling
MD(1:0)
I
3.3 V Input
Function mode setting
IDECS(1:0)B
O (I/O)
5 V tolerant Output
Low
IDE host chip select
IDEA(2:0)
O (I/O)
5 V tolerant Output
IDE address bus
IDEINT
I (I/O)
5 V tolerant Input
High
IDE interrupt request from device to host
IDEDAKB
O (I/O)
5 V tolerant Output
Low
IDE DMA acknowledge
IDEIORDY
I (I/O)
5 V tolerant Input
High
IDE IO channel ready
IDEIORB
O (I/O)
5 V tolerant Output
Low
IDE IO read strobe
IDEIOWB
O (I/O)
5 V tolerant Output
Low
IDE IO write strobe
IDEDRQ
I (I/O)
5 V tolerant Input
High
IDE DMA request from device to host
IDED(15:0)
I/O
5 V tolerant I/O
IDE data bus
IDERSTB
O (I/O)
5 V tolerant Output
Low
IDE reset from host to device
DCC
I (I/O)
3.3 V Input
IDE controller operational mode setting
DV(1:0)
I (I/O)
3.3 V Input
Device select
CLC
I (I/O)
3.3 V Input
System clock setting
PWR
I (I/O)
3.3 V Input
Bus powered /self-powered select
CMB_BSY
O (I/O)
3.3 V Output
Combo IDE bus busy
CMB_STATE
I (I/O)
3.3 V Input
Combo IDE bus state
DPC
O (I/O)
3.3 V Output
Power control signaling for IDE device
SDA
I/O
3.3 V I/O
Serial ROM data signaling
SCL
I/O
3.3 V I/O
Serial ROM clock signaling
VBUS
I
5 V Schmitt Input
Note
VBUS monitoring
DP
I/O
USB high speed D+ I/O
USB's high speed D+ signal
DM
I/O
USB high speed D
- I/O
USB's high speed D
- signal
RSDP
O
USB full speed D+ Output
USB's full speed D+ signal
RSDM
O
USB full speed D
- Output
USB's full speed D
- signal
RPU
A
USB Pull-up control
USB's 1.5 k
pull-up resistor control
RREF
A
Analog
Reference resistor
SPD
I (I/O)
3.3 V Input
NEC private
SMC
I
3.3 V Input
Scan mode control
TEST(3:0)
I
3.3 V Input
Test mode setting
Note
VBUS pin may be used to monitor for VBUS line even if V
DD33
, V
DD25
, and AV
DD25
are shut off. System must
ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is
not exceeded.
Data Sheet S16302EJ3V0DS
6



PD720130
(2/2)
Pin Name
I/O
Buffer Type
Active
Level
Function
GPIO(7:0)
I/O
3.3 V Schmitt I/O
General purpose IO port (for future extension)
PIO(15:14)
I/O
3.3 V I/O
IO port (for future extension)
PIO(5)
I/O
3.3 V Schmitt I/O
IO port (for future extension)
IRQ0
I
3.3 V Schmitt Input
High
External interrupt input (for future extension)
AV
DD25
2.5 V V
DD
for Analog circuit
V
DD25
2.5 V V
DD
V
DD33
3.3 V V
DD
AV
SS
V
SS
for Analog circuit
V
SS
V
SS
Remarks 1. "5 V tolerant" means that the buffer is 3.3 V buffer with 5 V tolerant circuit.
2. The signal marked as "(I/O)" in the above table operates as I/O signals during testing. However, they
do not need to be considered in normal use.
Data Sheet S16302EJ3V0DS
7



PD720130
2.
FUNCTION INFORMATION
USB to IDE system can be realized by the
PD720130, Serial ROM which has USB vender ID, product ID, etc,
and power control circuit. The
PD720130 can be selected bus powered mode or self powered mode. If all power
consumption for USB to IDE system is less than the specification of bus powered device, it will be possible to realize
high-speed capable bus powered system. The
PD720130 has some features for bus powered system. Also, some
system may control target IDE device by two IDE controllers. At the time, IDE bus arbitration should be required to
each IDE controller. The
PD720130 has a feature of IDE bus arbitration, too.
The setting of IDE controller in the
PD720130 is controlled by data in serial ROM or external pin setting. If there
is any inconsistency between data in serial ROM and external pin setting, the data in serial ROM is higher priority than
external pin setting.
2.1
Data in Serial ROM
The
PD720130 loads some data such as Vendor ID, Product ID and some additional USB related information,
etc from serial ROM when the
PD720130 is initialized. Example of data in serial ROM is as follows. ExPinReset
and ExPinSet fields hold data which is related to the external pin setting.
Table 2-1. Data in Serial ROM
Data size
Symbol
Description
1 Word
Flags
Control for descriptor overwrite
1 Byte
ExPinReset
PWR, CLC, DCC, DV[1:0] Reset bit map field
1 Byte
ExPinSet
PWR, CLC, DCC, DV[1:0] Set bit map field
1 Word
idVendor
idVendor field in Device descriptor
1 Word
idProduct
idProduct field in Device descriptor
1 Word
bcdDevice
bcdDevice field in Device descriptor
1 Byte
MaxPower BUS
MaxPower field in Configuration descriptor for Bus powered mode
1 Byte
MaxPower Self
MaxPower field in Configuration descriptor for Self powered mode
1 Byte
bInterfaceClass
bInterfaceClass field in Interface descriptor
1 Byte
bInterfaceSubClass
bInterfaceSubClass field in Interface descriptor
1 Byte
bInterfaceProtocol
bInterfaceProtocol field in Interface descriptor
1 Word
TxMode Reset
IDE transmission type such as Ultra DMA 66 Reset bit map field
1 Word
TxMode Set
IDE transmission type such as Ultra DMA 66 Set bit map field
32 Bytes
ManufactureString
String descriptor for Manufacturer
32 Bytes
ProductString
String descriptor for Product
32 Bytes
SerialString
String descriptor for Device serial number
Data Sheet S16302EJ3V0DS
8



PD720130
2.2
External Pin Setting
Usually, serial ROM should be used to keep Vendor ID, Product ID and some additional USB related
information. And then, the external pin setting of the
PD720130 is not so important to realize USB to IDE bridge
system. The recommended external pin setting is as follows.
Table 2-2. Recommended External Pin Setting
Pin Name
Setting
MD1
1
MD0
0
SCL
Pull Up
Note 1
SDA
Pull Up
DV1
"L" clamp
DV0
"L" clamp
CLC
"L" clamp
PWR
"L" clamp
DCC
Pull Down
Note 2
GPIO(7:0)
"L" clamp
PIO(14:15)
"L" clamp
PIO5
"L" clamp
SPD
"H" clamp
TEST(3:0)
"L" clamp
SMC
"L" clamp
IRQ0
"L" clamp
Notes 1. If serial ROM size is more than 2 Kbytes, SCL should be pull down.
2. If target IDE device is not fixed, it is preferable that DCC pin can
switch pull-up or pull-down.
The setting for any other pins such as CMB_BSY, CMB_STATE depends on USB2.0 to IDE Bridge system.
For example, if two IDE controllers control one target IDE device and one of two IDE controllers is the
PD720130,
CMB_BSY and CMB_STATE are used to handshake between two IDE controller chips. On the other hand, when
the
PD720130 is only controller of target IDE device, CMB_BSY should be opened and CMB_STATE should be
clamped to "L".
Data Sheet S16302EJ3V0DS
9



PD720130
2.3
Control Bit in Serial ROM or External Pin Setting
The following tables show IDE status and control bit in serial ROM or external pin setting.
Table 2-3. DV1/DV0, CLC, PWR Setting
Setting in Serial ROM or External Pin
No.
Device Power
Internal
Clock
ATA/ATAPI
PWR
CLC
DV1
DV0
0
No device connected
1
1
1
1
1
ATA
1
1
1
0
2
ATAPI
1
1
0
1
3
7.5 MHz
Reserved
1
1
0
0
4
No device connected
1
0
1
1
5
ATA
1
0
1
0
6
ATAPI
1
0
0
1
7
Bus Powered
60 MHz
Reserved
1
0
0
0
8
No device connected
0
1
1
1
9
Combo (ATA)
0
1
1
0
10
Combo (ATAPI)
0
1
0
1
11
Reserved
0
1
0
0
12
No device connected
0
0
1
1
13
ATA
0
0
1
0
14
ATAPI
0
0
0
1
15
Self Powered
60 MHz
Auto device detect
0
0
0
0
Remark
Setting No. 0, 3, 4, 7, 8, 11, and 12 are prohibited to use.
Data Sheet S16302EJ3V0DS
10



PD720130
Table 2-4. DV1/DV0, DCC Setting
Condition
DV1
DV0
Mode
Target
Device
DCC
Pin
Setting
DCC Setting
in Serial
ROM
Description
0
No setting
Ultra, Multi Word DMA are disabled
0
Reset
Ultra, Multi Word DMA are disabled
0
Set
Ultra, Multi Word DMA are enabled.
1
No setting
Ultra, Multi Word DMA are enabled.
1
Reset
Ultra, Multi Word DMA are disabled
1
0
ATA
ATA
1
Set
Ultra, Multi Word DMA are enabled.
0
No setting
Ultra DMA is disabled
0
Reset
Ultra DMA is disabled
0
Set
Ultra, Multi Word DMA are enabled.
1
No setting
Ultra, Multi Word DMA are enabled.
1
Reset
Ultra DMA is disabled
0
1
ATAPI
ATAPI
1
Set
Ultra, Multi Word DMA are enabled.
0
No setting
Ultra, Multi Word DMA are disabled
0
Reset
Ultra, Multi Word DMA are disabled
0
Set
Ultra, Multi Word DMA are enabled.
1
No setting
Ultra, Multi Word DMA are enabled.
1
Reset
Ultra, Multi Word DMA are disabled
ATA
1
Set
Ultra, Multi Word DMA are enabled.
0
No setting
Ultra DMA is disabled
0
Reset
Ultra DMA is disabled
0
Set
Ultra, Multi Word DMA are enabled.
1
No setting
Ultra, Multi Word DMA are enabled.
1
Reset
Ultra DMA is disabled
0
0
Auto
device
detect
ATAPI
1
Set
Ultra, Multi Word DMA are enabled.
Remark
PIO mode 0-4 are always enabled.
Data Sheet S16302EJ3V0DS
11



PD720130
2.4
Combo Mode Function
The
PD720130 can be used to realize that two IDE controller chips control one target IDE device in one
system. To realize IDE bus arbitration between two IDE controller chips, the
PD720130 has CMB_BSY and
CMB_STATE. Combo mode is enabled when PWR = 0 and CLC = 1.
CMB_BSY and CMB_STATE connect to other IDE controller chip as follows.
Figure 2-1. CMB_BSY and CMB_STATE Connection between Two IDE Controller Chips
Other IDE controller
IDE Bus Request
PD720130
CMB_STATE
CMB_BSY
IDE Bus Grant
Table 2-5. Description of CMB_BSY and CMB_STATE
Pin Name
Direction
Value
Description
0
Other IDE controller does not require or does not use IDE bus.
CMB_STATE
IN
1
Other IDE controller requires or is using IDE bus.
0
The
PD720130 does not require or does not use IDE bus.
CMB_BSY
OUT
1
The
PD720130 requires or is using IDE bus.
Data Sheet S16302EJ3V0DS
12



PD720130
The IDE bus arbitration will be done by following sequence. The
PD720130 will confirm whether other
IDE controller requires or is using IDE bus or not. If other IDE controller does not require or does not use IDE
bus, the
PD720130 will use IDE bus.
Figure 2-2. IDE Bus Arbitration Sequence
START
Chip Init
CMB_BSY = 1
CMB_STATE = 1?
CMB_STATE = 0?
CMB_BSY = 0
Yes.
No.
Other IDE controller requires or
is using IDE bus.
No.
IDE bus is used
Yes.
END
The PD720130 can not use IDE bus
by the PD720130
Data Sheet S16302EJ3V0DS
13



PD720130
2.5
Power Control
To realize bus-powered or high performance self-powered USB2.0 to IDE Bridge system, the
PD720130 has
two internal system clock mode. One is 7.5 MHz for bus-powered mode and the other is 60 MHz for self-powered
mode. The
PD720130 controls the power state by events as follows. The word with under line shows event.
The Italic word shows the power state.
Figure 2-3. Power State Control
(a) Bus-powered Mode
Idle Mode
Vbus OFF
Vbus ON
Connect
Set Configuration
Resume
Resume
Suspend
Hardware Reset
Bus Reset
Power OFF
Set Configuration
Resume
Resume
Suspend
Suspend
FS CONNECT
HS CONNECT
Power = P
ENUM_FS
Power = P
ENUM_HS
Suspend
Suspend
Resume
Suspend
Resume
Power = P
FS_B
Power = P
HS_B
Power = P
SPND
Power = P
SPND
Power = P
RESET
HS Enumeration
State
Suspend
Mode
HS Operation
State
FS Operation
State
Configured
State
FS Enumeration
State
Suspend
Mode
Configured
State
Power OFF
Default State
(b) Self-powered Mode
Power = P
SPND
Power ON
Vbus OFF
Vbus ON
Connect
Set Configuration
Resume
Resume
Suspend
Hardware Reset
Bus Reset
Power OFF
Set Configuration
Resume
Resume
Suspend
Suspend
FS CONNECT
HS CONNECT
Power = P
ENUM_FS
Power = P
ENUM_HS
Power = P
COMBO
Suspend
Suspend
Resume
Suspend
Resume
Power = P
FS_S
Power = P
HS_S
Power = P
SPND
Power = P
RESET
CMB_STATE = 0
CMB_STATE = 1
Power OFF
IDE Bus
Release
State
Idle Mode
Default
State
Suspend
Mode
HS Operation
State
Disconnect
Mode
FS Operation
State
Configured
State
FS Enumeration
State
Suspend
Mode
HS Enumeration
State
Configured
State
Data Sheet S16302EJ3V0DS
14



PD720130
To realize bus-powered USB2.0 to IDE Bridge system, the power consumption for IDE device should be
controlled by the power state of the
PD720130. The PD720130 has DPC pin to control IDE device's power
circuit. DPC pin's output level relates to USB device states. DPC should be pull up to 3.3 V because DPC
output becomes high impedance state until the
PD720130 is initialized.
Figure 2-4. DPC Pin to Control IDE Device's Power Circuit
DPC
Power ON
Hardware Reset
Bus Reset
Set
Configuration
Un-configured
Default
Configured
Suspend
Occured
Resume
Occured
Suspend
Configured
Normal
Operation
Normal
Operation
High impedance state
Following reference circuit can cut off power supply to IDE device during the
PD720130 is under default
and un-configured state. Also, the power supply to IDE device is disabled during suspend state, too.
Power consumption of total system under default, un-configured, and suspend state can be reduced by
DPC pin.
Figure 2-5. Power Control Circuit Example
P-Channel Switch
ON
Pull
Up
3.3 V
IN
OUT
Regulator
Power supply rail
IDE Device
Power
DPC
PD720130
Data Sheet S16302EJ3V0DS
15



PD720130
3.
ELECTRICAL SPECIFICATIONS
3.1
Buffer List
2.5 V oscillator interface
XIN, XOUT
3.3 V input buffer
MD(1:0), TEST(3:0), SMC
3.3 V schmitt input buffer
RESETB, IRQ0
3.3 V input buffer with enable (OR type)
DCC, DV(1:0), SPD, CLC, PWR, CMB_STATE
3.3 V I
OL
= 6 mA 3-state output buffer
CMB_BSY, DPC
3.3 V I
OL
= 3 mA bi-directional schmitt buffer with input enable (OR-type)
GPIO(7:0), PIO5, SDA, SCL
3.3 V I
OL
= 6 mA bi-directional buffer with input enable (OR-type)
PIO(15:14)
5 V schmitt input buffer
VBUS
5 V I
OL
= 6 mA 3-state output buffer
IDECS(1:0)B, IDEA(2:0), IDEDAKB, IDEIORB, IDEIOWB, IDERSTB
5 V I
OL
= 6 mA bi-directional buffer with input enable (OR-type)
IDED(15:0), IDEINT, IDEIORDY, IDEDRQ
USB interface
DP, DM, RSDP, RSDM, RREF, RPU
Remark
Above, "5 V" refers to a 3.3 V buffer with 5-V tolerant circuit. Therefore, it is possible to have a 5-V
connection for an external bus, but the output level will be only up to 3.3 V, which is the V
DD33
voltage.
Data Sheet S16302EJ3V0DS
16



PD720130
3.2
Terminology
Terms Used in Absolute Maximum Ratings
Parameter
Symbol
Meaning
Power supply voltage
V
DD33
, V
DD25
Indicates voltage range within which damage or reduced reliability will not result when
power is applied to a V
DD
pin.
Input voltage
V
I
Indicates voltage range within which damage or reduced reliability will not result when
power is applied to an input pin.
Output voltage
V
O
Indicates voltage range within which damage or reduced reliability will not result when
power is applied to an output pin.
Output current
I
O
Indicates absolute tolerance value for DC current to prevent damage or reduced
reliability when a current flows out of or into an output pin.
Operating temperature
T
A
Indicates the ambient temperature range for normal logic operations.
Storage temperature
T
stg
Indicates the element temperature range within which damage or reduced reliability
will not result while no voltage or current are applied to the device.
Terms Used in Recommended Operating Range
Parameter
Symbol
Meaning
Power supply voltage
V
DD33
, V
DD25
Indicates the voltage range for normal logic operations occur when V
SS
= 0 V.
High-level input voltage
V
IH
Indicates the voltage, which is applied to the input pins of the device, is the voltage
indicates that the high level states for normal operation of the input buffer.
* If a voltage that is equal to or greater than the "Min." value is applied, the input
voltage is guaranteed as high level voltage.
Low-level input voltage
V
IL
Indicates the voltage, which is applied to the input pins of the device, is the voltage
indicates that the low level states for normal operation of the input buffer.
* If a voltage that is equal to or lesser than the "Max." value is applied, the input
voltage is guaranteed as low level voltage.
Hysteresys voltage
V
H
Indicates the differential between the positive trigger voltage and the negative trigger
voltage.
Input rise time
t
ri
Indicates allowable input rise time to input pins. Input rise time is transition time from
0.1
V
DD
to 0.9
V
DD
.
Input fall time
t
fi
Indicates allowable input fall time to input pins. Input fall time is transition time from
0.9
V
DD
to 0.1
V
DD
.
Terms Used in DC Characteristics
Parameter
Symbol
Meaning
Off-state output leakage
current
I
OZ
Indicates the current that flows from the power supply pins when the rated power
supply voltage is applied when a 3-state output has high impedance.
Output short circuit current
I
OS
Indicates the current that flows when the output pin is shorted (to GND pins) when
output is at high-level.
Input leakage current
I
I
Indicates the current that flows when the input voltage is supplied to the input pin.
Low-level output current
I
OL
Indicates the current that flows to the output pins when the rated low-level output
voltage is being applied.
High-level output current
I
OH
Indicates the current that flows from the output pins when the rated high-level output
voltage is being applied.
Data Sheet S16302EJ3V0DS
17



PD720130
3.3
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
V
DD33
V
DD25
3.3 V power supply rail
2.5 V power supply rail
-0.5 to +4.6
-0.5 to +3.6
V
V
Input voltage, 5 V buffer
V
I
3.0 V
V
DD33
3.6 V
V
I
< V
DD33
+ 3.0 V
-0.5 to +6.6
V
Input voltage, 3.3 V buffer
V
I
3.0 V
V
DD33
3.6 V
V
I
< V
DD33
+ 1.0 V
-0.5 to +4.6
V
Input voltage, 2.5 V buffer
V
I
2.3 V
V
DD25
2.7 V
V
I
< V
DD25
+ 0.9 V
-0.5 to +3.6
V
Output voltage, 5 V buffer
V
O
3.0 V
V
DD33
3.6 V
V
O
< V
DD33
+ 3.0 V
-0.5 to +6.6
V
Output voltage, 3.3 V buffer
V
O
3.0 V
V
DD33
3.6 V
V
O
< V
DD33
+ 1.0 V
-0.5 to +4.6
V
Output voltage, 2.5 V buffer
V
O
2.3 V
V
DD25
2.7 V
V
O
< V
DD25
+ 0.9 V
-0.5 to +3.6
V
Output current, 5 V buffer
I
O
I
OL
= 6 mA
20
mA
Output current, 3.3 V buffer
I
O
I
OL
= 6 mA
I
OL
= 3 mA
20
10
mA
mA
Operating ambient temperature
T
A
0 to
+70
C
Storage temperature
T
stg
-65 to +150
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameters. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent the
quality assurance range during normal operation.
Two Power Supply Rails Limitation
The
PD720130 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply
rail is stable at V
DD
level. And, there will be difference between the time of V
DD25
and V
DD33
. The
PD720130
requires that V
DD25
should be stable before V
DD33
becomes stable. At this case, the system must ensure that the
absolute maximum ratings for V
I
/ V
O
are not exceeded. System reset signaling should be asserted more than
specified time after both V
DD25
and V
DD33
are stable.
Data Sheet S16302EJ3V0DS
18



PD720130
Recommended Operating Ranges
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating voltage
V
DD33
3.3 V for V
DD33
pins
3.0
3.3
3.6
V
V
DD25
2.5 V for V
DD25
pins
2.3
2.5
2.7
V
V
DD25
2.5 V for AV
DD25
pins
2.3
2.5
2.7
V
High-level input voltage
V
IH
5.0 V high-level input voltage
2.0
5.5
V
3.3 V high-level input voltage
2.0
V
DD33
V
2.5 V high-level input voltage
1.7
V
DD25
V
Low-level input voltage
V
IL
5.0 V low-level input voltage
0
0.8
V
3.3 V low-level input voltage
0
0.8
V
2.5 V low-level input voltage
0
0.7
V
Hysteresis voltage
V
H
5 V hysteresis voltage
0.3
1.5
V
3.3 V hysteresis voltage
0.2
1.0
V
Input rise time
t
ri
Normal buffer
0
200
ns
Schmitt buffer
0
10
ms
Input fall time
t
fi
Normal buffer
0
200
ns
Schmitt buffer
0
10
ms
Data Sheet S16302EJ3V0DS
19



PD720130
DC Characteristics (V
DD33
= 3.0 to 3.6 V, V
DD25
= 2.3 to 2.7 V, T
A
= 0 to
+
+
+
+70C)
Control Pin Block
Parameter
Symbol
Condition
Min.
Max.
Unit
Off-state output current
I
OZ
V
O
= V
DD33,
V
DD25
or V
SS
10
A
Output short circuit current
I
OS
Note
-250
mA
Low-level output current
5.0 V low-level output current
3.3 V low-level output current
3.3 V low-level output current
I
OL
V
OL
= 0.4 V
V
OL
= 0.4 V
V
OL
= 0.4 V
6.0
6.0
3.0
mA
mA
mA
High-level output current
5.0 V high-level output current
3.3 V high-level output current
3.3 V high-level output current
I
OH
V
OH
= 2.4 V
V
OH
= 2.4 V
V
OH
= 2.4 V
-2.0
-6.0
-3.0
mA
mA
mA
Input leakage current
3.3 V buffer
5.0 V buffer
I
I
V
I
= V
DD
or V
SS
V
I
= V
DD
or V
SS
10
10
A
A
Note The output short circuit time is one second or less and is only for one pin on the LSI.
Data Sheet S16302EJ3V0DS
20



PD720130
USB Interface Block
Parameter
Symbol
Conditions
Min.
Max.
Unit
Serial Resistor between DP (DM) and
RSDP (RSDM)
R
S
38.61
39.39
Output pin impedance
Z
HSDRV
Includes R
S
resistor
40.5
49.5
Bus pull-up resistor on upstream facing
port
R
PU
1.5 k
5% consists of
resistance of transistor and
pull-up resistor
1.485
1.515
Termination voltage for upstream facing
port pull-up
V
TERM
3.0
3.6
V
Input Levels for Full-speed:
High-level input voltage (drive)
V
IH
2.0
V
High-level input voltage (floating)
V
IHZ
2.7
3.6
Low-level input voltage
V
IL
0.8
V
Differential input sensitivity
V
DI
(D+) - (D-)
0.2
V
Differential common mode range
V
CM
Includes V
DI
range
0.8
2.5
V
Output Levels for Full-speed:
High-level output voltage
V
OH
R
L
of 14.25 k
to V
SS
2.8
3.6
V
Low-level output voltage
V
OL
R
L
of 1.425 k
to 3.6 V
0.0
0.3
V
SE1
V
OSE1
0.8
V
Output signal crossover point voltage
V
CRS
1.3
2.0
V
Input Levels for High-speed:
High-speed squelch detection threshold
(differential signal)
V
HSSQ
100
150
mV
High-speed disconnect detection threshold
(differential signal)
V
HSDSC
525
625
mV
High-speed data signaling common mode
voltage range
V
HSCM
-50
+500
mV
High-speed differential input signaling level
See Figure 3-4.
Output Levels for High-speed:
High-speed idle state
V
HSOI
-10.0
+10.0
mV
High-speed data signaling high
V
HSOH
360
440
mV
High-speed data signaling low
V
HSOL
-10.0
+10.0
mV
Chirp J level (differential signal)
V
CHIRPJ
700
1100
mV
Chirp K level (differential signal)
V
CHIRPK
-900
-500
mV
Data Sheet S16302EJ3V0DS
21



PD720130
Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed
4.6
-1.0
Input Voltage Range (V)
Differential Input Voltage Range
Differential Output
Crossover
Voltage Range
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Figure 3-2. Full-speed Buffer V
OH
/I
OH
Characteristics for High-speed Capable Transceiver
Max.
Min.
-80
-60
-40
-20
0
V
DD
-0.3
V
OUT
(V)
I
OUT
(mA)
V
DD
-2.3
V
DD
-3.3
V
DD
-0.8
V
DD
V
DD
-1.3
V
DD
-1.8
V
DD
-2.8
Figure 3-3. Full-speed Buffer V
OL
/I
OL
Characteristics for High-speed Capable Transceiver
Max.
Min.
80
60
40
20
0
0
0.5
1
1.5
2
2.5
3
V
OUT
(V)
I
OUT
(mA)
Data Sheet S16302EJ3V0DS
22



PD720130
Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM
0 V
Differential
+400 mV
Differential
-400 mV
Differential
Unit Interval
Level 1
Level 2
0%
100%
Point 5
Point 2
Point 1
Point 3
Point 4
Point 6
Figure 3-5. Receiver Measurement Fixtures
Vbus
D+
D-
Gnd
15.8
+
To 50
Inputs of a
High Speed Differential
Oscilloscope, or 50
Outputs of a High Speed
Differential Data Generator
-
50
Coax
50
Coax
USB
Connector
Nearest
Device
Test Supply Voltage
15.8
143
143
Pin Capacitance
Parameter
Symbol
Condition
Min.
Max.
Unit
Input capacitance
C
IN
4
6
pF
Output capacitance
C
OUT
4
6
pF
I/O capacitance
C
IO
V
DD
= 0 V, T
A
= 25C
f
C
= 1 MHz
Unmeasured pins returned to 0 V
4
6
pF
Data Sheet S16302EJ3V0DS
23



PD720130
Power Consumption
(1) The power consumption when device works as bus-powered mode
Symbol
Condition
Max.
Unit
V
DD25
V
DD33
AV
DD25
The power consumption under unconfigured stage
P
ENUM-BUS
High-speed operating
Full-speed operating
57
23
3
4
10
10
mA
mA
The power consumption when device works
P
W-BUS
High-speed operating
Full-speed operating
110
113
22
13
10
10
mA
mA
P
W_SPD-BUS
The power consumption under suspend state
10
235
5
A
(2) The power consumption when device works as self-powered mode
Symbol
Condition
Max.
Unit
V
DD25
V
DD33
AV
DD25
The power consumption under unconfigured stage
P
ENUM-SELF
High-speed operating
Full-speed operating
85
60
5
5
10
10
mA
mA
The power consumption when device works
P
W-SELF
High-speed operating
Full-speed operating
120
113
25
13
10
10
mA
mA
P
W_SPD-SELF
The power consumption under suspend state
50
5
5
mA
P
W_UNP
The power consumption under unplug state
87
3
10
mA
P
W_COM
The power consumption under combo mode
The device is releasing the IDE bus.
90
5
10
mA
Data Sheet S16302EJ3V0DS
24



PD720130
AC Characteristics (V
DD33
= 3.0 to 3.6 V, V
DD25
= 2.3 to 2.7 V, T
A
= 0 to
+
+
+
+70C)
System Clock Ratings
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
X'tal
-500
ppm
30
+500
ppm
MHz
Clock frequency
f
CLK
Oscillator block
-500
ppm
30
+500
ppm
MHz
Clock duty cycle
t
DUTY
45
50
55
%
Remarks 1. Recommended accuracy of clock frequency is
100 ppm.
2. Required accuracy of X'tal or Oscillator block is including initial frequency accuracy, the spread of
X'tal capacitor loading, supply voltage, temperature, and aging, etc.
System Reset signaling
Parameter
Symbol
Conditions
Min.
Max.
Unit
Reset active time
t
rst
2
s
USB Interface Block
(1/2)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Full-speed Source Electrical Characteristics
Rise time (10% - 90%)
t
FR
C
L
= 50 pF,
R
S
= 36
4
20
ns
Fall time (90% - 10%)
t
FF
C
L
= 50 pF,
R
S
= 36
4
20
ns
Differential rise and fall time matching
t
FRFM
(t
FR
/t
FF
)
90
111.11
%
Full-speed data rate for device which are
high-speed capable
t
FDRATHS
Average bit rate
11.9940
12.0060
Mbps
Frame interval
t
FRAME
0.9995
1.0005
ms
Consecutive frame interval jitter
t
RFI
No clock adjustment
42
ns
Source jitter total (including frequency
tolerance):
To next transition
For paired transitions
t
DJ1
t
DJ2
-3.5
-4.0
+3.5
+4.0
ns
ns
Source jitter for differential transition to
SE0 transition
t
FDEOP
-2
+5
ns
Receiver jitter:
To next transition
For paired transitions
t
JR1
t
JR2
-18.5
-9
+18.5
+9
ns
ns
Source SE0 interval of EOP
t
FEOPT
160
175
ns
Receiver SE0 interval of EOP
t
FEOPR
82
ns
Width of SE0 interval during differential
transition
t
FST
14
ns
Data Sheet S16302EJ3V0DS
25



PD720130
(2/2)
Parameter
Symbol
Conditions
Min.
Max.
Unit
High-speed Source Electrical Characteristics
Rise time (10% - 90%)
t
HSR
500
ps
Fall time (90% - 10%)
t
HSF
500
ps
Driver waveform
See Figure 3-6.
High-speed data rate
t
HSDRAT
479.760
480.240
Mbps
Microframe interval
t
HSFRAM
124.9375
125.0625
s
Consecutive microframe interval difference
t
HSRFI
4 high-
speed
Bit
times
Data source jitter
See Figure 3-6.
Receiver jitter tolerance
See Figure 3-4.
Device Event Timings
Time from internal power good to device
pulling D+ beyond V
IHZ
(min.) (signaling
attached)
t
SIGATT
100
ms
Debounce interval provided by USB
system software after attach
t
ATTDB
100
ms
Inter-packet delay for full-speed
t
IPD
2
Bit
times
Inter-packet delay for device response
w/detachable cable for full-speed
t
RSPIPD1
6.5
Bit
times
High-speed detection start time from
suspend
t
SCA
2.5
s
Sample time for suspend vs reset
t
CSR
100
875
s
Time to detect bus suspend state
t
SPD
3.000
3.125
ms
Power down under suspend
t
SUS
10
ms
Reversion time from suspend to high-
speed
t
RHS
1.333
s
Drive Chirp K width
t
CKO
1
ms
Finish Chirp K assertion
t
FCA
7
ms
Start sequencing Chirp K-J-K-J-K-J
t
SSC
100
s
Finish sequencing Chirp K-J
t
FSC
-500
-100
s
Detect sequencing Chirp K-J width
t
CSI
2.5
s
Sample time for sequencing Chirp
t
SCS
1
2.5
ms
Reversion time to high-speed
t
RHA
500
s
High-speed detection start time
t
HDS
2.5
3000
s
Reset completed time
t
DRS
10
ms
Data Sheet S16302EJ3V0DS
26



PD720130
IDE Interface Block
PIO mode
Parameter
Symbol
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Unit
Cycle time (min.)
t
0
600
383
240
180
120
ns
Address setup time (min.)
t
1
70
50
30
30
25
ns
16 bits DIOR/DIOW pulse width (min.)
t
2
165
125
100
80
70
ns
8 bits DIOR/DIOW pulse width (min.)
290
290
290
80
70
ns
DIOR/DIOW recovery time (min.)
t
2i
-
-
-
70
25
ns
DIOW data setup time (min.)
t
3
60
45
30
30
20
ns
DIOW data hold time (min.)
t
4
30
20
15
10
10
ns
DIOR data setup time (min.)
t
5
50
35
20
20
20
ns
DIOR data hold time (min.)
t
6
5
5
5
5
5
ns
DIOR 3-state delay time (max.)
t
6Z
30
30
30
30
30
ns
Address hold time (min.)
t
9
20
15
10
10
10
ns
IORDY read data valid time (min.)
Note
t
RD
0
0
0
0
0
ns
IORDY setup time (min.)
Note
t
A
35
35
35
35
35
ns
IORDY pulse width (max.)
Note
t
B
1250
1250
1250
1250
1250
ns
IORDY Inactive to Hi-Z time (max.)
Note
t
C
5
5
5
5
5
ns
Note IORDY is an option in mode 0 - 2. IORDY is essential in modes 3 and 4.
Multi Word DMA mode
Parameter
Symbol
Mode 0
Mode 1
Mode 2
Unit
Cycle time (min.)
t
0
480
150
120
ns
DIOR/DIOW pulse width (min.)
t
D
215
80
70
ns
DIOR data access time (max.)
t
E
150
60
50
ns
DIOR data hold time (min.)
t
F
5
5
5
ns
DIOR data setup time (min.)
t
Gr
100
30
20
ns
DIOW data setup time (min.)
t
Gw
100
30
20
ns
DIOW data hold time (min.)
t
H
20
15
10
ns
DMACK setup time (min.)
t
I
0
0
0
ns
DMACK hold time (min.)
t
J
20
5
5
ns
DIOR negate pulse width (min.)
t
Kr
50
50
25
ns
DIOW negate pulse width (min.)
t
Kw
215
50
25
ns
DIOR-DMARQ delay time (max.)
t
Lr
120
40
35
ns
DIOW-DMARQ delay time (max.)
t
Lw
40
40
35
ns
DMACK 3-state delay time (max.)
t
Z
20
25
25
ns
CS setup time (min.)
t
M
50
30
25
ns
CS hold time (min.)
t
N
15
10
10
ns
Data Sheet S16302EJ3V0DS
27



PD720130
Ultra DMA mode
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Average cycle time for 2 cycles
t
2CYC
240
-
160
-
120
-
90
-
60
-
ns
Minimum cycle time for 2 cycles
t
2CYC
235
-
156
-
117
-
86
-
57
-
ns
Cycle time for 1 cycle
t
CYC
114
-
75
-
55
-
39
-
25
-
ns
Data setup time on receive side
t
DS
15
-
10
-
7
-
7
-
5
-
ns
Data hold time on receive side
t
DH
5
-
5
-
5
-
5
-
5
-
ns
Data setup time on transmit side
t
DVS
70
-
48
-
34
-
20
-
6
-
ns
Data hold time on transmit side
t
DVH
6
-
6
-
6
-
6
-
6
-
ns
First STROBE time
t
FS
0
230
0
200
0
170
0
130
0
120
ns
Interlock time with limitation
t
LI
0
150
0
150
0
150
0
100
0
100
ns
Minimum interlock time
t
MLI
20
-
20
-
20
-
20
-
20
-
ns
Interlock time without limitation
t
UI
0
-
0
-
0
-
0
-
0
-
ns
Output release time
t
AZ
-
10
-
10
-
10
-
10
-
10
ns
Output delay time
t
ZAH
20
-
20
-
20
-
20
-
20
-
ns
Output stabilization time
(from release)
t
ZAD
0
-
0
-
0
-
0
-
0
-
ns
Envelope time
t
ENV
20
70
20
70
20
70
20
55
20
55
ns
STROBE DMARDY delay time
t
SR
-
50
-
30
-
20
-
NA
-
NA
ns
Last STROBE time
t
RFS
-
75
-
60
-
50
-
60
-
60
ns
Pause time
t
RP
160
-
125
-
100
-
100
-
100
-
ns
IORDY pull-up time
t
IORYZ
-
20
-
20
-
20
-
20
-
20
ns
IORDY wait time
t
ZIORY
0
-
0
-
0
-
0
-
0
-
ns
DMACK setup/hold time
t
ACK
20
-
20
-
20
-
20
-
20
-
ns
STROBE STOP time
t
SS
50
-
50
-
50
-
50
-
50
-
ns
Data Sheet S16302EJ3V0DS
28



PD720130
Serial ROM interface Block
Parameter
Symbol
Conditions
Min.
Max.
Unit
Clock frequency
t
SCL
100
KHz
Clock pulse width low
t
LOW
4.7
s
Clock pulse width high
t
HIGH
4.0
s
Clock Low to data valid
t
AA
100
4500
ns
Start hold time
t
HD.STA
4.0
s
Start setup time
t
SU.STA
4.7
s
Data in hold time
t
HD.DAT
0
ns
Data in setup time
t
SU.DAT
0.2
s
Data out hold time
t
DH
50
ns
Stop setup time
t
SU.STO
4.7
s
Time the bus must be free before a new
transmission can start
t
BUF
10
s
Write cycle time
t
WR
10
ms
Data Sheet S16302EJ3V0DS
29



PD720130
Figure 3-6. Transmit Waveform for Transceiver at DP/DM
0 V
Differential
+400 mV
Differential
-400 mV
Differential
Unit Interval
Level 1
Level 2
0%
100%
Point 4
Point 3
Point 1
Point 2
Point 5
Point 6
Figure 3-7. Transmitter Measurement Fixtures
Vbus
D+
D-
Gnd
15.8
+
To 50
Inputs of a
High Speed Differential
Oscilloscope, or 50
Outputs of a High Speed
Differential Data Generator
-
50
Coax
50
Coax
USB
Connector
Nearest
Device
Test Supply Voltage
15.8
143
143
Data Sheet S16302EJ3V0DS
30



PD720130
Timing Diagram
System reset timing
RESETB
t
rst
Remark
After RESET is negated, this chip read the serial ROM first. Do not reset while the serial ROM is read. The
serial ROM is completed to read below time, after RESET is negated.
5
+ 0.1197 bytes (serial ROM size) + 0.5678 (ms)
Example In the case of 512 bytes: 66.855 ms, in the case of 8 Kbytes: 986.15 ms
USB power-on and connection events
t
SIGATT
D
+
or
D
-
Hub port
power OK
Attatch detected
Reset recovery
time
USB system software
reads device speed
4.01 V
V
BUS
V
IH(min)
V
IH
Hub port
power-on
10 ms
t
ATTDB
USB differential data jitter for full-speed
t
PERIOD
Differential
Data Lines
Crossover
Points
Consecutive
Transitions
N
t
PERIOD
+ t
DJ1
Paired
Transitions
N
t
PERIOD
+ t
DJ2
Data Sheet S16302EJ3V0DS
31



PD720130
USB differential-to-EOP transition skew and EOP width for full-speed
t
PERIOD
Differential
Data Lines
Crossover
Point
Crossover
Point Extended
Source EOP Width: t
FEOPT
Receiver EOP Width: t
FEOPR
Diff. Data-to-
SE0 Skew
N
t
PERIOD
+ t
FDEOP
USB receiver jitter tolerance for full-speed
Differential
Data Lines
t
PERIOD
t
JR
t
JR1
t
JR2
Consecutive
Transitions
N
t
PERIOD
+ t
JR1
Paired
Transitions
N
t
PERIOD
+ t
JR2
USB connection sequence on full-speed system bus
t
HDS
t
SCA
t
CKO
t
SCS
t
FCA
t
DRS
Chirp K device out
Reversion to full-speed mode
FSJ
FSJ
Pull-up is active.
T
0
USB bus
USB connection sequence on high-speed system bus
t
HDS
t
SCA
t
CKO
t
SCS
t
FCA
Chirp K device out
Reset Complete
FSJ
Pull-up is active.
T
0
USB bus
t
SSC
t
CSI
t
RHA
t
FSC
Chirp state from host/hub
Reversion to high-speed mode
K
K
J
J
K
J
K
J
Data Sheet S16302EJ3V0DS
32



PD720130
USB reset sequence from suspend state on full-speed system bus
t
SCA
t
CKO
t
SCS
t
FCA
t
DRS
Chirp K device out
FSJ
FSJ
Pull-up is active.
T
0
USB bus
USB reset sequence from suspend state on high-speed system bus
t
SCA
t
CKO
t
SCS
t
FCA
Chirp K device out
Reversion to high-speed mode
FSJ
Pull-up is active.
T
0
USB bus
t
SSC
t
CSI
t
RHA
t
FSC
Chrip state from host/hub
Reset Complete
K
K
J
K
K
J
J
J
USB suspend and resume on full-speed system bus
USB bus
FSJ
FSJ
FSK
FS EOP
t
SUS
Power will be down
Note time required to relock PLL
and stabilize oscillator.
t
SPD
USB suspend and resume on high-speed system bus
USB bus
FSJ
FSK
High-speed packet
t
SPD
t
t
SUS
Power will be down
Note time required to relock PLL
and stabilize oscillator.
t
CSR
Reversion to full-speed mode
t
RHS
High-speed packet
Reversion to high-speed mode
T
0
Data Sheet S16302EJ3V0DS
33



PD720130
IDE PIO mode timing
t
1
IDECS1B, IDECS0B
IDEEA2-IDEEA0
IDEIORB
IDEIOWB
IDED15-IDED0
IDED15-IDED0
IDEIORDY
H
L
H
L
H
L
H
L
H
L
t
0
t
2
t
4
t
2i
t
5
t
6
t
6Z
t
3
t
A
t
9
t
C
t
RD
t
B
(WRITE)
(READ)
IDE multi word DMA mode timing
t
0
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDEIORB
IDEIOWB
IDED15-IDED0
(READ)
IDED15-IDED0
(WRITE)
H
L
t
Kr
/t
Kw
t
M
t
Z
t
D
t
E
t
F
t
Gr
t
H
t
I
t
J
t
Gw
t
Lr
/t
Lw
t
N
IDECS1B, IDECS0B
IDE ultra DMA mode data-in timing
t
ACK
CRC
t
2CYC
t
CYC
t
DVS
t
DVH
t
FS
t
CYC
t
AZ
t
ZIORY
t
ACK
t
IORYZ
t
SS
t
LI
t
MLI
t
UI
t
ZAD
t
ZAH
t
ENV
t
LI
t
LI
t
AZ
t
DVH
t
DVS
t
ZAD
t
FS
t
ENV
t
ACK
t
ACK
t
ACK
t
ACK
t
ACK
t
ACK
H
L
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDED15-IDED0
H
L
IDEIOWB
(STOP)
IDEIORDY
(HDMARDY)
IDEIORB
(DSTROBE)
IDEA2-IDEA0
H
L
IDECS1B, IDECS0B
Data
Data
Data
Data Sheet S16302EJ3V0DS
34



PD720130
IDE ultra DMA mode data-in stop timing
t
SR
t
RP
t
RFS
H
L
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDED15-IDED0
IDEIOWB
(STOP)
IDEIORB
(HDMARDY)
IDEIORDY
(DSTROBE)
IDE ultra DMA mode data-in end timing
CRC
t
RPS
t
IORYZ
t
RP
t
LI
t
MLI
t
ZAH
t
DVH
t
DVS
t
ACK
t
AZ
t
ACK
t
LI
t
MLI
t
ACK
H
L
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDED15-IDED0
H
L
IDEIOWB
(STOP)
IDEIORB
(HDMARDY)
IDEIORDY
(DSTROBE)
IDECS1B, IDECS0B
IDEA2-IDEA0
IDE ultra DMA mode data-out timing
t
RFS
t
RP
t
ACK
t
UI
t
ACK
t
ACK
t
ACK
t
ACK
t
ACK
t
LI
t
ENV
t
UI
t
LI
t
MLI
t
ACK
t
ACK
t
ZIORY
t
DVS
t
DVH
t
2CYC
t
CYC
t
CYC
t
DVS
t
DVH
t
IORYZ
t
MLI
t
LI
H
L
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDED15-IDED0
H
L
IDEIOWB
(STOP)
IDEIORDY
(DDMARDY)
IDEIORB
(HSTROBE)
IDEA2-IDEA0
H
L
IDECS1B, IDECS0B
Data
Data
Data
CRC
Data Sheet S16302EJ3V0DS
35



PD720130
IDE ultra DMA mode data-out stop timing
t
SR
t
RP
t
RFS
H
L
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDED15-IDED0
IDEIOWB
(STOP)
IDEIORB
(HDMARDY)
IDEIORDY
(DSTROBE)
IDE ultra DMA mode data-out end timing
H
L
H
L
H
L
H
L
H
L
H
L
IDEDRQ
IDEDAKB
IDED15-IDED0
H
L
CRC
t
IORYZ
t
SS
t
LI
t
MLI
t
DVH
t
DVS
t
ACK
IDEIOWB
(STOP)
IDEIORB
(HDMARDY)
IDEIORDY
(DSTROBE)
IDECS1B, IDECS0B
IDEA2-IDEA0
t
LI
t
ACK
t
ACK
t
LI
IDE ultra DMA mode data skew timing
xSTROBE
DD0
:
:
DD15
t
2CYC
t
CYC
t
DVS
t
DVH
Data
Data
Data
t
DS
t
DH
IDEIORB
(Output side)
IDED15-IDED0
(Output side)
Output side
Input side
Delay, skew, etc., by cable
IDEIORDY
(Input side)
IDED15-IDED0
(Input side)
H
L
H
L
H
L
H
L
t
CYC
Data Sheet S16302EJ3V0DS
36



PD720130
Serial ROM access timing
SCL
SDA
(Output)
SDA
(Input)
t
SU.STA
t
HD.STA
t
SU.DAT
t
HIGH
t
LOW
t
LOW
t
HD.DAT
t
AA
t
DH
t
SU.STO
t
BUF
Serial ROM write cycle timing
PIO1
PIO0
Word n
8th bit
ACK
Stop
condition
Start
condition
t
WR
Data Sheet S16302EJ3V0DS
37



PD720130
4.
PACKAGE DRAWING
PD720130GC-9EU
75
76
50
100
1
26
25
51
S
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
ITEM
MILLIMETERS
B
14.0
0.2
D
16.0
0.2
F
1.0
G
1.0
A
16.0
0.2
C
14.0
0.2
H
0.22
0.05
I
0.08
J
K
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
1.0
0.2
0.5 (T.P.)
A
R
detail of lead end
S
M
H
I
G
F
B
C
D
L
0.5
N
0.08
P
1.0
Q
0.1
0.05
P100GC-50-9EU
M
0.17+0.03
-0.07
S
1.1
0.1
T
0.25
U
0.6
0.15
R
3
+4
-3
K
J
P
Q
L
U
T
M
S
N
Data Sheet S16302EJ3V0DS
38



PD720130
PD720130GC-9EU-SIN
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
16.0
0.2
14.0
0.2
0.5 (T.P.)
1.0
J
16.0
0.2
K
C
14.0
0.2
I
0.10
1.0
0.2
L
0.5
0.2
F
1.0
N
P
Q
0.10
1.0
0.1
0.1
0.05
S100GC-50-9EU-2
S
1.27 MAX.
H
0.22+0.05
-0.04
M
0.145+0.055
-0.045
R
3
+7
-3
75
76
50
100
1
26
25
51
S
N
J
detail of lead end
C
D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
Data Sheet S16302EJ3V0DS
39



PD720130
5.
RECOMMENDED SOLDERING CONDITIONS
The
PD720130 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)



PD720130GC-9EU: 100-pin plastic TQFP (Fine pitch) (14 14)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher),
Count: Two times or less
Exposure limit: 3 days
Note
(after that, prebake at 125C for 10 hours)
IR35-103-2
Partial heating
Pin temperature: 300C max., Time: 3 seconds or less (per pin row)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.



PD720130GC-9EU-SIN: 100-pin plastic TQFP (Fine pitch) (14 14)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher),
Count: Two times or less
Exposure limit: 3 days
Note
(after that, prebake at 125C for 10 hours)
IR35-103-2
Partial heating
Pin temperature: 300C max., Time: 3 seconds or less (per pin row)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Data Sheet S16302EJ3V0DS
40



PD720130
[MEMO]
Data Sheet S16302EJ3V0DS
41



PD720130
[MEMO]
Data Sheet S16302EJ3V0DS
42



PD720130
[MEMO]
Data Sheet S16302EJ3V0DS
43



PD720130
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.



PD720130
EEPROM is a trademark of NEC Electronics Corporation.
USB logo is a trademark of USB Implementers Forum, Inc.
The information in this document is current as of June, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
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representative for availability and additional information.
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(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
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"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
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"Standard":
"Special":
"Specific":