Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATION (TOP VIEW)
- PIN NAMES
- INTERNAL BLOCK DIAGRAM
- 1. PIN FUNCTIONS
- 1.1 Port Pins
- 1.2 Non-Port Pins
- 1.3 Pin I/O Circuits and Processing of Unused Pins
- 2. INTERNAL UNITS
- 2.1 Bus Interface Unit (BIU)
- 2.2 Wait Control Unit (WCU)
- 2.3 DRAM Controller (DRAMC)
- 2.4 ROM Controller (ROMC)
- 2.5 Interrupt Controller
- 2.6 DMA Controller (DMAC)
- 2.7 Serial Interfaces (UART/CSI)
- 2.8 Real-Time Pulse Unit (RPU)
- 2.9 Watchdog Timer (WDT)
- 2.10 Clock Generator (CG)
- 2.11 Bus Arbitration Unit (BAU)
- 2.12 Port
- 3. CPU FUNCTIONS
- 3.1 Features
- 3.2 Address Space
- 3.2.1 Memory map
- 3.2.2 I/O map
- 3.3 CPU Register Set
- 3.3.1 Program register set
- 3.3.2 System register set
- 3.4 Built-in Peripheral I/O Registers
- 3.5 Data Types
- 3.5.1 Data types
- 3.5.2 Data alignment
- 3.6 Cache
- 4. INTERRUPT/EXCEPTION HANDLING FUNCTIONS
- 5. WAIT CONTROL FUNCTIONS
- 6. MEMORY ACCESS CONTROL FUNCTIONS
- 6.1 DRAM Controller (DRAMC)
- 6.1.1 Features
- 6.1.2 Address multiplexing function
- 6.1.3 Refresh function
- 6.1.4 Self-refresh function
- 6.2 ROM Controller (ROMC)
- 6.2.1 on-page/off-page decision
- 7. DMA FUNCTIONS (DMA CONTROLLER)
- 8. SERIAL INTERFACE FUNCTION
- 8.1 Features
- 8.2 Asynchronous Serial Interface (UART)
- 8.3 Synchronous Serial Interface (CSI)
- 8.4 Baud Rate Generator (BRG)
- 8.4.1 Configuration and function
- 9. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
- 10. WATCHDOG TIMER FUNCTIONS
- 10.1 Features
- 10.2 Operation
- 11. PORT FUNCTIONS
- 12. CLOCK GENERATION FUNCTIONS
- 13. STANDBY FUNCTIONS
- 13.1 Features
- 13.2 Standby Mode
- 14. RESET FUNCTIONS
- 14.1 Features
- 14.2 Pin Functions
- 15. INSTRUCTION SET
- 15.1 Instruction Format
- 15.2 Instruction Mnemonic (In Alphabetical Order)
- 16. ELECTRICAL SPECIFICATIONS
- 17. PACKAGE DRAWINGS
- 18. RECOMMENDED SOLDERING CONDITIONS
DATA SHEET
MOS INTEGRATED CIRCUIT
PD70741
V821
TM
32-/16-BIT MICROPROCESSOR
The
PD70741 (V821) is a 32/16-bit RISC microprocessor that uses, as its processor core, the high-
performance 32-bit microprocessor
PD70732 (V810
TM
) designed for built-in control applications. It incorporates
peripheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serial
interface, and interrupt controller.
The V821, which offers quick real-time response, high-speed integer instructions, bit string instructions, and
floating-point instructions, is ideally suited to use in OA equipment such as printers and facsimiles, image
processing devices such as those used in navigation units, portable devices, and other devices demanding
excellent cost performance.
The functions are described in detail in the following User's Manuals, which should be read before
starting design work.
V821 User's Manual Hardware
: U10077E
V810 Family
TM
User's Manual Architecture : U10082E
FEATURES
The V810 32-bit microprocessor is used as the CPU core
Separate address/data bus
Address bus : 24 bits
Data bus
: 16 bits
Built-in 1-Kbyte instruction cache memory
Pipeline structure of 1-clock pitch
Internal 4-Gbyte linear address space
32-bit general-purpose registers: 32
Instructions ideal for various application fields
Floating-point operation instructions and bit string
instructions
Interrupts controller
Nonmaskable : 1 external input
Maskable
: 8 external inputs and 11 types of
internal sources
Priorities can be specified in units of four groups.
Wait control unit
Capable of CS control over four blocks in both memory
and I/O spaces.
Linear address space of each block: 16M bytes
Memory access control functions
Supports DRAM high-speed page mode.
Supports page-ROM page mode.
DMA controller (DMAC): 2 channels
Maximum transfer count: 65 536
Two transfer types (fly-by (1-cycle) transfer and
2-cycle transfer)
Three transfer modes (single transfer, single-
step transfer, and block transfer)
Serial interfaces : 2 channels
Asynchronous serial interface (UART):
1 channel
Synchronous serial interface (CSI):
1 channel
Real-time pulse unit
16-bit timer/event counter : 1 channel
16-bit interval timer
: 1 channel
Watchdog timer functions
Clock generator functions
Standby functions (HALT, IDLE, and STOP modes)
The information in this document is subject to change without notice.
The mark shows major revised points.
Document No. U11678EJ4V0DS00 (4th edition)
Date Published June 1998 J CP(K)
Printed in Japan
1996
PD70741
2
ORDERING INFORMATION
Part number
Package
PD70741GC-25-8EU
100-pin plastic LQFP (fine pitch) (14
14
1.40 mm)
PIN CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch) (14
14 mm)
PD70741GC-25-8EU
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
D15
D14
D13
D12
D11
D10
D9
D8
GND
V
DD
D7
D6
D5
D4
D3
D2
D1
D0
IC
RESET
INTP10
INTP11
INTP12
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
V
DD
RAS
UMWR
LMWR/WE
MRD
READY
CS0/REFRQ
CS1
CS2
CS3
A12
A13
A14
A15
A16
GND
V
DD
A17
A18
A19
A20
A21
A22
A23
V
DD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
LCAS
UCAS
GND
X1
X2
V
DD
CLKOUT
V
DD
GND
A11
A10
A9
A8
A7
A6
GND
V
DD
A5
A4
A3
A2
A1
A0
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
IORD
IOWR
NMI
HLDRQ
HLDAK
RXD/P09/TC
TXD/P08/UBE
SCLK/P07
SO/P06
SI/P05
DACK1/P04
DREQ1/P03
DACK0/P02
DREQ0/P01
GND
V
DD
TCLR/P00
BLOCK/WDTOUT
INTP03
INTP02/TO01
INTP01
INTP00/TO00
INTP13/TI
V
DD
Caution Connect the IC pin to GND through a resistor.
PD70741
3
PIN NAMES
A0-A23
: Address Bus
BLOCK
: Bus Lock
CLKOUT
: System Clock Out
CS0-CS3
: Chip Select
D0-D15
: Data Bus
DACK0, DACK1
: DMA Acknowledge
DREQ0, DREQ1
: DMA Request
HLDAK
: Hold Acknowledge
HLDRQ
: Hold Request
INTP00-INTP03, INTP10-INTP13
: Interrupt Request
IORD
: I/O Read
IOWR
: I/O Write
LCAS
: Lower Column Address Strobe
LMWR
: Lower Memory Write
MRD
: Memory Read
NMI
: Non-maskable Interrupt Request
P00-P09
: Port
RAS
: Row Address Strobe
READY
: Ready
REFRQ
: Refresh Request
RESET
: Reset
RXD
: Receive Data
SCLK
: Serial Clock
SI
: Serial Input
SO
: Serial Output
TC
: Terminal Count
TCLR
: Timer Clear
TI
: Timer Input
TO00, TO01
: Timer Output
TXD
: Transmit Data
UBE
: Upper Byte Enable
UCAS
: Upper Column Address Strobe
UMWR
: Upper Memory Write
WDTOUT
: Watchdog Timer Output
WE
: Write Enable
X1, X2
: Crystal Oscillator
PD70741
4
INTERNAL BLOCK DIAGRAM
V821
CLKOUT
TI
TO00,TO01
TCLR
INTP00-INTP03,
INTP10-INTP13
TXD
RXD
SCLK
SI
SO
PORT00-PORT09
NMI
RPU
4
ICU
CSI
UART
PORT
BIU
DRAMC
ROMC
WCU/CS
DMAC
BAU
WDT
CG
CPU
(V810)
X1
X2
RESET
WDTOUT
HLDAK
HLDRQ
DREQ0, DREQ1
DACK0, DACK1
TC
A0-A23
D0-D15
RAS
UBE
UCAS
LCAS
WE
REFRQ
MRD
IORD
IOWR
LMWR
UMWR
READY
CS0-CS3
PD70741
5
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
8
1.1
Port Pins .........................................................................................................................................
8
1.2
Non-Port Pins .................................................................................................................................
8
1.3
Pin I/O Circuits and Processing of Unused Pins ......................................................................
10
2.
INTERNAL UNITS ......................................................................................................................
12
2.1
Bus Interface Unit (BIU) ................................................................................................................
12
2.2
Wait Control Unit (WCU) ...............................................................................................................
12
2.3
DRAM Controller (DRAMC) ...........................................................................................................
12
2.4
ROM Controller (ROMC) ................................................................................................................
12
2.5
Interrupt Controller ........................................................................................................................
12
2.6
DMA Controller (DMAC) ................................................................................................................
12
2.7
Serial Interfaces (UART/CSI) ........................................................................................................
12
2.8
Real-Time Pulse Unit (RPU) .........................................................................................................
12
2.9
Watchdog Timer (WDT) .................................................................................................................
13
2.10
Clock Generator (CG) ....................................................................................................................
13
2.11
Bus Arbitration Unit (BAU) ...........................................................................................................
13
2.12
Port ..................................................................................................................................................
13
3.
CPU FUNCTIONS .......................................................................................................................
14
3.1
Features ..........................................................................................................................................
14
3.2
Address Space ...............................................................................................................................
14
3.2.1
Memory map ...................................................................................................................
15
3.2.2
I/O map ............................................................................................................................
16
3.3
CPU Register Set ...........................................................................................................................
17
3.3.1
Program register set .....................................................................................................
18
3.3.2
System register set ........................................................................................................
19
3.4
Built-in Peripheral I/O Registers ..................................................................................................
20
3.5
Data Types ......................................................................................................................................
23
3.5.1
Data types .......................................................................................................................
23
3.5.2
Data alignment ...............................................................................................................
25
3.6
Cache ...............................................................................................................................................
26
4.
INTERRUPT/EXCEPTION HANDLING FUNCTIONS ...............................................................
27
4.1
Features ..........................................................................................................................................
27
5.
WAIT CONTROL FUNCTIONS ..................................................................................................
30
5.1
Features ..........................................................................................................................................
30
PD70741
6
6.
MEMORY ACCESS CONTROL FUNCTIONS ..........................................................................
32
6.1
DRAM Controller (DRAMC) ...........................................................................................................
32
6.1.1
Features ..........................................................................................................................
32
6.1.2
Address multiplexing function ....................................................................................
32
6.1.3
Refresh function ............................................................................................................
33
6.1.4
Self-refresh function ......................................................................................................
33
6.2
ROM Controller (ROMC) ................................................................................................................
33
6.2.1
on-page/off-page decision ............................................................................................
33
7.
DMA FUNCTIONS (DMA CONTROLLER) ...............................................................................
35
7.1
Features ..........................................................................................................................................
35
8.
SERIAL INTERFACE FUNCTION .............................................................................................
37
8.1
Features ..........................................................................................................................................
37
8.2
Asynchronous Serial Interface (UART) ......................................................................................
37
8.2.1
Features ..........................................................................................................................
37
8.3
Synchronous Serial Interface (CSI) .............................................................................................
39
8.3.1
Features ..........................................................................................................................
39
8.4
Baud Rate Generator (BRG) .........................................................................................................
40
8.4.1
Configuration and function ..........................................................................................
40
9.
TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) .................................................
41
9.1
Features ..........................................................................................................................................
41
10. WATCHDOG TIMER FUNCTIONS ............................................................................................
43
10.1
Features ..........................................................................................................................................
43
10.2
Operation ........................................................................................................................................
44
11. PORT FUNCTIONS ....................................................................................................................
45
11.1
Features ..........................................................................................................................................
45
12. CLOCK GENERATION FUNCTIONS ........................................................................................
46
12.1
Features ..........................................................................................................................................
46
13. STANDBY FUNCTIONS .............................................................................................................
47
13.1
Features ..........................................................................................................................................
47
13.2
Standby Mode ................................................................................................................................
47
14. RESET FUNCTIONS ..................................................................................................................
49
14.1
Features ..........................................................................................................................................
49
14.2
Pin Functions .................................................................................................................................
49
15. INSTRUCTION SET ....................................................................................................................
50
15.1
Instruction Format .........................................................................................................................
50
15.2
Instruction Mnemonic (In Alphabetical Order) ..........................................................................
52
PD70741
7
16. ELECTRICAL SPECIFICATIONS ..............................................................................................
62
17. PACKAGE DRAWINGS ............................................................................................................. 107
18. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 108
PD70741
8
(1/2)
1. PIN FUNCTIONS
1.1 Port Pins
Pin name
Input/output
Function
Dual-function pin
P00
Input/output
Port 0
TCLR
P01
10-bit input/output port
DREQ0
P02
Can be set for input/output bit.
DACK0
P03
DREQ1
P04
DACK1
P05
SI
P06
SO
P07
SCLK
P08
TXD/UBE
P09
RXD/TC
Remark After a reset is released, each port pin is set as an input port pin.
1.2 Non-Port Pins
Pin name
Input/output
Function
Dual-function pin
A0-A23
Tristate output
Address bus signal
-
D0-D15
Tristate input/output
Bidirectional data bus signal
-
READY
Input
Bus cycle termination permit signal
-
HLDRQ
Input
Bus mastership request signal
-
HLDAK
Output
Bus mastership permit signal
-
BLOCK
Output
Bus mastership prohibit signal
WDTOUT
MRD
Tristate output
Read strobe signal to memory
-
LMWR
Tristate output
Write strobe signal to lower data in memory
WE
UMWR
Tristate output
Write strobe signal to upper data in memory
-
IORD
Tristate output
Read strobe signal to I/O data
-
IOWR
Tristate output
Write strobe signal to I/O data
-
UBE
Tristate output
Data bus upper data enable signal
TXD/P08
RESET
Input
System reset input
-
X1, X2
Input
Crystal connection/external clock input
-
PD70741
9
(2/2)
Pin name
Input/output
Function
Dual-function pin
CLKOUT
Output
System clock output
-
CS0
Tristate output
Chip select signal
REFRQ
CS1
-
CS2
-
CS3
-
INTP00
Input
Interrupt request input
TO00
INTP01
-
INTP02
TO01
INTP03
-
INTP10
-
INTP11
-
INTP12
-
INTP13
TI
NMI
Input
Nonmaskable interrupt request input
-
REFRQ
Tristate output
Refresh request signal to DRAM
CS0
RAS
Tristate output
Row address strobe signal to DRAM
-
LCAS
Tristate output
Column address strobe signal to lower data in DRAM
-
UCAS
Tristate output
Column address strobe signal to upper data in DRAM
-
WE
Tristate output
Write strobe signal to DRAM
LMWR
DREQ0
Input
DMA request signal (channel 0)
P01
DREQ1
Input
DMA request signal (channel 1)
P03
DACK0
Output
DMA permit signal (channel 0)
P02
DACK1
Output
DMA permit signal (channel 1)
P04
TC
Output
DMA end signal
RXD/P09
TO00
Output
RPU pulse output
INTP00
TO01
INTP02
TCLR
Input
External clear or start signal input to timer 0
P00
TI
Input
External count clock input to timer 0
INTP13
TXD
Output
UART serial data output
UBE/P08
RXD
Input
UART serial data input
TC/P09
SCLK
Input/output
CSI serial clock input/output
P07
SO
Output
CSI serial data output
P06
SI
Input
CSI serial data input
P05
WDTOUT
Output
WDT overflow signal
BLOCK
IC
-
Internal connection (must be connected to GND through a resistor)
-
V
DD
-
Supplies positive power.
-
GND
-
Ground potential
-
PD70741
10
1.3 Pin I/O Circuits and Processing of Unused Pins
Table 1-1 shows the I/O circuit type of each pin and the processing for unused pins. Figure 1-1 shows the I/O
circuit of each type.
Table 1-1. I/O Circuits Type of Each Pin and Recommended Connection of Unused Pins
Pin
Recommended connection
I/O circuit type
5
5
4
1
4
8
2
8
2
4
-
-
Input status:
Individually connected to V
DD
or GND through a resistor.
Output status: Open
Open
Open
Connected to GND through a resistor.
Connected to V
DD
through a resistor.
Open
Connected to V
DD
through a resistor.
Connected to V
DD
through a resistor.
Connected to V
DD
through a resistor.
Connected to V
DD
through a resistor.
Open
Connected to GND through a resistor.
P00/TCLR
P01/DREQ0
P02/DACK0
P03/DREQ1
P04/DACK1
P05/SI
P06/SO
P07/SCLK
P08/TXD/UBE
P09/RXD/TC
D0-D15
A0-A7, A16-A18
A8-A15, A19-A23
READY
HLDRQ
HLDAK
BLOCK/WDTOUT
MRD
LMWR/WE
UMWR
IORD
IOWR
CLKOUT
CS0/REFRQ
CS1-CS3
INTP00/TO00
INTP01
INTP02/TO01
INTP03
INTP10-INTP12
INTP13/TI
NMI
RESET
RAS
LCAS
UCAS
X2
IC
PD70741
11
Figure 1-1. Pin I/O Circuits
IN
V
DD
P-ch
N-ch
Type 1
Schmitt trigger input with hysteresis characteristics
IN
Type 2
Data
Output
disable
V
DD
IN/OUT
N-ch
P-ch
Type 8
V
DD
P-ch
N-ch
OUT
Data
Output
disable
Push-pull output which can output high impedance
(Both the positive and negative channels are off.)
Type 4
Data
Output
disable
IN/OUT
Input
enable
P-ch
N-ch
Type 5
V
DD
PD70741
12
2. INTERNAL UNITS
2.1 Bus Interface Unit (BIU)
Controls the pins of the address bus, data bus, and control bus. A bus cycle activated by the CPU or DMAC is
controlled via the WCU, DRAMC, and ROMC.
2.2 Wait Control Unit (WCU)
Manages the four blocks corresponding to four chip select signals (CS0-CS3).
This block generates chip select signals, performs wait control, and selects a bus cycle type.
2.3 DRAM Controller (DRAMC)
Generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to DRAM.
This block supports DRAM high-speed page mode. Access to DRAM can be of either of two types, each having
a different cycle, normal access (off-page) or high-speed page access (on-page).
2.4 ROM Controller (ROMC)
Supports access to ROM supporting a page access function.
Performs address comparison relative to the previous bus cycle and performs wait control for normal access (off-
page)/page access (on-page). It supports page widths of 8-64 bytes.
2.5 Interrupt Controller
Handles maskable interrupt requests (INTP00-INTP03, INTP10-INTP13) from both the built-in and external
peripheral hardware. Priorities can be specified for these interrupt requests, in units of four groups. It can apply
multiple handling control to the interrupt sources.
2.6 DMA Controller (DMAC)
Transfers data between memory and I/O, as instructed by the CPU.
There are two address modes, fly-by (1-cycle) transfer and 2-cycle transfer. There are three bus modes, single
transfer, single-step transfer, and block transfer.
2.7 Serial Interfaces (UART/CSI)
As serial interfaces, the V821 features an asynchronous serial interface (UART) and a synchronous serial interface
(CSI), one channel being assigned to each.
The UART transfers data via pins TXD and RXD.
The CSI transfers data via pins SO, SI, and SCLK.
Either the baud rate generator or the system clock can be selected as the serial clock source.
2.8 Real-Time Pulse Unit (RPU)
This block incorporates a 16-bit timer/event counter and a 16-bit interval timer. It can calculate pulse intervals
and frequencies and output programmable pulses.
PD70741
13
2.9 Watchdog Timer (WDT)
This block incorporates an 8-bit watchdog timer to detect a program hanging up or system errors. If the watchdog
timer overflows, the WDTOUT pin becomes active.
2.10 Clock Generator (CG)
Supplies clock pulses at a frequency five times greater than that of the oscillator connected to pins X1 and X2 (when
the built-in PLL is being used) or at half the frequency (when the built-in PLL is not being used) of the operating clock
pulses for the CPU. Also, instead of connecting an oscillator, external clock pulses can be input.
2.11 Bus Arbitration Unit (BAU)
Arbitrates any contention over bus mastership between the bus masters (CPU, DRAMC, DMAC, external bus
master). Bus mastership can be switched in each bus cycle and also in the idle state.
2.12 Port
Port 0 provides a total of ten input/output port pins. The pins can be used as either port or control pins.
PD70741
14
3. CPU FUNCTIONS
The CPU has functions equivalent to those of the V810 microprocessor, designed for built-in control. It offers bit
string instructions, floating-point instructions, and quick real-time response.
3.1 Features
The features of the CPU are:
High-performance 32-bit RISC microprocessor
Built-in 1-Kbyte cache memory
Pipeline structure of 1-clock pitch
16-bit data bus
32-bit general-purpose registers: 32
4-Gbyte linear address space
Instructions ideal for various application fields
Floating-point operation instructions (conforming to the IEEE754 data format)
Bit string instructions
High-speed interrupt response
Debug support functions
3.2 Address Space
The V821 supports internal memory and I/O spaces of 4G bytes each. The V821 outputs 24-bit addresses to
memory and I/O, such that the addresses range from 0 to 2
24
- 1.
In byte data, bit 0 is defined as the LSB (Least Significant Bit) and bit 7 as the MSB (Most Significant Bit). In multiple-
byte data, bit 0 of the byte data in the lower address is defined as the LSB and bit 7 of the byte data in the upper
address as the MSB, unless noted otherwise.
In the case of the V821, 2-byte data is referred to as halfword data, and 4-byte data as word data. In this data
sheet, in representations of multiple-byte memory and I/O data, the right address corresponds to the lower address
and the left address to the upper address, as shown below.
A (address)
7
0
7
8
15
0
7
8
15
16
23
24
31
0
A + 3
A + 2
A + 1
A (address)
A + 1
A (address)
Byte of address A
Halfword of address A
Word of address A/short real
PD70741
15
3.2.1 Memory map
Figure 3-1 shows the memory map of the V821.
The internal 4-Gbyte memory space is divided into blocks of 1G byte each.
Each block has a linear address space of 16M bytes. (The lower 24 bits of a 32-bit address are output.)
Figure 3-1. Memory Map
Interrupt handler table
Note
Block 3
Block 2
Block 1
Block 0
FFFFFFFFH
FFFFFE00H
FFFFFDFFH
C0000000H
BFFFFFFFH
80000000H
7FFFFFFFH
40000000H
3FFFFFFFH
00000000H
Note See Table 4-1 for details.
PD70741
16
3.2.2 I/O map
Figure 3-2 shows the I/O map of the V821.
The internal 4-Gbyte memory space is divided into blocks of 1G byte each.
Each block has a linear address space of 16M bytes. (The lower 24 bits of a 32-bit address are output.)
The V821 reserves I/O addresses C0000000H-FFFFFFFFH (I/O block 3) as an internal I/O space. Each unit is
mapped to this internal I/O space.
See Section 3.4 for details of the configuration of the internal I/O space.
Figure 3-2. I/O Map
Block 3
(Internal I/O)
Block 2
Block 1
Block 0
FFFFFFFFH
C0000000H
BFFFFFFFH
80000000H
7FFFFFFFH
40000000H
3FFFFFFFH
00000000H
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3.3 CPU Register Set
The registers of the V821 belong to one of two sets, the general-purpose program register set and the dedicated
system register set. All registers are 32 bits in wide.
EIPC
EIPSW
Exception/Interrupt PC
r0
Zero Register
r1
Reserved for Address Generation
r2
Handler Stack Pointer (hp)
r3
Stack Pointer (sp)
r4
Global Pointer (gp)
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
Text Pointer (tp)
r26
String Destination Bit Offset
r27
String Source Bit Offset
r28
String Length
r29
String Destination
r30
String Source
r31
Link Pointer (lp)
Exception/Interrupt PSW
FEPC
FEPSW
Fatal Error PC
Fatal Error PSW
ECR
Exception Cause Register
PSW
Program Status Word
PIR
Processor ID Register
TKCW
Task Control Word
CHCW
Cache Control Word
ADTRE
Address Trap Register
PC
Program Counter
31
0
31
0
31
0
31
0
31
0
31
0
31
0
31
0
31
0
31
0
Program register set
System register set
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3.3.1 Program register set
The program register set includes general-purpose registers and a program counter.
(1) General-purpose registers
The V821 has 32 general-purpose registers, r0-r31. These registers can be used for data or address variables.
Registers r0 and r26-r30 are used implicitly with instructions. Caution is therefore necessary when using these
registers. Registers r1-r5 and r31 are used implicitly by the assembler and the C compiler. Before using these
registers, therefore, the contents of the registers must be saved to prevent their being destroyed. After using
the registers, their contents must be restored.
Table 3-1. Program Registers
Name
Use
Explanation
r0
Zero register
Always stores zeros.
r1
Assembler-reserved register
Used as a working register to create 32-bit immediate.
r2
Handler stack pointer
Used as a stack pointer for the handler.
r3
Stack pointer
Used to create a stack frame at a function call.
r4
Global pointer
Used to access a global variable in a data area.
r5
Text pointer
Points to the top of a text area
r6-r25
-
Register for an address/data variable
r26
String destination start bit offset
Used to execute a bit string instruction.
r27
String source start bit offset
r28
String length register
r29
String destination start address register
r30
String start address register
r31
Link pointer
Stores a return point address according to the execution of a JAL instruction.
(2) Program counter
Stores the address of an instruction while a program is running. Bit 0 of the program counter (PC) is fixed to
0, thus preventing a branch to an odd address. It is initialized to FFFFFFF0H at reset.
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3.3.2 System register set
System registers are used to control the state of the CPU and store interrupt information.
Table 3-2. System Register Numbers
No.
Register name
Use
Explanation
0
EIPC
Registers for saving the current
Retain the contents of PC and PSW if an exception or
status upon the occurrence of an
interrupt occurs. Note, however, that there is only one
exception or interrupt
pair of these registers.
1
EIPSW
When multiple interrupts are allowed, therefore, the
contents of the registers must be saved by the program.
2
FEPC
Registers for saving the current
Retain the contents of PC and PSW if an
status upon the occurrence of an
NMI or double exception occurs.
3
FEPSW
NMI or double exception
4
ECR
Exception source register
Stores the source of an exception, maskable interrupt, or
NMI. The upper 16 bits of this register are called
"FECC" and set to the exception code of an NMI/double
exception. The lower 16 bits are called "EICC" and set
to the exception code of an exception/interrupt.
5
PSW
Program status word
The program status word is a set of flags indicating the
state of the program (result of executing an instruction)
and the state of the CPU.
6
PIR
Processor ID register
Used to identify a CPU type number.
7
TKCW
Task control word
Used to control a floating-point operation.
8-23
Reserved
24
CHCW
Cache control word
Used to control the built-in instruction cache.
25
ADTRE
Address trap register
Stores the address used to detect an address match with
PC, and to generate an address trap.
26-31
Reserved
Read and write operations made to these system registers can be performed using the system register load/store
instructions (LDSR and STSR) with the system register numbers specified.
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3.4 Built-in Peripheral I/O Registers
The built-in peripheral I/O registers are allocated to the 256-byte area between C0000000H and C00000FFH in
the 1-Gbyte space between C0000000H and FFFFFFFFH. Starting from address C0000100H, 256-byte images are
created every 256 bytes.
The least significant bit of an address is not decoded. Thus, when byte access is attempted to a register at an
odd address (2n+1), a register at an even address (2n) is actually performed.
When 16-bit access is attempted to an 8-bit I/O register, the upper eight bits are ignored for write, and become
undefined for read.
Table 3-3 lists the built-in peripheral I/O registers.
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Table 3-3. Built-in Peripheral I/O Registers (1/2)
Address
Function register name
Abbreviation
Manipulatable bits
Initial value
8-bits
16-bits
C0000010
Port mode control register 0
PMC0
o
0000H
C0000012
Port mode register 0
PM0
o
03FFH
C0000014
Port register 0
P0
o
Not defined
C0000020
Bus cycle type control register
BCTC
o
01H
C0000022
Programmable wait control register 0
PWC0
o
77H
C0000024
Programmable wait control register 1
PWC1
o
77H
C0000026
Programmable wait control register 2
PWC2
o
77H
C0000028
DRAM configuration register
DRC
o
81H
C000002A
Refresh control register
RFC
o
80H
C000002C
Page-ROM configuration register
PRC
o
80H
C0000040
DMA source address register 0H
DSA0H
o
Not defined
C0000042
DMA source address register 0L
DSA0L
o
Not defined
C0000044
DMA destination address register 0H
DDA0H
o
Not defined
C0000046
DMA destination address register 0L
DDA0L
o
Not defined
C0000048
DMA source address register 1H
DSA1H
o
Not defined
C000004A
DMA source address register 1L
DSA1L
o
Not defined
C000004C
DMA destination address register 1H
DDA1H
o
Not defined
C000004E
DMA destination address register 1L
DDA1L
o
Not defined
C0000050
DMA byte count register 0
DBC0
o
Not defined
C0000052
DMA byte count register 1
DBC1
o
Not defined
C0000054
DMA channel control register 0
DCHC0
o
0000H
C0000056
DMA channel control register 1
DCHC1
o
0000H
C0000060
Timer unit mode register 0
TUM0
o
0A00H
C0000062
Timer control register 0
TMC0
o
00H
C0000064
Timer control register 1
TMC1
o
00H
C0000066
Timer output control register 0
TOC0
o
03H
C0000068
Timer overflow status register
TOVS
o
00H
C0000070
Timer register 0
TM0
o
0000H
C0000072
Capture/compare register 00
CC00
o
Not defined
C0000074
Capture/compare register 01
CC01
o
Not defined
C0000076
Capture/compare register 02
CC02
o
Not defined
C0000078
Capture/compare register 03
CC03
o
Not defined
C000007C
Timer register 1
TM1
o
0000H
C000007E
Compare register 1
CM1
o
Not defined
C0000080
Asynchronous serial interface mode register ASIM
o
00H
C0000082
Asynchronous serial interface status register ASIS
o
00H
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Table 3-3. Built-in Peripheral I/O Registers (2/2)
Address
Function register name
Abbreviation
Manipulatable bits
Initial value
8-bits
16-bits
C0000084
Reception buffer
RXB
o
Not defined
C0000086
Reception buffer L
RXBL
o
Not defined
C0000088
Transmission shift register
TXS
o
Not defined
C000008A
Transmission shift register L
TXSL
o
Not defined
C0000090
Synchronous serial interface mode register
CSIM
o
00H
C0000092
Serial I/O shift register
SIO
o
Not defined
C00000A0
Baud rate generator register
BRG
o
Not defined
C00000A2
Baud rate generator prescale mode register BPRM
o
00H
C00000B0
Interrupt group priority register
IGP
o
E4H
C00000B2
Interrupt clear register
ICR
o
0000H
C00000B4
Interrupt request register
IRR
o
0000H
C00000B6
Interrupt request mask register
IMR
o
FFFFH
C00000B8
ICU mode register
IMOD
o
AAAAH
C00000C0
WDT mode register
WDTM
o
00H
C00000D0
Standby control register
STBC
o
00H
C00000E0
Clock control register
CGC
o
03H
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3.5 Data Types
3.5.1 Data types
The data types supported by the V821 are as follows:
Integer (8, 16, 32 bits)
Unsigned integer (8, 16, 32 bits)
Bit string
Single-precision floating-point data (32 bits)
(1) Data type and addressing
The V821 uses the little-endian data addressing. In this addressing, if fixed-length data is located in a memory
area, the data must be either of the data types shown below.
(a) Byte
A byte is consecutive 8-bit data whose first-bit address is aligned to a byte boundary. Each bit in a byte is
numbered from 0 to 7: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 7. To
access a byte, specify address A. (See diagram below.)
(b) Halfword
A halfword is consecutive 16-bit (= 2 bytes) data whose first-bit address is aligned to a halfword boundary.
Each bit in a halfword is numbered from 0 to 15: LSB (the least significant bit) is bit 0 and MSB (the most
significant bit) is bit 15. To access a halfword, specify the address A only (lowest bit must be 0).
(c) Word/short real
A word, also called short real, is consecutive 32-bit (= 4 bytes) data whose first-bit address is aligned to a
word boundary. Each bit in a word is numbered from 0 to 31: LSB (the least significant bit) is bit 0 and MSB
(the most significant bit) is bit 31. To access a word or short real, specify the address A only (lower two bits
must be 0).
15
8 7
A + 1
0
A
7
0
A
31
24 23
A + 3
16 15
A + 2
8 7
A + 1
0
A
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(2) Integer
In the V821, all integers are expressed in the two's-complement binary notation, and are composed of either 8
bits, 16 bits, or 32 bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered bits
express higher digits of the integer with the highest bit expressing its sign.
Data length
Range
Byte
8 bits
-128 to +127
Halfword
16 bits
-32 768 to +32 767
Word
32 bits
-2 147 483 648 to +2 147 483 647
(3) Unsigned integer
An unsigned integer is either zero or a positive integer unlike the integer explained in (2) which can be negative
as well as zero and positive. Unsigned integers are expressed in the binary notation in the same way as integers,
and are either 8 bits, 16 bits, or 32 bits long. Regardless of the data length, the bit assignments are the same
as in the case of integers except that unsigned integers do not include a sign bit; the highest bit is also a part
of the integer.
Data length
Range
Byte
8 bits
0 to 255
Halfword
16 bits
0 to 65 535
Word
32 bits
0 to 4 294 967 295
(4) Bit string
A bit string is a type of data whose bit length is variable from 0 to 2
32
- 1. To specify a bit-string data, define
the following three attributes.
A : address of the string data's first word (lower two bits must be 0.)
B : in-word bit offset in the string data (0 to 31)
M : bit length of the string data (0 to 2
32
- 1)
The above three attributes may vary depending on the bit-string data manipulation direction: upward or downward,
as shown below. The former is the direction from lower addresses to higher addresses while the latter is the direction
from higher to lower addresses.
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(5) Single-precision floating-point data
This data type is 32 bits long and its bit allocation complies with the IEEE single format. A single-precision floating-
point data consists of 1-bit mantissa sign bit, 8-bit exponent, and 23-bit mantissa. The exponent is offset-
expressed from the bias value - 127, and the mantissa is binary-expressed with the integer part omitted.
3.5.2 Data alignment
In the V821, a word data must be aligned to a word boundary (with the lowest two bits of the address fixed to 0s),
and a halfword data to a halfword boundary (with the lowest bit of the address fixed to 0). If a data is not aligned
as specified, the lowest two bits (in the case of word) or one bit (in the case of halfword) of its address will forcibly
be masked with 0s when the data is accessed.
31
23
30
s
exp (8)
mantissa (23)
22
0
D
A + 8
M - 1
0
A + 4
A (Word boundary)
M
B
Attribute
Upward
Downward
First-word address (0s in bits 1 and 0)
In-word bit offset (0 to 31)
Bit length (0 to 2 - 1)
32
A
B
M
A + 4
D
M
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3.6 Cache
Figure 3-3 shows the instruction cache configuration provided to the V821.
Figure 3-3. Cache Configuration
31
27
22
31
0
0
21
10
Memory address
TAG
TAG31 to TAG10
Tag memory
(ICHT27 to ICHT0)
Data memory
(ICHD31 to ICHD0)
Entry 0
Entry 1
128 entries
Entry 127
Valid bits (1 bit for every 4 bytes)
NECRV (Reserved by NEC)
Sub-block (4 bytes)
Block
(8 bytes)
Offset
Index
9
3 2
0
128 blocks
Capacity
Mapping system
Block size
Sub-block size
: 1 Kbytes
: direct map
: 8 bytes
: 4 bytes
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4. INTERRUPT/EXCEPTION HANDLING FUNCTIONS
The V821 features an interrupt controller (ICU) that is dedicated to interrupt handling. The V821 thus supports
a powerful interrupt handling function capable of handling interrupt requests issued by up to 16 sources.
As referred to in this manual, an interrupt is an event which occurs independently of program execution while an
exception is an event that depends on program execution. In general, an exception assumes a higher priority than
an interrupt.
The V821 can handle interrupt requests issued by both built-in peripheral hardware and external devices.
Exception handling can be triggered by executing an instruction (TRAP instruction) as well as by the occurrence of
an exception (such as an address trap or invalid instruction code).
4.1 Features
Interrupts
Nonmaskable interrupt : 1 source
Maskable interrupt
: 15 sources
Programmable priority control with four groups
Multiple interrupt handling control according to priority
Mask specification for each maskable interrupt request
Valid edge specification for external interrupt requests
The noise eliminator introducing an analog delay (60 to 300 ns) is incorporated into the nonmaskable
interrupt (NMI) pin.
Exceptions
Software exception : 32 sources
Exception trap
: 10 sources
Table 4-1 lists the interrupt and exception sources.
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Table 4-1. Interrupts (1/2)
Type
Category
Group Priority
Interrupt/exception source
Exception
Handler
Return
in group
Name
Source
Unit
code
address
PC
Note 1
Reset
Interrupt
-
-
RESET
Reset input
-
FFF0H
FFFFFFF0H
Undefined
Non-
Interrupt
-
-
NMI
NMI input
-
FFD0H
FFFFFFD0H
Next
maskable
PC
Note 2
Software
Exception
-
-
TRAP1nH
trap instruction
-
FFBnH
FFFFFFB0H
Next PC
exception
-
-
TRAP0nH
trap instruction
-
FFAnH
FFFFFFA0H
Next PC
Exception Exception
-
-
DP-EX
Double exception
-
Note 3
FFFFFFD0H
Current
trap
-
-
AD-TR
Address trap
-
FFC0H
FFFFFFC0H
PC
-
-
I-OPC
Invalid instruction
-
FF90H
FFFFFF90H
code
-
-
DIV0
Division by zero
-
FF80H
FFFFFF80H
-
-
FIZ
Invalid floating-
-
FF70H
FFFFFF60H
point operation
-
-
FZD
Floating-point
-
FF68H
FFFFFF60H
division by zero
-
-
FOV
Floating-point
-
FF64H
FFFFFF60H
overflow
-
-
FUD
Floating-point
-
FF62H
FFFFFF60H
underflow
Note 4
-
-
FPR
Floating-point
-
FF61H
FFFFFF60H
degraded
precision
Note 4
-
-
FRO
Floating-point
-
FF60H
FFFFFF60H
reserved operand
Remark n = 0H to FH
Notes 1. PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling
2. Return PC = current PC if an interrupt occurred during the execution of an instruction which was stopped
by an interrupt (DIV/DIVU, floating-point, and bit string instructions).
3. The exception code for the exception which occurred first is written into in the 16 low-order bits of ECR,
while and that for the second exception is written into the 16 high-order bits.
4. The V821 is not subject to floating-point underflow or degraded precision exceptions.
PD70741
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Table 4-1. Interrupts (2/2)
Type
Category
Group
Priority
Interrupt/exception source
Exception
Handler
Return
in group
Name
Source
Unit
code
address
PC
Note 1
Maskable Interrupt
GR3
3
RESERVED
Reserved
-
FEF0H
FFFFFEF0H
Next
2
INTOV0
Timer 0
RPU
FEE0H
FFFFFEE0H
PC
Note 2
overflow
1
INTSER
UART recep-
UART
FED0H
FFFFFED0H
tion error
0
INTP13
INTP13 pin
External
FEC0H
FFFFFEC0H
input
GR2
3
INTSR
UART recep-
UART
FEB0H
FFFFFEB0H
tion end
2
INTST
UART trans-
UART
FEA0H
FFFFFEA0H
mission end
1
INTCSI
CSI transmis-
CSI
FE90H
FFFFFE90H
sion/reception
end
0
INTP12
INTP12 pin
External
FE80H
FFFFFE80H
input
GR1
3
INTDMA
DMA transfer
DMAC
FE70H
FFFFFE70H
end
2
INTP00/
INTP00 pin
External/
FE60H
FFFFFE60H
INTCC00
input/CC00
RPU
match
1
INTP01/
INTP01 pin
External/
FE50H
FFFFFE50H
INTCC01
input/CC01
RPU
match
0
INTP11
INTP11 pin
External
FE40H
FFFFFE40H
input
GR0
3
INTCM1
CM1 match
RPU
FE30H
FFFFFE30H
2
INTP02/
INTP02 pin
External/
FE20H
FFFFFE20H
INTCC02
input/CC02
RPU
match
1
INTP03/
INTP03 pin
External/
FE10H
FFFFFE10H
INTCC03
input/CC03
RPU
match
0
INTP10
INTP10 pin
External
FE00H
FFFFFE00H
input
Notes 1. PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling
2. Return PC = current PC if an interrupt occurred during the execution of an instruction which was stopped
by an interrupt (DIV/DIVU, floating-point, and bit string instructions).
Caution The exception code and handler address for a maskable interrupt assume the values existing
when the default priority is specified.
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5. WAIT CONTROL FUNCTIONS
The wait control unit (WCU) manages the four blocks corresponding to the four chip select signals, generates the
chip select signals, performs wait control, and selects the bus cycle types.
5.1 Features
Able to control up to four blocks in the memory and I/O spaces
Linear address space of each block: 16 Mbytes
Wait control
Automatic insertion of 0-7 waits per block
Insertion of waits using the READY pin
Bus cycle selection function
Page-ROM cycle selectable (address block 3)
DRAM cycle selectable (address block 0)
Figure 5-1. Memory and I/O Maps
FFFFFFFFH
00000000H
40000000H
3FFFFFFFH
80000000H
7FFFFFFFH
C0000000H
BFFFFFFFH
FFFFFFFFH
00000000H
40000000H
3FFFFFFFH
80000000H
7FFFFFFFH
C0000000H
BFFFFFFFH
Block 3
(1 Gbyte)
Block 2
(1 Gbyte)
Block 1
(1 Gbyte)
Block 0
(1 Gbyte)
16 Mbytes
16 Mbytes
Image
Image
Image
Image
Image
Image
Block 3
(1 Gbyte)
Internal I/O
Block 2
(1 Gbyte)
Block 1
(1 Gbyte)
Block 0
(1 Gbyte)
16 Mbytes
Image
Image
Image
(1) Memory map
(2) I/O map
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Table 5-1. Bus Cycles during Which the Wait Function Is Effective
Bus cycle
Programmable wait
Wait with the READY pin
SRAM (ROM) cycle (Blocks 0-3)
0-7 waits
o
DRAM cycle (Block 0)
off-page
2 or 3 waits
o
on-page
0 or 1 wait
Page-ROM cycle (Block 3)
off-page
0-7 waits
on-page
0 or 1 wait
External I/O cycle (Blocks 0-2)
0-7 waits
o
Internal I/O cycle (Block 3)
1 or 2 waits
CBR refresh cycle
Fixed (3 waits)
o
CBR self-refresh cycle
-
Fly-by DMA transfer
SRAM (ROM) cycle (Blocks 0-3)
0-7 waits
o
DRAM cycle (Block 0)
off-page
2-7 waits
o
on-page
0-7 waits
Page-ROM cycle (Block 3)
off-page
0-7 waits
on-page
0-7 waits
Halt acknowledge cycle
Fixed (0 wait)
Machine fault cycle (I/O block 0 write)
0-7 wait
o
Remark o: Effective
: Not effective
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6. MEMORY ACCESS CONTROL FUNCTIONS
6.1 DRAM Controller (DRAMC)
The DRAM controller (DRAMC) generates the REFRQ, RAS, LCAS, and UCAS signals, and controls access to
DRAM. Access to DRAM is achieved by multiplexing the DRAM row and column addresses and outputting them from
the address pins.
The microprocessor assumes the connected DRAM to be of
4 bits or more, and that it supports high-speed page
mode. There are two types of DRAM access cycles, on-page (2 or 3 clock pulses) and off-page (4 or 5 pulses).
Refresh uses the CAS before RAS method, allowing the user to set any refresh period. In IDLE and STOP modes,
CBR self-refresh is performed.
6.1.1 Features
Generates the REFRQ, RAS, LCAS, and UCAS signals.
Supports DRAM high-speed page mode.
Address multiplexing function: 8, 9, 10, and 11 bits
CBR refresh and CBR self-refresh functions
6.1.2 Address multiplexing function
In the DRAM cycle, row and column addresses are multiplexed according to the value of the DAW bits of the DRAM
configuration register (DRC), then output, as shown in Figure 6-1. In Figure 6-1, a0-a23 are the addresses output
from the CPU, while A0-A23 are the address pins of the V821. For example, if DAW = 11, row address a12-a22 and
column address a1-a11 are output from address pins (A1-A11).
Table 6-1 lists the relationship between the connectable DRAMs and address multiplexing widths. Depending on
the connected DRAM, the DRAM space can be between 128 Kbytes and 8 Mbytes.
Figure 6-1. Output of Row and Column Addresses
a23
a16
a15 a14 a13 a23
a22
a21 a20
a19 a18
a17 a16
a15 a14
a13 a12 a11
A23
A16
A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
a23
a16
a15 a14 a23 a22
a21
a20 a19
a18 a17
a16 a15
a14 a13
a12 a11 a10
a23
a16
a15 a23 a22 a21
a20
a19 a18
a17 a16
a15 a14
a13 a12
a11 a10
a9
a23
a16
a23 a22 a21 a20
a19
a18 a17
a16 a15
a14 a13
a12 a11
a10
a9
a8
a23
a0
Address pin
Row address
DAW = 11
DAW = 10
DAW = 01
DAW = 00
Column address
PD70741
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Table 6-1. Examples of DRAM and Address Multiplexing Width
Address multiplexing width
DRAM capacity (in bits) and configuration
DRAM space (in bytes)
256 K
1 M
4 M
16 M
8 bits
64 K
4
-
-
-
128 K
9 bits
-
256 K
4
256 K
16
-
512 K
-
-
512 K
8
-
1 M
10 bits
-
-
1 M
4
1 M
16
2 M
-
-
-
2 M
8
4 M
11 bits
-
-
-
4 M
4
8 M
6.1.3 Refresh function
DRAMC can automatically generate the distributed CBR refresh cycle needed to refresh external DRAM. Whether
refresh should be enabled or disabled, and the refresh interval, are specified using the refresh control register (RFC).
While another bus master is occupying a bus, DRAMC cannot forcibly acquire the bus. In this case, in response
to a refresh request issued from DRAMC, BAU makes the HLDAK pin inactive to post notification of the occurrence
of a refresh request. In this state, by making the HLDRQ pin inactive, the refresh cycle is activated.
6.1.4 Self-refresh function
DRAMC generates the CBR self-refresh cycle in IDLE and STOP modes. The self-refresh cycle is activated by
setting the SMD bit of the standby control register (STBC) to IDLE or STOP mode and executing the HALT instruction.
To enable DRAM to perform self-refresh, the standard RAS pulse width for DRAM (100
s or greater) must be
ensured.
Self-refresh is canceled using the RESET or NMI pin. The procedure for cancellation by RESET input is the same
as that for normal reset.
6.2 ROM Controller (ROMC)
The ROM controller supports access to ROM having a page access function (page-ROM).
The ROM controller performs address comparison with the previous bus cycle and performs wait control for normal
access (off-page)/page access (on-page). It supports page widths of 8-64 bytes.
The page-ROM cycle is supported with address block 3.
6.2.1 on-page/off-page decision
Whether the page-ROM cycle is on-page or off-page is determined by latching the address during the previous
cycle and comparing it with the address during the current cycle.
The address(es) (A3-A5) to be masked (not compared) is set using the page-ROM configuration register (PRC),
according to the configuration of the connected page-ROM and the number of consecutively readable bits.
PD70741
34
Figure 6-2. on-page/off-page Decision When ROM Having a Page Access Function Is Connected
on/off-page
A'0
A'1
A'2
A'4 A'3
A'17
A'18
A'19
MRQ a31 a30
A23 A22 A21
mrq a31 a30
a23 a22 a21 a20
A20 A19
a19 a18
A18
a5
a4
a3
A5
A4
A3
A2
A1
MA5
0
MA4
0
MA3
0
A0
Internal
address latch
Setting of the
PRC register
V821 output
address
Compa-
rison
Compa-
rison
(Same address block)
Memory access
Comparison
Comparison
(Internal)
Consecutively readable bits: 16 bits
4
In-page address
on/off-page
A'-1
A'0
A'1
A'2
A'4 A'3
A'17
A'18
A'19
MRQ a31 a30
A23 A22 A21
mrq a31 a30
a23 a22 a21 a20
A20 A19
a19 a18
A18
a5
a4
a3
A5
A4
A3
A2
A1
MA5
0
MA4
0
MA3
1
A0
Internal
address latch
Setting of the
PRC register
V821 output
address
Compa-
rison
Compa-
rison
(Same address block)
(Internal)
Memory access
Comparison
Comparison
Consecutively readable bits: 8 bits
8
In-page
address
(1) For 16-Mbit ROM (1-Mbit
16)
(2) For 16-Mbit ROM (2-Mbit
8)
PD70741
35
7. DMA FUNCTIONS (DMA CONTROLLER)
The V821 includes a DMA (Direct Memory Access) controller that executes and controls DMA transfer.
The DMAC (DMA controller) transfers data between memory and I/O, or within memory, based on DMA requests
issued by the built-in peripheral hardware (serial interfaces and timer), external DREQ pins, or software triggers.
7.1 Features
Two independent DMA channels
Transfer units: 8/16 bits
Maximum transfer count: 65 536 (2
16
)
Two types of transfer
Fly-by (one-cycle) transfer
Two-cycle transfer
Three transfer modes
Single transfer mode
Single-step transfer mode
Block transfer mode
Transfer requests
External DREQ pin (
2)
Requests from built-in peripheral hardware (serial interfaces and timer)
Requests from software
Transfer objects
Memory to I/O and vice versa
Memory to memory and vice versa
Programmable wait function
DMA transfer end output signal (TC)
PD70741
36
Figure 7-1. Block Diagram of DMAC
Bus interface
DMA source
address registers
DMA destination
address registers
DMA byte count
registers
DMA channel
control registers
Address control
section
Data control
section
Count control
section
INTDMA
INTCM1
INTSR
INTST
INTCSI
TC
DREQ
DACK
ROM
RAM
I/O
I/O
I/O
Internal data bus
External data bus
Peripheral data bus
Channel control
section
PD70741
37
8. SERIAL INTERFACE FUNCTION
8.1 Features
The V821 provides two transmission and reception channels as part of its serial interface function.
The two interface modes listed below are supported, one channel being provided for each mode. The two modes
operate independently of each other.
(1) Asynchronous serial interface (UART)
(2) Synchronous serial interface (CSI)
In UART mode, one-byte serial data is transmitted or received after a start bit, and full-duplex communication is
enabled.
In CSI mode, data is transferred using three signal lines (three-wire serial I/O): the serial clock (SCLK), serial input
(SI), and serial output (SO).
8.2 Asynchronous Serial Interface (UART)
8.2.1 Features
Transfer rate 110 bps to 38 400 bps
(when BRG is used with
= 25 MHz)
781 Kbps maximum
(when
/2 is used with
= 25 MHz)
Full-duplex communication
Two-pin configuration TXD : Transmission data output pin
RXD : Reception data input pin
Reception error detection function
Parity error
Framing error
Overrun error
Interrupt source (3 types)
Reception error interrupt (INTSER)
Reception completion interrupt (INTSR)
Transmission completion interrupt (INTST)
The character length for transmission and reception data is specified upon ASIM reception.
Character length : 7 or 8 bits
9 bits (when an extended bit is used)
Parity function: Odd parity, even parity, zero parity, without parity
Transmission stop bit: 1 or 2 bits
On-chip baud rate generator
PD70741
38
Figure 8-1. Block Diagram of Asynchronous Serial Interface
RXD
TXD
RXB
RXBL
ASIS
TXS
TXSL
INTST
8
16/8
16/8
8
ASIM
Internal bus
Reception
buffer
Reception
shift register
Transmission
shift register
Transmission
control parity
bit addition
Reception
control parity
check
Selector
Baud rate generator
1
16
1
2
1
16
PE FE OVESOT
RXE PS EBS CL
SL SCLS
INTSER
INTSR
PD70741
39
CSIM
D
Q
SI
SO
SCLK
1
2
/2
INTCSI
CTXE
CRXE SOT MOD
CLS
Internal bus
SO latch
Shift register (SIO)
Serial clock
control circuit
Selector
Selector
Baud rate generator
Serial clock
counter
Interrupt
control circuit
8.3 Synchronous Serial Interface (CSI)
8.3.1 Features
High-speed transfer 6.25 Mbps maximum (when
/2 is used with
= 25 MHz)
Half-duplex communication
Character length: 8 bits
Switchable between the MSB and LSB to lead data transfer
Allows selection between external serial clock input and internal serial clock output
Three-wire method
SO
: Serial data output
SI
: Serial data input
SCLK : Serial clock I/O pin
One interrupt source
Interrupt request signal (INTCSI)
Figure 8-2. Block Diagram of Clock Synchronous Serial Interface
PD70741
40
/2
UART
CSI
TMBRG
BRG
BPR
BRCE
BPRM
7
0
1
2
Internal bus
Match
Clear
Prescaler
8.4 Baud Rate Generator (BRG)
8.4.1 Configuration and function
With the serial interface, a serial clock chosen from the baud rate generator output and clocks generated using
the system clock (
) can be used as a baud rate.
A serial clock source can be specified by using the SCLS bit of the ASIM register when the UART is used, or by
using the CLS bit of the CSIM register when the CSI is used.
When baud rate generator output is specified, the baud rate generator is selected as the clock source.
The same serial clock is used for both transmission and reception on a channel, so that the same baud rate applies
to transmission and reception.
Figure 8-3. Block Diagram
PD70741
41
9. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
The real-time pulse unit (RPU) measures pulse intervals and frequencies, and outputs programmable pulses. It
is capable of 16-bit measurement. It can also generate various types of pulses, such as interval pulse and one-shot
pulse.
9.1 Features
Timer 0 (TM0)
16-bit timer/event counter
Two count clock sources (system clock frequency division selected or external pulse input)
Four capture/compare registers
Count clear pin (TCLR)
Five interrupt sources
Two external pulse outputs
Timer 1 (TM1)
16-bit interval timer
Count clock generated by dividing the system clock frequency
Compare register
Interrupt source
Figure 9-1. Timer 0 (16-Bit Timer/Event Counter)
INTOV0
INTCC00
INTCC01
S
R
Note 3
Q
Q
S
R
Note 3
Q
Q
TO00
TO01
INTCC02
INTCC03
CC00
CC01
CC02
CC03
INTP00
INTP01
INTP02
INTP03
TI
Note 2
m
/2
/4
TCLR
Note 1
m
m/4
m/8
m/16
TM0 (16 bits)
Edge
detection
Clear and
start
Clear and start
Edge
detection
Edge
detection
Edge
detection
Edge
detection
Edge
detection
Notes 1. Internal count clock
2. External count clock
3. A reset takes precedence.
Remark
: System clock
PD70741
42
Figure 9-2. Timer 1 (16-Bit Interval Timer)
CM1
INTCM1
Note
m
m/16
m/32
/2
/4
/8
TM1 (16 bits)
Clear and start
Note Internal count clock
Remark : System clock
PD70741
43
10. WATCHDOG TIMER FUNCTIONS
The watchdog timer is intended to prevent program crash and deadlock.
10.1 Features
The following three different time-out time values can be specified: 10.5 ms, 41.9 ms, and 167.8 ms (when
system clock
= 25 MHz)
Watchdog timer time-out output (WDTOUT)
Figure 10-1. Watchdog Timer Block Diagram
/2
10
/2
12
/2
14
S
Q
R
WDTOUT
Frequency
divider
Watchdog
timer
(8 bits)
Time-out
Clear
WDTM register CLR bit
RESET
STOP
Time-out
Oscillation
settling time
control circuit
Active timer
(5 bits)
Remark : System clock
PD70741
44
(1) Watchdog timer
One of the watchdog timer functions is to secure the oscillation settling time of the system clock. When the system
is reset or placed in STOP mode, the timer is cleared to 00H.
The watchdog timer behaves in the standby modes as follows:
(a) STOP mode
The watchdog timer stops counting. When the system is released from STOP mode, the timer value is
cleared.
The watchdog timer starts counting at 00H, and keeps counting until a time-out occurs. A time-out
signal is supplied to the oscillation settling time control circuit, thus starting to supply the system clock
pulse. At this point, the WDTOUT pin does not become active. If the system is released from STOP
mode by the NMI pin, the timer continues counting.
(b) IDLE mode
The watchdog timer stops counting, but it holds the count value.
When the system is released from IDLE mode, the watchdog timer resumes counting by starting at the
current count value.
(c) HALT mode
The watchdog timer continues counting.
(2) Active timer
The watchdog timer outputs the WDTOUT signal when it times out. The active timer retains this signal for 32
clock cycles.
When the watchdog timer times out, it can cause a system reset by connecting the WDTOUT and RESET pins
through an external circuit.
10.2 Operation
The watchdog timer indicates that the program or system is running normally, by keeping the WDTOUT pin from
becoming active.
To use the watchdog timer, it is necessary to specify the WDTM register so that the watchdog timer is cleared
(restarted to count) at constant intervals during program execution or at the beginning of a subroutine. If the watchdog
timer expires because it is not cleared within a specified period of time, the WDTOUT pin becomes active, indicating
a program failure. In addition, the WDT time-out flag (OV) is set. This flag is cleared by clearing the WDT counter.
To use a watchdog timer time-out as an interrupt source, it is necessary to connect the WDTOUT pin to an external
interrupt request pin (INTPn or NMI) through an external circuit.
PD70741
45
11. PORT FUNCTIONS
The V821 pins are dual-function pins that can function as both port and control pins. See Chapter 1 for details
of each pin.
11.1 Features
10 input/output ports (P00 to P09)
Figure 11-1. Configuration
Write
Mode (PM
)
I/O
Read
Internal address
Latch
PD70741
46
12. CLOCK GENERATION FUNCTIONS
The clock generator generates and controls the internal clock pulse (
) for the CPU and other built-in hardware
units.
12.1 Features
Frequency multiplication (5 times) using a PLL (phase locked loop) synthesizer
Clock sources
Resonator-based oscillation: f
XX
=
/5
(PLL mode)
External clock
: f
XX
=
/5
(PLL mode)
External clock
: f
XX
= 2
(direct mode)
Clock output control
Figure 12-1. Configuration
: Internal clock frequency ( = 1/210f
XX
: PLL mode)
Internal clock frequency ( = 1/2f
XX
: Direct mode)
: Oscillator (only for the PLL mode)
OSC
RESET
TCLR
X1
(f
XX
)
X2
OSC
1
2
Latch
PLL synthesizer
1
2
CLKOUT
(10 f
XX
)
PLL mode
Direct mode
(f
XX
)
STOP mode
PD70741
47
13. STANDBY FUNCTIONS
The V821 supports three standby modes to suppress power dissipation. In these standby modes, the operation
of the clock is controlled. The HALT instruction is used to select a standby mode. Mode switching is controlled using
the standby control register.
13.1 Features
HALT mode (Only the CPU clock stops.)
IDLE mode (The CPU and peripheral operation clocks stop. The clock generator continues to operate.)
STOP mode (The entire system, including the clock generator, stops.)
13.2 Standby Mode
The standby modes of the V821 are detailed below.
(1) HALT mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but the CPU clock stops.
Clock supply to other built-in peripheral functions continues to allow them to keep running. Intermittent operation
achieved using this standby mode in conjunction with the ordinary operation mode can reduce the total power
dissipation of the system.
(2) IDLE mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but internal system clock
supply is stopped to bring the entire system to a stop.
When the system is released from IDLE mode, it is unnecessary to secure oscillation settling time for the oscillator,
and therefore it is possible for the system to shift to the ordinary operation quickly.
For the oscillation settling time and current drain, IDLE mode lies in between STOP and HALT modes. IDLE
mode is suitable for an application where it is necessary to cut the oscillation settling time using a low current
drain mode.
(3) STOP mode
In this mode, the clock generator (oscillator and PLL synthesizer) is stopped to bring the entire system to a stop.
This mode can generate an ultra-low power dissipation condition; only leak current occurs.
(a) PLL mode
In this mode, the PLL synthesizer clock output is stopped simultaneously with the oscillator. After the
system is released from STOP mode, it is necessary to allow oscillation settling time for the oscillator.
Some programs require a PLL lock-up time.
(b) Direct mode
In the direct mode, it is unnecessary to secure lock-up time.
Table 13-1 lists the operation of the clock generator in the ordinary, HALT, IDLE, and STOP modes. An effective
low power dissipation system can be implemented by combining and switching these modes.
PD70741
48
Table 13-1. Clock Generator Operation under Standby Control
Clock source
Standby mode
Oscillator
PLL
Clock supply
Clock supply
(OSC)
synthesizer
to the pe-
to the CPU
ripheral I/O
PLL mode
Resonator-
Ordinary
o
o
o
o
based
HALT
o
o
o
oscillation
IDLE
o
o
STOP
External clock
Ordinary
o
o
o
HALT
o
o
IDLE
o
STOP
Direct mode
Ordinary
o
o
HALT
o
IDLE
STOP
Remark o : Operating
: Stopped
Table 13-2. Operation Status in HALT, IDLE, or STOP Mode
Note High impedance when HLDAK = 0
Clock generator
Internal system clock
CPU
I/O line
Peripheral function
Internal data
A0-A23, UBE
D0-D15
CS0-CS3
IORD, IOWR
MWR/LMWR, UMWR
REFRQ, RAS, LCAS, UCAS
HLDRQ
CLKOUT
Operating
Operating
Stopped
Retained
Operating
All internal data, such as in CPU registers is retained.
PC output
Note
High impedance
1
Note
1 (other than during CBR
refresh)
Note
Operating
Note
Clock output (when the clock output is not inhibited)
Stopped
Stopped
Stopped
PC output
1
CBR self-refresh
Stopped
1
Function
HALT mode
IDLE mode
STOP mode
CBR self-refresh
Note
PD70741
49
14. RESET FUNCTIONS
Inputting a low level to the RESET pin triggers a system reset, thus initializing the on-chip hardware.
When the RESET pin is driven from a low level to a high, the CPU starts program execution. The registers should
be initialized in a program as required.
14.1
Features
The reset pin is provided with a noise suppressor circuit based on an analog delay (60 to 300 ns).
14.2
Pin Functions
Table 14-1 lists the state of the output from each pin during a system reset. The output state is retained during
the entire reset period.
After the RESET pin is kept at a low level for 30 clock cycles, if the HLDRQ signal is inactive, a memory read cycle
is started to fetch an instruction.
Even during a reset period (when the RESET pin is kept at a low level), activating the HLDRQ signal can place
the bus on hold. The state of each pin with the bus put on hold during a reset is basically the same as that with the
bus put on hold during a non-reset period.
The HLDRQ signal should be kept inactive during a power-on reset.
It is necessary to provide a pull-up or pull-down resistor to the pins that become high impedance during a reset.
If no pull-up or pull-down resistor is provided to these pins, memory may be damaged when the pins are driven to
high impedance.
The CLKOUT pin supplies clock pulses even during a reset.
Table 14-1. Output State of Each Pin during a Reset
Pin
Operation state
Pin
Operation state
A0-A23
Not defined
HLDAK
High level
D0-D15
High impedance
MRD
P00/TCLR
LMWR/WE
P01/DREQ0
UMWR
P02/DACK0
IORD
P03/DREQ1
IOWR
P04/DACK1
CS1-CS3
P05/SI
RAS
P06/SO
LCAS
P07/SCLK
UCAS
P08/TXD/UBE
CS0/REFRQ
P09/RXD/TC
BLOCK/WDTOUT
Low level
PD70741
50
15. INSTRUCTION SET
15.1 Instruction Format
The V821 instructions are formatted in either 16 bits or 32 bits. Examples of the 16-bit format instruction are
binomial operation, control, and conditional branch; those for the 32-bit format are load/store, I/O manipulate, 16-
bit immediate, jump & link, and extended operations.
Some instructions have an unused field. However, do not write a program that uses this field because it is reserved
for future use. This unused field must be set to zeros.
Instructions are stored in memory in the following manner.
The lower half of an instruction, that is, the half which includes bit 0, is stored at the lower address.
The higher half of an instruction, that is, the half which includes bit 15 or 31, is stored at the higher address.
(1) reg-reg instruction format (Format I)
This format consists of one 6-bit field to hold an operation code and two 5-bit fields to specify general-purpose
registers as instruction's operands. 16-bit instructions use this format.
(2) imm-reg instruction format (Format II)
This format consists of one 6-bit field to hold an operation code, one 5-bit field to hold an immediate data, and
one field to specify a general-purpose register as an operand. 16-bit instructions use this format.
(3) Conditional branch instruction format (Format III)
This format consists of one 3-bit field to hold an operation code, one 4-bit field to hold a condition code, and one
9-bit field to hold a branch displacement (with its LSB masked to 0). 16-bit instructions use this format.
15
10
opcode
reg2
imm
9
5 4
0
15
10
opcode
reg2
reg1
9
5 4
0
15
13
opcode
cond
disp
12
9 8
0
0
PD70741
51
(4) Intermediate jump instruction format (Format IV)
This format consists of one 6-bit field to hold an operation code and one 26-bit field to hold a displacement (with
its LSB masked to 0). 32-bit instructions use this format.
(5) 3-operand instruction format (Format V)
This format consists of one 6-bit field to hold an operation code, two fields to specify general-purpose registers
as operands, and one 16-bit field to hold an immediate data. 32-bit instructions use this format.
(6) Load/store instruction format (Format VI)
This format consists of one 6-bit field to hold an operation code, two fields to specify a general-purpose register,
and one 16-bit field to hold a displacement. 32-bit instructions use this format.
(7) Extension instruction format (Format VII)
This format consists of one 6-bit field to hold an operation code, two 5-bit fields to specify general-purpose
registers as operands, and one 6-bit field to hold an sub-operation code. 32-bit instructions use this format.
15
10
opcode
reg2
reg1
imm
9
5 4
0 31
16
15
10
opcode
reg2
reg1
disp
9
5 4
0 31
16
15
10
opcode
disp
9
0 31
16
0
15
10
opcode
reg2
reg1
sub-opcode
RFU
9
5 4
0 31
26 25
16
PD70741
52
15.2 Instruction Mnemonic (In Alphabetical Order)
The list of mnemonics is shown below.
This section lists the instructions incorporated in the V821 along with their operations. The instructions are listed
in the instruction mnemonic's alphabetical order to allow users to use this section as a quick reference or dictionary.
The conventions used in the list are shown below.
Identifier
Description
reg1
General-purpose register (Used as a source register)
reg2
General-purpose register (Used mainly as a destination register and occasionally as a source register)
imm5
5-bit immediate
imm16
16-bit immediate
disp9
9-bit displacement
disp16
16-bit displacement
disp26
26-bit displacement
regID
System register number
vector adr
Trap handler address that corresponds to a trap vector
ADD
Mnemonic of instruction
reg1, reg2
Identifier of operand
I
Instruction format
(See Section 15.1.)
*
*
*
*
Instruction mnemonic
Legend
Operand (s)
Format
Instruction function
CY OV
S
Z
Flag operation
-
*
0
1
Remains unchanged
Inverts the previous value
Changes to 0
Changes to 1
PD70741
53
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (1/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
ADD
reg1, reg2
I
*
*
*
*
Addition:
Adds the word data in the reg2-specified register and
the word data in the reg1-specified register, then
stores the result into the reg2-specified register.
ADD
imm5, reg2
II
*
*
*
*
Addition:
Sign-extends the 5-bit immediate data to 32 bits, and
adds the extended immediate data and the word data
in the reg2-specified register, then stores the result
into the reg2-specified register.
ADDF.S
reg1, reg2
VII
*
0
*
*
Floating-point addition:
Adds the single-precision floating-point data in the
reg2-specified register and the single-precision floating-
point data in the reg1-specified register, then restores
the result into the reg2-specified register while changing
flags according to the result.
ADDI
imm16, reg1, reg2
V
*
*
*
*
Addition:
Sign-extends the 16-bit immediate data to 32 bits, and
adds the extended immediate data and the word data
in the reg1-specified register, then stores the result
into the reg2-specified register.
AND
reg1, reg2
I
-
0
*
*
AND:
Performs the logical AND operation on the word data
in the reg2-specified register and the word data in the
reg1-specified register, then stores the result into the
reg2-specified register.
ANDBSU
-
II
-
-
-
-
Transfer after ANDing bit strings:
Performs a logical AND operation on a source bit
string and a destination bit string, then transfers the
result to the destination bit string.
ANDI
imm16, reg1, reg2
V
-
0
0
*
AND:
Sign-extends the 16-bit immediate data to 32 bits, and
performs a logical AND operation on the extended
immediate data and the word data in the reg1-specified
register, then stores the result into the reg2-specified
register.
ANDNBSU
-
II
-
-
-
-
Transfer after NOTting a bit string then ANDing it with
another bit string:
Performs a logical AND operation on a destination bit
string and the 1's complement of a source bit string,
then transfers the result to the destination bit string.
BC
disp9
III
-
-
-
-
Conditional branch (if Carry):
PC relative branch
BE
disp9
III
-
-
-
-
Conditional branch (if Equal):
PC relative branch
BGE
disp9
III
-
-
-
-
Conditional branch (if Greater than or Equal):
PC relative branch
BGT
disp9
III
-
-
-
-
Conditional branch (if Greater than):
PC relative branch
PD70741
54
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (2/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
BH
disp9
III
-
-
-
-
Conditional branch (if Higher):
PC relative branch
BL
disp9
III
-
-
-
-
Conditional branch (if Lower):
PC relative branch
BLE
disp9
III
-
-
-
-
Conditional branch (if Less than or Equal):
PC relative branch
BLT
disp9
III
-
-
-
-
Conditional branch (if Less than):
PC relative branch
BN
disp9
III
-
-
-
-
Conditional branch (if Negative):
PC relative branch
BNC
disp9
III
-
-
-
-
Conditional branch (if Not Carry):
PC relative branch
BNE
disp9
III
-
-
-
-
Conditional branch (if Not Equal):
PC relative branch
BNH
disp9
III
-
-
-
-
Conditional branch (if Not Higher):
PC relative branch
BNL
disp9
III
-
-
-
-
Conditional branch (if Not Lower):
PC relative branch
BNV
disp9
III
-
-
-
-
Conditional branch (if Not Overflow):
PC relative branch
BNZ
disp9
III
-
-
-
-
Conditional branch (if Not Zero):
PC relative branch
BP
disp9
III
-
-
-
-
Conditional branch (if Positive):
PC relative branch
BR
disp9
III
-
-
-
-
Unconditional branch:
PC relative branch
BV
disp9
III
-
-
-
-
Conditional branch (if Overflow):
PC relative branch
BZ
disp9
III
-
-
-
-
Conditional branch (if Zero):
PC relative branch
CAXI
disp16 [reg1], reg2
VI
*
*
*
*
Inter-processor synchronization in a multi-processor
system
CMP
reg1, reg2
I
*
*
*
*
Comparison:
Subtracts the word data in the reg1-specified register
from that for reg2 for comparison, then changes flags
according to the result.
CMP
imm5, reg2
II
*
*
*
*
Comparison:
Sign-extends the 5-bit immediate data to 32 bits, and
subtracts the extended immediate data from the word
data in the reg2-specified register for comparison,
then changes flags according to the result.
CMPF.S
reg1, reg2
VII
*
0
*
*
Floating-point comparison:
Subtracts the single-precision floating-point data in
the reg1-specified register from that for reg2 for
comparison, then changes flags according to the
result.
PD70741
55
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (3/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
CVT.SW
reg1, reg2
VII
-
0
*
*
Data conversion from floating-point to integer:
Converts the single-precision floating-point data in the
reg1-specified register into an integer data, then stores
the result into the reg2-specified register while changing
flags according to the result.
CVT.WS
reg1, reg2
VII
*
0
*
*
Data conversion from integer to floating-point:
Converts the integer data in the reg1-specified register
into a single-precision floating-point data, then stores
the result into the reg2-specified register while changing
flags according to the result.
DIV
reg1, reg2
I
-
*
*
*
Signed division:
Divides the word data in the reg2-specified register by
that for reg1 with their sign bits validated, then stores
the quotient into the reg2-specified register and the
remainder into r30. Division is performed so that the
sign of the remainder matches that of the dividend.
DIVF.S
reg1, reg2
VII
*
0
*
*
Floating-point division:
Divides the single-precision floating-point data in the
reg2-specified register by that for reg1, then stores the
result into the reg2-specified register while changing
flags according to the result.
DIVU
reg1, reg2
I
-
0
*
*
Unsigned division:
Divides the word data in the reg2-specified register by
that for reg1 with their data handled as unsigned data,
then stores the quotient into the reg2-specified register
and the remainder into r30. Division is performed so
that the sign of the remainder matches that of the
dividend.
HALT
-
II
-
-
-
-
Processor stop
IN.B
disp16 [reg1], reg2
VI
-
-
-
-
Port input:
Sign-extends the 16-bit displacement to 32 bits, and
adds the extended displacement and the content of
the reg1-specified register to generate a 32-bit unsigned
port address, then reads the byte data located at the
generated port address, zero-extends the byte data to
32 bits, and stores the result into the reg2-specified
register.
IN.H
disp16 [reg1], reg2
VI
-
-
-
-
Port input:
Sign-extends the 16-bit displacement to 32 bits, and
adds the extended displacement and the content of
the reg1-specified register to generate a 32-bit unsigned
port address, then reads the halfword data located at
the generated port address while masking the address's
bit 0 to 0, zero-extends the halfword data to 32 bits,
and stores the result into the reg2-specified register.
PD70741
56
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (4/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
IN.W
disp16 [reg1], reg2
VI
-
-
-
-
Port input:
Sign-extends the 16-bit displacement to 32 bits, and
adds the extended displacement and the content of
the reg1-specified register to generate a 32-bit unsigned
port address, then reads the word data located at the
generated address while masking the address's bits
0 and 1 to 0, and stores the word into the reg2-
specified register.
JAL
disp26
IV
-
-
-
-
Jump and link:
Increments the current PC by 4, then saves it into r31,
and sign-extends the 26-bit displacement to 32 bits
while masking the displacement's bit 0 to 0, adds the
extended displacement and the PC value, loads the
PC with the addition result, so that the instruction
stored at the PC-pointing address is executed next.
JMP
[reg1]
I
-
-
-
-
Register-indirect unconditional branch:
Loads the PC with the jump address value in the reg1-
specified register while masking the value's bit 0 to 0,
so that the instruction stored at the address pointed
by the reg1-specified register is executed next.
JR
disp26
IV
-
-
-
-
Unconditional branch:
Sign-extends the 26-bit displacement to 32 bits while
masking bit 0 to 0, adds the result with the current PC
value, and loads the PC with the addition result so that
the instruction stored at the PC-pointing address is
executed next.
LD.B
disp16 [reg1], reg2
VI
-
-
-
-
Byte load:
Sign-extends the 16-bit displacement to 32 bits, and
adds the result with the content of the reg1-specified
register to generate the 32-bit unsigned address, then
reads the byte data located at the generated address,
sign-extends the byte data to 32 bits, and stores the
result into the reg2-specified register.
LD.H
disp16 [reg1], reg2
VI
-
-
-
-
Halfword load:
Sign-extends the 16-bit displacement to 32 bits, and
adds the result with the content of the reg1-specified
register to generate a 32-bit unsigned address while
masking its bit 0 to 0, then reads the halfword data
located at the generated address, sign-extends the
halfword data to 32 bits, and stores the result into the
reg2-specified register.
LD.W
disp16 [reg1], reg2
VI
-
-
-
-
Word load:
Sign-extends the 16-bit displacement to 32 bits and
adds the result with the content of the reg1-specified
register to generate a 32-bit unsigned address while
masking bits 0 and 1 to 0, then reads the word data
located at the generated address and stores the data
into the reg2-specified register.
PD70741
57
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (5/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
LDSR
reg2, regID
II
*
*
*
*
Loading system register:
Transfers the word data in the reg2-specified register
to the system register specified with the system register
number (regID).
MOV
reg1, reg2
I
-
-
-
-
Transferring data:
Loads the reg2-specified register with the word data
in of the reg1-specified register.
MOV
imm5, reg2
II
-
-
-
-
Transferring data:
Sign-extends the 5-bit immediate data to 32 bits, then
loads the reg2-specified register with the extended
immediate data.
MOVBSU
-
II
-
-
-
-
Transferring bit strings:
Loads the destination bit string with the source bit
string.
MOVEA
imm16, reg1, reg2
V
-
-
-
-
Addition:
Sign-extends the 16-bit immediate data to 32 bits,
adds it with the word data in the reg1-specified register,
then stores the addition result into reg2.
MOVHI
imm16, reg1, reg2
V
-
-
-
-
Addition:
Appends 16-bit zeros below the 16-bit immediate data
to form a 32-bit word data, then adds it with the word
data in the reg1-specified register, and stores the
result into the reg2-specified register.
MUL
reg1, reg2
I
-
*
*
*
Signed multiplication:
Signed-multiplies the word data in the reg2-specified
register by that for reg1, then separates the 64-bit
(double-word) result into two 32-bit data, and stores
the higher 32 bits into r30 and the lower 32 bits into
the reg2-specified register.
MULF.S
reg1, reg2
VII
*
0
*
*
Floating-point multiplication:
Multiplies the single-precision floating-point data in
the reg2-specified register by that for reg1, then stores
the result into the reg2-specified register while changing
flags according to the result.
MULU
reg1, reg2
I
-
*
*
*
Unsigned multiplication:
Multiplies the word data in the reg2-specified register
by that for reg1 while handling these data as unsigned
data, then separates the 64-bit (double-word) result
into two 32-bit data, and stores the higher 32 bits into
r30 and the lower 32 bits into the reg2-specified
register.
NOP
-
III
-
-
-
-
No operation
NOT
reg1, reg2
I
-
0
*
*
Logical NOT:
Obtains the 1's complement (logical NOT) of the
content of the reg1-specified register, then stores the
result into the reg2-specified register.
PD70741
58
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (6/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
NOTBSU
-
II
-
-
-
-
Transfer after NOTting a bit string:
Obtains the 1's complement (all bits inverted) of the
source bit string, then transfers the result to the
destination bit string.
OR
reg1, reg2
I
-
0
*
*
OR:
Performs a logical OR operation on the word data in
the reg2-specified register and that for reg1, then
stores the result into the reg2-specified register.
ORBSU
-
II
-
-
-
-
Transfer after ORing bit strings:
Performs a logical OR operation on the source and
destination bit strings, then transfers the result to the
destination bit string.
ORI
imm16, reg1, reg2
V
-
0
*
*
OR:
Zero-extends the 16-bit immediate data to 32 bits,
performs a logical OR operation on the extended data
and the word data in the reg1-specified register, then
stores the result into the reg2-specified register.
ORNBSU
-
II
-
-
-
-
Transfer after NOTting a bit string and ORing it with
another bit string:
Obtains the 1's complement (logical NOT) of the
source bit string, performs a logical OR operation on
the NOTted bit string and the destination bit string,
then transfers the result to the destination bit string.
OUT.B
reg2, disp16 [reg1]
VI
-
-
-
-
Port output:
Sign-extends the 16-bit displacement to 32 bits, adds
the extended value and the content of the reg1-
specified register to generate a 32-bit unsigned port
address, then outputs the lowest 8 bits (= 1 byte) of
the reg2-specified register onto the port pins
corresponding to the generated port address.
OUT.H
reg2, disp16 [reg1]
VI
-
-
-
-
Port output:
Sign-extends the 16-bit displacement to 32 bits, adds
the extended value and the content of the reg1-
specified register to generate a 32-bit unsigned port
address with its bit 0 masked to 0, then outputs the
lowest 16 bits (= 1 halfword) of the reg2-specified
register onto the port pins corresponding to the generated
port address.
OUT.W
reg2, disp16 [reg1]
VI
-
-
-
-
Port output:
Sign-extends the 16-bit displacement to 32 bits, adds
the extended value and the content of the reg1-
specified register to generate a 32-bit unsigned port
address with its bits 0 and 1 masked to 0, then outputs
the 32 bits (= 1 word) of the reg2-specified register
onto the port pins corresponding to the generated port
address.
PD70741
59
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (7/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
RETI
-
II
*
*
*
*
Return from a trap or interrupt routine:
Reads the restore PC and PSW from the system
registers and loads them to the due places to return
from a trap or interrupt routine to the original operation
flow.
SAR
reg1, reg2
I
*
0
*
*
Arithmetic right shift:
Shifts every bit of the word data in the reg2-specified
register to the right by the number of times specified
with the reg1-specified register's lowest 5 bits, then
stores the result into the reg2-specified register. In
arithmetic right shift operations, the MSB is loaded
with the LSB value at each shift.
SAR
imm5, reg2
II
*
0
*
*
Arithmetic right shift:
Zero-extends the 5-bit immediate data to 32 bits, shifts
every bit of the word data in the reg2-specified register
to the right by the number of times specified with the
extended immediate data, then stores the result into
the reg2-specified register.
SCH0BSU
-
II
-
-
-
*
Searching 0s in a bit string:
SCH0BSD
-
II
-
-
-
*
Searches "0" bits in the source bit string, and loads r30
and r27 with the address of the bit next to the first
detected "0" bit, then r29 with the number of bits
skipped until the first "0" bit is detected, and r28 with
the value subtracted by the r29 value.
SCH1BSU
-
II
-
-
-
-
Searching 1s in a bit string:
SCH1BSD
-
II
-
-
-
-
Searches 1s in the source bit string, and loads r30 and
r27 with the bit address next to the first detected "1"
bit, then r29 with the number of bits skipped until the
first "1" is detected, and r28 with the value subtracted
by the r29 value.
SETF
imm5, reg2
II
-
-
-
-
Flag condition setting:
Sets the reg2-specified register to 1 if the condition
flag value matches the lowest 4 bits of the 5-bit
immediate data, and sets the reg2-specified register
to 0 when they do not match.
SHL
reg1, reg2
I
*
0
*
*
Logical left shift:
Shifts every bit of the word data in the reg2-specified
register to the left by the number of times specified
with the reg1-specified register's lowest 5 bits, then
stores the result into the reg2-specified register. In
logical left shift operations, the LSB is loaded with 0
at each shift.
PD70741
60
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (8/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
SHL
imm5, reg2
II
*
0
*
*
Logical left shift:
Zero-extends the 5-bit immediate data to 32 bits, shifts
every bit of the word data in the reg2-specified register
to the left by the number of times specified by the
extended immediate data, then stores the result into
the reg2-specified register.
SHR
reg1, reg2
I
*
0
*
*
Logical right shift:
Shifts every bit of the word data in the reg2-specified
register to the right by the number of times specified
with the reg1-specified register's lowest 5 bits, then
stores the result into the reg2-specified register. In
logical right shift operations, the MSB is loaded with
0 at each shift.
SHR
imm5, reg2
II
*
0
*
*
Logical right shift:
Zero-extends the 5-bit immediate data to 32 bits, shifts
every bit of the word data in the reg2-specified register
to the right by the number of times specified by the
extended immediate data, then stores the result into
the reg2-specified register.
ST.B
reg2, disp16 [reg1]
VI
-
-
-
-
Byte store:
Sign-extends the 16-bit displacement to 32 bits and
adds the 32-bit displacement and the content of the
reg1-specified register to generate a 32-bit unsigned
address, then transfers the reg2-specified register's
lowest 8 bits to the generated address.
ST.H
reg2, disp16 [reg1]
VI
-
-
-
-
Halfword store:
Sign-extends the 16-bit displacement to 32 bits with
its bit 0 masked to 0, and adds the content of the reg1-
specified register and the 32-bit displacement to generate
a 32-bit unsigned address, then transfers the reg2-
specified register's lower 16 bits to the generated
address.
ST.W
reg2, disp16 [reg1]
VI
-
-
-
-
Word store:
Sign-extends the 16-bit displacement to 32 bits with
its bits 0 and 1 masked to 0, and adds the reg1-
specified register and the 32-bit displacement to generate
a 32-bit unsigned address, then transfers the word
data of the reg2-specified register to the generated
address.
STSR
regID, reg2
II
-
-
-
-
Storing system register contents:
Loads the reg2-specified register with the content of
the system register specified by the system register
number (regID).
SUB
reg1, reg2
I
*
*
*
*
Subtraction:
Subtracts the word data in the reg1-specified register
from that in the reg2-specified register, then stores the
result into the reg2-specified register.
PD70741
61
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (9/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
SUBF.S
reg1, reg2
VII
*
0
*
*
Floating-point subtraction:
Subtracts the single-precision floating-point data in
the reg1-specified register from that for reg2, then
stores the result into the reg2-specified register while
changing flags according to the result.
TRAP
vector
II
-
-
-
-
Software trap:
Jumps to a trap handler address according to the
vector-specified trap vector (from 0 to 31) to start an
exception handling after completing all necessary
saving and presetting procedures as follows:
(1) Saving the restore PC and PSW into the FEPC
and FEPSW system registers, respectively, if the
PSW's EP flag = 1, or into the EIPC and EIPSW
system registers, respectively, if EP = 0
(2) Setting an exception code into the ECR's FECC
and FEPSW flags if the PSW's EP flag = 1, or into
the ECR's EICC if EP = 0
(3) Setting the PSW's ID flag and clearing the PSW's
AE flag
(4) Setting the PSW's NP flag if the PSW's EP flag
= 1, or setting the PSW's ID flag if EP = 0
TRNC.SW
reg1, reg2
VII
-
0
*
*
Conversion from floating-point data to integer:
Converts the single-precision floating-point data in the
reg1-specified register into an integer data, then stores
the result into the reg2-specified register while changing
flags according to the result.
XOR
reg1, reg2
I
-
0
*
*
Exclusive OR:
Performs a logical exclusive-OR operation on the
word data in the reg2-specified register and that for
reg1, then stores the result into the reg2-specified
register.
XORBSU
-
II
-
-
-
-
Transfer of exclusive ORed bit string:
Performs a logical exclusive-OR operation on the
source and destination bit strings, then transfers the
result to the destination bit string.
XORI
imm16, reg1, reg2
V
-
0
*
*
Exclusive OR:
Zero-extends the 16-bit immediate data to 32 bits and
performs a logical exclusive-OR operation on the
extended immediate data and the word data in the
reg1-specified register, then stores the result into the
reg2-specified register.
XORNBSU
-
II
-
-
-
-
Transfer after exclusive-ORing a NOTted bit string
and another bit string:
Obtains the 1's complement (NOT) of the source bit
string, and exclusive-ORs it with the destination bit
string, then transfers the result to the destination bit
string.
PD70741
62
16. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
-0.5 to +7.0
V
Input voltage
V
I
V
DD
= +5.0 V
10 %
-0.5 to V
DD
+ 0.3
V
Clock input voltage
V
K
V
DD
= +5.0 V
10 %
-0.5 to V
DD
+ 0.3
V
Output voltage
V
O
V
DD
= +5.0 V
10 %
-0.5 to V
DD
+ 0.3
V
Operating ambient temperature
T
A
-40 to +85
C
Storage temperature
T
stg
-65 to +150
C
Cautions 1. Do not connect an output (or input/output) pin of an IC device directly to any other output (or
input/output) pin of the same device, or directly to V
DD
, V
CC
, or GND. Open-drain pins and
open-collector pins can, however, be connected directly to each other. Note, however, that
these restrictions do not apply to those high-impedance pins that are provided with an external
circuit for which timings have been designed such that no output contention occurs.
2. Absolute maximum ratings are rated values beyond which some physical damages may be
caused to the product; if any of the parameters in the table above exceeds its rated value even
for a moment, the quality of the product may deteriorate. Be sure to use the product with a
moderate value within the rated range.
The standard values and conditions listed in the DC and AC characteristics tables indicate
the ranges in which the normal operation and performance of the product can be guaranteed.
DC CHARACTERISTICS (T
A
= -40 to +85
C, V
DD
= +5.0 V
10 %)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Low-level clock input voltage
V
KL
-0.5
+0.6
V
High-level clock input voltage
V
KH
4.0
V
DD
+ 0.3
V
Low-level input voltage
V
IL1
Other than RESET, NMI, and INTPn
-0.5
+0.8
V
V
IL2
RESET, NMI, and INTPn
-0.5
+0.2V
DD
V
High-level input voltage
V
IH1
Other than RESET, NMI, and INTPn
2.2
V
DD
+ 0.3
V
V
IH2
RESET, NMI, and INTPn
0.8V
DD
V
DD
+ 0.3
V
Schmitt-triggered input hysteresis width V
SH
RESET, NMI, and INTPn
0.5
V
Low-level output voltage
V
OL
I
OL
= 2.5 mA
0.45
V
High-level output voltage
V
OH
I
OH
= -2.5 mA
0.7V
DD
V
I
OH
= -100
A
V
DD
- 0.4
V
Low-level input leakage current
I
LIL
V
IN
= 0 V
-10
A
High-level input leakage current
I
LIH
V
IN
= V
DD
10
A
Low-level output leakage current
I
LOL
V
O
= 0 V
-10
A
High-level output leakage current
I
LOH
V
O
= V
DD
10
A
Supply current
I
DD
Operation (f = 25 MHz)
100
150
mA
HALT (f = 25 MHz)
18
45
mA
IDLE (f = 25 MHz)
4
35
mA
STOP
5
20
A
PD70741
63
CAPACITANCE (T
A
= 25
C, V
DD
= +5.0 V
10 %)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Input capacitance
C
I
fc = 1 MHz
15
pF
Input/output capacitance
C
IO
15
pF
PD70741
64
AC CHARACTERISTICS (T
A
= -40 to +85
C, V
DD
= +5.0 V
10 %)
AC Test Input Waveform (Other than RESET, NMI, and INTPn)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Input rise time
1
t
R
7
ns
Input fall time
2
t
F
7
ns
AC Test Input Waveform (RESET, NMI, and INTPn)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Schmitt-triggered input rise time
3
t
RS
10
ns
Schmitt-triggered input fall time
4
t
FS
10
ns
AC Test Output Waveform
Load Condition
1
2
V
DD
0 V
2.2 V
0.8 V
2.2 V
0.8 V
Test
points
3
4
V
DD
0 V
0.8V
DD
0.8 V
0.8V
DD
0.8 V
Test
points
2.2 V
0.8 V
2.2 V
0.8 V
Test
points
V821 output pin
C
L
= 100 pF
PD70741
65
RECOMMENDED OSCILLATION CIRCUIT
(a) Connecting a ceramic resonator
(Murata Mfg. Co., Ltd.: T
A
= -20 to +80
C, TDK Corp.: T
A
= -40 to +85
C)
X1
X2
C1
C2
Cautions 1. The oscillation circuit should be placed as close to the X1 and X2 pins as
possible.
2. Do not draw other signal lines in the area enclosed by broken lines.
3. Throughly evaluate the matching between the PD70741 and the oscillation
circuit.
Manufacturer
Product name
Oscillation settling
time (MAX.)
T
OST
(ms)
Recommended circuit
constants
C1 (pF)
30
30
5.00
CSA5.00MG
Murata Mfg.
Co., Ltd
C2 (pF)
Oscillating voltage
range
MIN. (V)
MAX. (V)
4.5
5.5
0.102
Built-in
Built-in
5.00
CST5.00MGW
4.5
5.5
0.102
30
30
4.00
CSA4.00MG
4.5
5.5
0.1
Built-in Built-in
4.00
CST4.00MGW
4.5
5.5
0.1
30
30
3.20
CSA3.20MG
2.7
3.3
0.102
4.5
5.5
0.102
Built-in
Built-in
3.20
CST3.20MGW
2.7
3.3
0.102
4.5
5.5
0.102
100
100
2.00
CSA2.00MG040
2.7
3.3
0.498
4.5
5.5
0.498
Built-in
Built-in
2.00
CST2.00MG040
2.7
3.3
0.498
4.5
5.5
0.498
Built-in
Built-in
5.00
CCR5.0MC3
TDK
4.5
5.5
0.28
Built-in
Built-in
5.00
FCR5.0MC5
4.5
5.5
0.22
Built-in
Built-in
4.00
CCR4.0MC3
4.5
5.5
0.3
Built-in
Built-in
4.00
FCR4.0MC5
4.5
5.5
0.22
Built-in
Built-in
3.20
CCR3.2MC3
2.7
5.5
0.38
Built-in
Built-in
2.00
CCR2.0MC33
2.7
5.5
0.36
Oscillation
frequency
fxx (MHz)
PD70741
66
(b) External clock input
X1
X2
Open
External clock
High-speed CMOS inverter
PD70741
67
(1) Clock input timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
External clock cycle
5
t
CYX
Direct mode
20
ns
PLL mode
200
500
ns
External clock high-level width
6
t
XKH
Direct mode
7
ns
PLL mode
85
ns
External clock low-level width
7
t
XKL
Direct mode
7
ns
PLL mode
85
ns
External clock rise time
8
t
XKR
Direct mode
3
ns
PLL mode
15
ns
External clock fall time
9
t
XKF
Direct mode
3
ns
PLL mode
15
ns
(2) CLKOUT output timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
CLKOUT cycle
10
t
CYK
40
100
ns
CLKOUT high-level width
11
t
KKH
0.5T - 3
ns
CLKOUT low-level width
12
t
KKL
0.5T - 3
ns
CLKOUT rise time (0.8 V
2.2 V)
13
t
KR
5
ns
CLKOUT fall time (2.2 V
0.8 V)
14
t
KF
5
ns
Remark T: t
CYK
5
6
7
9
8
X1 (input)
2.2 V
0.8 V
CLKOUT (output)
2.2 V
0.8 V
10
11
12
13
14
PD70741
68
(3) Reset input timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Reset input width
15
t
WRL
Power-on reset
10
ms
STOP mode
10
ms
release
System reset
30
t
CYK
15
RESET (input)
PD70741
69
[MEMO]
PD70741
70
(4) SRAM, ROM, and I/O access timing
(a) Access timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address output delay (relative to CLKOUT
)
16
t
DKA
2
15
ns
Address output hold time (relative to CLKOUT
)
17
t
HKA
2
15
ns
CSn output delay (relative to CLKOUT
)
18
t
DKCS
2
15
ns
CSn output hold time (relative to CLKOUT
)
19
t
HKCS
2
15
ns
RD output delay (relative to CLKOUT
)
20
t
DKRD
2
15
ns
RD output hold time (relative to CLKOUT
)
21
t
HKRD
2
15
ns
WR output delay (relative to CLKOUT
)
22
t
DKWR
1
12
ns
WR output hold time (relative to CLKOUT
)
23
t
HKWR
1
12
ns
READY setup time (relative to CLKOUT
)
24
t
SRYK
6
ns
READY hold time (relative to CLKOUT
)
25
t
HKRY
6
ns
Data output delay (from float, relative to CLKOUT)
26
t
LZKDT
2
15
ns
Data output hold time (to float, relative to CLKOUT
)
27
t
HZKDT
2
15
ns
PD70741
71
(a) Access timing (2/2)
16
17
18
19
20
21
22
23
24
25
24
25
26
26
27
27
T1
T2
T2
CLKOUT (output)
Note
CS0-CS3 (output)
IORD, MRD (output)
IOWR, UMWR, LMWR
(output)
READY (input)
D0-D15 (input/output)
(ADC = 0) (write)
D0-D15 (input/output)
(ADC = 1) (write)
Note A0-A23 (output), UBE (output), BLOCK (output)
Remark Broken lines indicate high impedance.
PD70741
72
(b) Read timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Read cycle time
28
t
RC
(n + 2)T - 10
ns
Address access time
29
t
AA
(n + 2)T - 25
ns
Hold time from address to data input
30
t
ADH
0
ns
CSn access time
31
t
CSA
(n + 2)T - 25
ns
Hold time from CSn to data input
32
t
CDH
0
ns
Delay from CSn
to write data output (ADC = 0)
33
t
DCD0
0.5T - 10
ns
Delay from CSn
to write data output (ADC = 1)
34
t
DCD1
1T - 10
ns
RD access time
35
t
RDA
(n + 1.5)T - 25
ns
Hold time from RD to data input
36
t
RDH
0
ns
RD pulse width
37
t
RDP
(n + 1.5)T - 7
ns
RD high-level width
38
t
RDRDH
0.5T - 10
ns
Delay from RD
to write data output (ADC = 0)
39
t
DRD0
0.5T - 10
ns
Delay from RD
to write data output (ADC = 1)
40
t
DRD1
1T - 10
ns
Address valid time prior to RD
41
t
ARS
0.5T - 7
ns
CSn valid time prior to RD
42
t
CRS
0.5T - 7
ns
Remark T : t
CYK
n : Wait state count
PD70741
73
(b) Read timing (2/2)
T1
T2
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CLKOUT (output)
A0-A23, UBE (output)
CS0-CS3 (output)
IORD, MRD (output)
D0-D15 (input/output)
(ADC = 0)
D0-D15 (input/output)
(ADC = 1)
Remark Broken lines indicate high impedance.
PD70741
74
(c) Write timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Write cycle time
43
t
WC
(n + 2)T - 10
ns
CSn setup time (relative to WR
)
44
t
CW
(n + 1.5)T - 10
ns
Address setup time (relative to WR
)
45
t
AW
(n + 1.5)T - 10
ns
Address valid time prior to WR
46
t
AWS
0.5T - 7
ns
Address valid time after WR
47
t
AWH
0.5T - 10
ns
CSn valid time prior to WR
48
t
CWS
0.5T - 7
ns
CSn valid time after WR
49
t
CWH
0.5T - 10
ns
WR pulse width
50
t
WRP
(n + 1)T - 7
ns
Delay from WR
to data output (ADC = 0)
51
t
WDS0
-10
ns
Delay from WR
to data output (ADC = 1)
52
t
WDS1
0.5T - 10
ns
Data output valid time prior to WR (ADC = 0)
53
t
DWS0
(n + 1)T - 7
ns
Data output valid time prior to WR (ADC = 1)
54
t
DWS1
(n + 0.5)T - 7
ns
Data output valid time after WR
55
t
DWH
0.5T - 10
ns
Remark T : t
CYK
n : Wait state count
PD70741
75
(c) Write timing (2/2)
T1
T2
43
46
47
48
49
50
51
53
55
55
54
52
45
44
Remark Broken lines indicate high impedance.
CLKOUT (output)
A0-A23, UBE (output)
CS0-CS3 (output)
IOWR, UMWR, LMWR (output)
D0-D15 (input/output)
(ADC = 0)
D0-D15 (input/output)
(ADC = 1)
PD70741
76
(5) DRAM access timing (when DRAM is directly connected)
(a) Read timing (normal access: off-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay from RD
to write data output (ADC = 0)
39
t
DRD0
0.5T - 10
ns
Delay from RD
to write data output (ADC = 1)
40
t
DRD1
1T - 10
ns
Read/write cycle time
56
t
RC
(w + 4)T - 10
ns
RAS access time
57
t
RAC
(w + 2)T - 20
ns
CAS access time
58
t
CAC
(w + 1)T - 20
ns
Access time from column address
59
t
AA
(w + 1)T - 3
ns
Output enable access time
60
t
OEA
1.5T - 20
ns
Output buffer turn-off delay (relative to CAS)
61
t
OFF
0
ns
Output buffer turn-off delay (relative to MRD)
62
t
OEZ
0
ns
RD setup time (relative to RAS
)
63
t
OES
1.5T
ns
RAS precharge time
64
t
RP
1.5T - 10
ns
RAS pulse width
65
t
RAS
(w + 2.5)T - 20
ns
RAS column address delay
66
t
RAD
0.5T - 3
0.5T + 7
ns
RAS hold width (read)
67
t
RSH
(w + 1.5)T - 20
ns
CAS pulse width (read)
68
t
CAS
(w + 1)T - 15
ns
CAS hold width
69
t
CSH
(w + 2)T - 15
ns
RAS-CAS delay (read)
70
t
RCD
1T - 15
ns
RAS-CAS precharge time
71
t
CRP
1.5T
ns
CAS precharge time
72
t
CP
0.5T - 10
ns
Row address setup time
73
t
ASR
0.5T - 15
ns
Row address hold time
74
t
RAH
0.5T - 7
ns
Column address setup time (read)
75
t
ASC
0.5T - 15
ns
Column address hold time (read)
76
t
CAH
(w + 1)T - 15
ns
Column address read time relative to RAS
77
t
RAL
(w + 1.5)T
ns
Read command setup time
78
t
RCS
0.5T
ns
Read command hold time
79
t
RCH
0.5T - 15
ns
Remark T : t
CYK
w : Wait state count - 2
PD70741
77
(a) Read timing (normal access: off-page) (2/2)
39
40
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
T1
T2
T2
T2
COL.
COL.
ROW
CLKOUT (output)
A0-A23, UBE
(output)
RAS (output)
UCAS, LCAS
(output)
WE (output)
MRD (output)
D0-D15
(input/output)
(ADC = 0)
D0-D15
(input/output)
(ADC = 1)
Remark Broken lines indicate high impedance.
PD70741
78
(b) Write timing (normal access: off-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Read/write cycle time
56
t
RC
(w + 4)T - 10
ns
RAS precharge time
64
t
RP
1.5T - 10
ns
RAS pulse width
65
t
RAS
(w + 2.5)T - 20
ns
RAS column address delay
66
t
RAD
0.5T - 3
0.5T + 7
ns
CAS hold width
69
t
CSH
(w + 2)T - 15
ns
RAS-CAS precharge time
71
t
CRP
1.5T
ns
Row address setup time
73
t
ASR
0.5T - 15
ns
Row address hold time
74
t
RAH
0.5T - 7
ns
Column address read time relative to RAS
77
t
RAL
(w + 1.5)T
ns
RAS hold width (write)
80
t
RSH
1.5T - 20
ns
CAS pulse width (write)
81
t
CAS
1T - 15
ns
RAS-CAS delay (write)
82
t
RCD
(w + 1)T - 15
ns
Column address setup time (write)
83
t
ASC
(w + 0.5)T - 15
ns
Column address hold time (write)
84
t
CAH
1T - 15
ns
Write command hold time
85
t
WCH
0.5T - 10
ns
Write command read time relative to RAS
86
t
RWL
1.5T
ns
Write command read time relative to CAS
87
t
CWL
1T
ns
Data setup time (relative to CAS
)
88
t
DS
0.5T - 15
ns
Data hold time (relative to CAS
)
89
t
DH
1T - 20
1T + 10
ns
Write command setup time
90
t
WCS
0.5T - 15
ns
Remark T : t
CYK
w : Wait state count - 2
PD70741
79
(b) Write timing (normal access: off-page) (2/2)
CLKOUT (output)
56
64
65
66
69
71
73
74
77
80
81
82
83
84
85
86
87
88
88
89
89
90
T1
T2
T2
T2
COL.
ROW
COL.
A0-A23, UBE
(output)
RAS (output)
UCAS, LCAS
(output)
WE (output)
D0-D15
(input/output)
(ADC = 0)
D0-D15
(input/output)
(ADC = 1)
MRD (output)
Remark Broken lines indicate high impedance.
PD70741
80
(c) READY input timing (normal access)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
READY setup time (relative to CLKOUT
)
24
t
SRYK
6
ns
READY hold time (relative to CLKOUT
)
25
t
HKRY
6
ns
T2
T2
T2
24
24
25
25
CLKOUT (output)
UCAS, LCAS (output)
(read)
UCAS, LCAS (output)
(write)
READY (input)
PD70741
81
[MEMO]
PD70741
82
(d) Read timing (high-speed page access: on-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay from RD
to write data output (ADC = 0)
39
t
DRD0
0.5T - 10
ns
Delay from RD
to write data output (ADC = 1)
40
t
DRD1
1T - 10
ns
CAS access time
58
t
CAC
(w + 1)T - 20
ns
Access time from column address
59
t
AA
(w + 1)T - 3
ns
Output enable access time
60
t
OEA
1.5T - 20
ns
Output buffer turn-off delay (relative to CAS)
61
t
OFF
0
ns
Output buffer turn-off delay (relative to MRD)
62
t
OEZ
0
ns
RD setup time (relative to RAS
)
63
t
OES
1.5T
ns
RAS hold width (read)
67
t
RSH
(w + 1.5)T - 20
ns
CAS pulse width (read)
68
t
CAS
(w + 1)T - 15
ns
CAS precharge time
72
t
CP
0.5T - 10
ns
Column address setup time (read)
75
t
ASC
0.5T - 15
ns
Column address hold time (read)
76
t
CAH
(w + 1)T - 15
ns
Cycle time in high-speed page mode
91
t
PC
1.5T - 10
ns
Access time from CAS precharge
92
t
ACP
2T - 20
ns
RAS hold time relative to CAS precharge
93
t
RHCP
2T
ns
Read command setup time
94
t
RCS
0.5T
ns
Read command hold time
95
t
RCH
0.5T - 15
ns
Remark T : t
CYK
w : 0
PD70741
83
(d) Read timing (high-speed page access: on-page) (2/2)
T1
T2
39
40
58
59
60
61
62
63
67
68
72
75
76
91
92
93
94
95
COL.
CLKOUT (output)
A0-A23, UBE (output)
RAS (output)
UCAS, LCAS (output)
WE (output)
MRD (output)
D0-D15 (input/output)
(ADC = 0)
D0-D15 (input/output)
(ADC = 1)
Remark Broken lines indicate high impedance.
PD70741
84
(e) Write timing (high-speed page access: on-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
CAS precharge time
72
t
CP
0.5T - 10
ns
RAS hold width (write)
80
t
RSH
1.5T - 20
ns
CAS pulse width (write)
81
t
CAS
1T - 15
ns
Column address setup time (write)
83
t
ASC
(w + 0.5)T - 15
ns
Column address hold time (write)
84
t
CAH
1T - 15
ns
Write command hold time
85
t
WCH
0.5T - 10
ns
Write command read time relative to RAS
86
t
RWL
1.5T
ns
Write command read time relative to CAS
87
t
CWL
1T
ns
Data setup time (relative to CAS
)
88
t
DS
0.5T - 15
ns
Data hold time (relative to CAS
)
89
t
DH
1T - 20
1T + 10
ns
Write command setup time
90
t
WCS
0.5T - 15
ns
Cycle time in high-speed page mode
91
t
PC
1.5T - 10
ns
Remark T : t
CYK
w : 0
PD70741
85
(e) Write timing (high-speed page access: on-page) (2/2)
T1
T2
T2
T1
T2
Note 1
Note 2
72
80
81
81
83
83
84
84
85
85
86
87
87
88
88
89
89
90
90
91
COL.
COL.
CLKOUT (output)
A0-A23, UBE (output)
RAS (output)
UCAS, LCAS (output)
WE (output)
MRD (output)
D0-D15 (input/output)
Notes 1.
When ADC = 1 and other than DRAM access was performed in the
previous cycle
2.
Other than the above
Remark Broken lines indicate high impedance.
PD70741
86
(6) DRAM access timing (when a control circuit is configured using a gate array or other devices)
(a) Read timing (normal access: off-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address output delay (relative to CLKOUT)
96
t
DKA
2
15
ns
Address output hold time (relative to CLKOUT
)
97
t
HKA
2
15
ns
RAS output delay (relative to CLKOUT
)
98
t
DKRAS
1
12
ns
RAS output hold time (relative to CLKOUT
)
99
t
HKRAS
1
12
ns
CAS output delay (relative to CLKOUT
)
100
t
DKCAS
1
12
ns
CAS output hold time (relative to CLKOUT
)
101
t
HKCAS
1
12
ns
MRD output delay (relative to CLKOUT
)
102
t
DKRD
2
15
ns
MRD output hold time (relative to CLKOUT
)
103
t
HKRD
2
15
ns
Data input setup time (relative to CLKOUT
)
104
t
SDK
6
ns
Data input hold time (relative to CLKOUT
)
105
t
HKD
6
ns
PD70741
87
(a) Read timing (normal access: off-page) (2/2)
96
98
96
96
97
99
100
102
103
104
105
104
105
101
T1
T2
T2
T2
COL.
ROW
COL.
CLKOUT (output)
A0-A23, UBE
(output)
RAS (output)
UCAS, LCAS
(output)
WE (output)
MRD (output)
D0-D15
(input/output)
(ADC = 0)
D0-D15
(input/output)
(ADC = 1)
Remark Broken lines indicate high impedance.
PD70741
88
(b) Write timing (normal access: off-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address output delay (relative to CLKOUT
)
96
t
DKA
2
15
ns
Address output hold time (relative to CLKOUT
)
97
t
HKA
2
15
ns
RAS output delay (relative to CLKOUT
)
98
t
DKRAS
1
12
ns
RAS output hold time (relative to CLKOUT
)
99
t
HKRAS
1
12
ns
CAS output delay (relative to CLKOUT
)
100
t
DKCAS
1
12
ns
CAS output hold time (relative to CLKOUT
)
101
t
HKCAS
1
12
ns
WE output delay (relative to CLKOUT
)
106
t
DKWE
1
12
ns
WE output hold time (relative to CLKOUT
)
107
t
HKWE
1
12
ns
Data active delay (from float, relative to CLKOUT)
108
t
LZKDT
2
15
ns
Data inactive hold time (to float, relative to CLKOUT
)
109
t
HZKDT
2
15
ns
PD70741
89
(b) Write timing (normal access: off-page) (2/2)
T1
T2
T2
T2
96
98
96
96
97
99
100
107
106
108
109
109
108
101
CLKOUT (output)
A0-A23, UBE
(output)
RAS (output)
UCAS, LCAS
(output)
WE (output)
MRD (output)
D0-D15
(input/output)
(ADC = 0)
D0-D15
(input/output)
(ADC = 1)
Remark Broken lines indicate high impedance.
COL.
COL.
ROW
PD70741
90
(c) READY input timing (normal access)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
READY setup time (relative to CLKOUT
)
24
t
SRYK
6
ns
READY hold time (relative to CLKOUT
)
25
t
HKRY
6
ns
T2
T2
T2
24
25
24
25
CLKOUT (output)
UCAS, LCAS (output)
(read)
UCAS, LCAS (output)
(write)
READY (input)
PD70741
91
[MEMO]
PD70741
92
(d) Read timing (high-speed page access: on-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address output delay (relative to CLKOUT)
96
t
DKA
2
15
ns
Address output hold time (relative to CLKOUT
)
97
t
HKA
2
15
ns
CAS output delay (relative to CLKOUT
)
100
t
DKCAS
1
12
ns
CAS output hold time (relative to CLKOUT
)
101
t
HKCAS
1
12
ns
MRD output delay (relative to CLKOUT
)
102
t
DKRD
2
15
ns
MRD output hold time (relative to CLKOUT
)
103
t
HKRD
2
15
ns
Data input setup time (relative to CLKOUT
)
104
t
SDK
6
ns
Data input hold time (relative to CLKOUT
)
105
t
HKD
6
ns
PD70741
93
(d) Read timing (high-speed page access: on-page) (2/2)
T1
T2
CLKOUT (output)
A0-A23, UBE (output)
RAS (output)
UCAS, LCAS (output)
WE (output)
MRD (output)
D0-D15 (input/output)
(ADC = 0)
D0-D15 (input/output)
(ADC = 1)
Remark Broken lines indicate high impedance.
96
97
100
102
104
105
104
105
103
101
COL.
PD70741
94
(e) Write timing (high-speed page access: on-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address output delay (relative to CLKOUT
)
96
t
DKA
2
15
ns
Address output hold time (relative to CLKOUT
)
97
t
HKA
2
15
ns
CAS output delay (relative to CLKOUT
)
100
t
DKCAS
1
12
ns
CAS output hold time (relative to CLKOUT
)
101
t
HKCAS
1
12
ns
WE output delay (relative to CLKOUT
)
106
t
DKWE
1
12
ns
WE output hold time (relative to CLKOUT
)
107
t
HKWE
1
12
ns
Data active delay (from float, relative to CLKOUT)
108
t
LZKDT
2
15
ns
Data inactive hold time (to float, relative to CLKOUT
)
109
t
HZKDT
2
15
ns
PD70741
95
(e) Write timing (high-speed page access: on-page) (2/2)
T1
T2
T2
T1
T2
Note 1
Note 2
COL.
COL.
CLKOUT (output)
A0-A23, UBE (output)
RAS (output)
UCAS, LCAS (output)
WE (output)
MRD (output)
D0-D15 (input/output)
Notes 1.
When ADC = 1 and other than DRAM access was performed in the
previous cycle
2.
Other than the above
Remark Broken lines indicate high impedance.
96
96
97
97
100
100
107
106
107
106
108
108
109
109
101
101
PD70741
96
(7) DRAM, CBR refresh timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
READY setup time (relative to CLKOUT
)
24
t
SRYK
6
ns
READY hold time (relative to CLKOUT
)
25
t
HKRY
6
ns
RAS pulse width
65
t
RAS
(w + 2.5)T - 20
ns
CAS setup time
110
t
CSR
1T - 20
ns
CAS hold time
111
t
CHR
(w + 2.5)T - 20
ns
Refresh pulse width
112
t
REF
(w + 2.5)T - 20
ns
RAS precharge to CAS hold time
113
t
RPC
4.5T - 20
ns
REFRQ active delay (relative to CLKOUT
)
114
t
DKREF
1
12
ns
REFRQ inactive delay (relative to CLKOUT
)
115
t
HKREF
1
12
ns
Remark T: t
CYK
w: Wait state count for CBR refresh
CLKOUT (output)
READY (input)
UCAS, LCAS (output)
RAS (output)
REFRQ (output)
24
25
24
25
65
114
115
112
111
113
110
110
TH
TH
TI
TH
TH
TH
TH
TH
TH
Remark In the above timing chart, w = 1 is assumed.
PD70741
97
(8) DRAM, CBR self-refresh timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
CAS setup time
110
t
CSR
1T - 20
ns
REFRQ active delay (relative to CLKOUT
)
114
t
DKREF
1
12
ns
REFRQ inactive delay (relative to CLKOUT
)
115
t
HKREF
1
12
ns
CAS hold time
116
t
CHS
-10
ns
RAS precharge time
117
t
RPS
4.5T - 20
ns
Remark T: t
CYK
CLKOUT (output)
UCAS, LCAS (output)
RAS (output)
REFRQ (output)
114
115
110
116
110
116
117
TI
TI
TH
TH
TH
TH
TH
TH
PD70741
98
(9) Page-ROM access timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Hold time from address to data input
30
t
ADH
0
ns
Hold time from CSn to data input
32
t
CDH
0
ns
Hold time from RD to data input
36
t
RDH
0
ns
Off-page address access time
118
t
OFPA
(n
OFF
+ 2)T - 25
ns
On-page address access time
119
t
ONPA
(n
ON
+ 2)T - 25
ns
Off-page CSn access time
120
t
OFCS
(n
OFF
+ 2)T - 25
ns
Off-page RD access time
121
t
OFRD
(n
OFF
+ 1.5)T - 25
ns
Remark T
: t
CYK
n
OFF
: Wait state count for off-page access (n
OFF
= 0-7)
n
ON
: Wait state count for on-page access (n
ON
= 0, 1)
PD70741
99
(9) Page-ROM access timing (2/2)
T1
T1
T2
Off-page access
On-page access
T2
T2
T2
CLKOUT (output)
A3-A23
Note 1
(output)
A0-A2
Note 2
(output)
CS3 (output)
MRD (output)
D0-D15
(input/output)
Remark Broken lines indicate high impedance.
30
30
32
36
118
120
119
121
Notes 1. The address pins to be used vary with the settings of bits MA5 to MA3 of the
page-ROM configuration register (PRC).
2. The address pins to be used vary with the settings of bits MA5 to MA3 of the
page-ROM configuration register (PRC).
MA5
MA4
MA3
Address
0
0
0
A3-A23
0
0
1
A4-A23
0
1
1
A5-A23
1
1
1
A6-A23
MA5
MA4
MA3
Address
0
0
0
A0-A2
0
0
1
A0-A3
0
1
1
A0-A4
1
1
1
A0-A5
PD70741
100
(10) Bus hold timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
HLDRQ setup time (relative to CLKOUT
)
122
t
SHQK
6
ns
HLDRQ hold time (relative to CLKOUT
)
123
t
HKHQ
6
ns
HLDAK output delay (relative to CLKOUT
)
124
t
DKHA
2
15
ns
HLDAK output hold time (relative to CLKOUT
)
125
t
HKHA
2
15
ns
Delay from address float to HLDAK
126
t
DAHA
0.5T - 10
ns
Delay from HLDAK
to address output
127
t
DHAA
0.5T - 10
ns
Delay from data float to HLDAK
128
t
DDHA
1.5T - 15
ns
Delay from HLDAK
to data output
129
t
DHAD
2T - 15
ns
Remark T: t
CYK
PD70741
101
(10) Bus hold timing (2/2)
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A0-A23 (output)
D0-D15 (input/output)
TI
T1
T1
T2
TI
TH
TH
TH
TH
123
122
122
124
127
129
128
126
Note 1
MRD (output)
CS3 (output)
RAS (output)
Note 2
Notes 1. The level existing immediately before the high-impedance state is held internally.
Remark Broken lines indicate high impedance.
2. CS2-CS0 (output), UCAS (output), LCAS (output), LMWR/WE (output), UMWR (output),
IORD (output), IOWR (output)
125
PD70741
102
(11) DMAC timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
DREQn setup time (relative to CLKOUT
)
130
t
SDQK
6
ns
DREQn hold time (relative to CLKOUT
)
131
t
HKDQ
6
ns
DACKn output delay (relative to CLKOUT
)
132
t
DKDAK
2
15
ns
DACKn output hold time (relative to CLKOUT
)
133
t
HKDAK
2
15
ns
TC output delay (relative to CLKOUT
)
134
t
DKTC
2
15
ns
TC output hold time (relative to CLKOUT
)
135
t
HKTC
2
15
ns
Delay from WR
to RD
136
t
DWRD
0.5T - 10
ns
Delay from DACK
to RD
137
t
DAKRD
0.5T - 10
ns
Delay from DACK
to WR
138
t
DAKWR
0.5T - 10
ns
Delay from RD
to DACK
139
t
RDDAK
-4
ns
Delay from WR
to DACK
140
t
WRDAK
0.5T - 10
ns
Delay from CAS
to IOWR
(DRAM read)
141
t
CASWR
(n + 1)T - 10
ns
Delay from IOWR
to CAS
(DRAM read)
142
t
WRCAS
0.5T - 10
ns
Delay from IORD
to CAS
(DRAM write)
143
t
RDCAS
(n + 0.5)T - 10
ns
Remark T: t
CYK
n: DMA wait state count
PD70741
103
(11) DMAC timing (2/2)
CLKOUT (output)
DREQ0, DREQ1
(input)
DACK0, DACK1
(output)
A0-A23, UBE
(output)
MRD, IORD
(output)
LMWR/WE, UMWR,
IOWR (output)
LCAS, UCAS
(output) (read)
LCAS, UCAS
(output) (write)
TC (output)
130
131
132
133
140
139
137
138
136
136
142
141
142
141
143
143
134
135
T2
T1
T2
T1
T2
TI
T3
PD70741
104
(12) INTPn input setup time, hold time
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
INTPn input low setup time
144
t
SILK
9
ns
INTPn input high setup time
145
t
SIHK
9
ns
INTPn input low pulse width
146
t
CYIL
2
t
CYK
INTPn input high-level width
147
t
CYIH
2
t
CYK
(13) NMI input
The NMI pin incorporates a noise eliminator which is based on an analog delay (60 to 300 ns). The input setup
time and input hold time are not, therefore, specified for NMI.
The NMI pin accepts a level input, such that the input level must be held until the acceptance of the input is
confirmed after a branch to the handler.
CLKOUT (output)
INTPn (input)
(edge mode)
INTPn (input)
(level mode)
145
147
146
144
144
NMI (input)
Internal NMI
signal
CPU processing
Analog delay
Analog delay
Analog delay
Normal processing
Nonmaskable interrupt handling
After confirming acceptance,
de-activate NMI from the interrupt
handler.
PD70741
105
(14) RPU block timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Timer clock cycle time
148
t
TCYK
4
t
CYK
Timer clock high-level width
149
t
TKH
2
t
CYK
Timer clock low-level width
150
t
TKL
2
t
CYK
Timer clear cycle time
151
t
TCLRY
4
t
CYK
Timer clear high-level width
152
t
TCLRH
2
t
CYK
Timer clear low-level width
153
t
TCLRL
2
t
CYK
Timer output high-level width
154
t
WTOH
2T - 7
ns
Timer output low-level width
155
t
WTOL
2T - 7
ns
Remark T: t
CYK
TI (input)
148
149
150
TCLR (input)
151
152
153
TO0n (input)
154
155
PD70741
106
(15) CSI timing
(a) Master mode
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Serial clock cycle time
156
t
CYSK
4
t
CYK
Serial clock high-level width
157
t
SKH
30
ns
Serial clock low-level width
158
t
SKL
30
ns
SI setup time (relative to SCLK
)
159
t
SSISK
20
ns
SI hold time (relative to SCLK
)
160
t
HSKSI
20
ns
SO output delay (relative to SCLK
)
161
t
DSKSO
30
ns
(b) Slave mode
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Serial clock cycle time
156
t
CYSK
4
t
CYK
Serial clock high-level width
157
t
SKH
30
ns
Serial clock low-level width
158
t
SKL
30
ns
SI setup time (relative to SCLK
)
159
t
SSISK
20
ns
SI hold time (relative to SCLK
)
160
t
HSKSI
20
ns
SO output delay (relative to SCLK
)
161
t
DSKSO
30
ns
SCLK (input/output)
SO (output)
SI (input)
156
158
161
159
160
157
Remark Broken lines indicate high impedance.
PD70741
107
17. PACKAGE DRAWINGS
100 PIN PLASTIC LQFP (FINE PITCH) (14
14)
ITEM
MILLIMETERS
INCHES
NOTE
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
S100GC-50-8EU
F
1.00
0.039
B
14.000.20
0.551+0.009
0.008
S
1.60 MAX.
0.063 MAX.
L
0.500.20
0.020+0.008
0.009
+0.009
0.008
C
14.000.20
0.551+0.009
0.008
A
16.000.20
0.6300.008
G
1.00
0.039
H
0.22
0.0090.002
I
0.08
0.003
J
0.50 (T.P.)
0.020 (T.P.)
K
1.000.20
0.039+0.009
0.008
N
0.08
0.003
P
1.400.05
0.0550.002
R
3
3
+7
3
+7
3
D
16.000.20
0.6300.008
M
Q
R
K
M
L
J
H
I
F
G
P
N
detail of lead end
M
0.17
0.007+0.001
0.003
+0.03
0.07
Q
0.100.05
0.0040.002
+0.05
0.04
1
25
26
50
100
76
75
51
C
D
S
A
B
PD70741
108
18. RECOMMENDED SOLDERING CONDITIONS
The
PD70741 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 18-1. Surface Mounting Type Soldering Conditions
PD70741GC-25-8EU: 100-pin plastic LQFP (fine pitch) (14
14
1.40 mm)
Soldering method
Soldering conditions
Recommended
condition symbol
Infrared reflow
Package peak temperature: 235
C, Duration: 30 sec. Max. (at 210
C or above),
IR35-107-2
Number of times: Twice Max., Time limit: 7 days
Note
(thereafter 10 hours prebaking
required at 125
C)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before
unpacking.
VPS
Package peak temperature: 215
C, Duration: 40 sec. Max. (at 200
C or above),
VP15-107-2
Number of times: Twice Max., Time limit: 7 days
Note
(thereafter 10 hours prebaking
required at 125
C)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before
unpacking.
Partial heating
Pin temperature: 300
C Max., Duration: 3 sec. Max. (per device side)
-
Note
For the storage period after dry-pack decapsulation, storage conditions are Max. 25
C, 65 % RH.
Caution Use of more than one soldering method should be avoided (except for partial heating).
PD70741
109
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD70741
110
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
J98. 2
PD70741
111
[MEMO]
PD70741
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
V810, V821, and V810 Family are trademarks of NEC Corporation.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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