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MOS INTEGRATED CIRCUIT
PD168103A
5-CHANNEL OPERATIONAL AMPLIFIER, IRIS DRIVER,
AND 4-CHANNEL H-BRIDGE DRIVER
DATA SHEET
Document No. S17655EJ1V0DS00 (1st edition)
Date Published June 2005 NS CP(K)
Printed in Japan
2005
DESCRIPTION
The
PD168103A is the motor driver IC with IRIS control circuit, operational amplifier and 4-ch H-bridge output.
Smooth operation is possible for IRIS control with linear method.
The package is 48-pin thin type QFN and then it helps reduce the mounting area and height.
The
PD168103A is suitable for the lens drive of a camcorder, DSC, etc.
FEATURES
5-ch H-bridge circuits employing power MOS FET
Low-voltage driving
LV
DD
= 2.7 to 3.6 V, AV
DD
= 4.5 to 5.5 V, V
M12
= V
M34
= V
SHUTTER
= V
IRIS
= 2.7 to 5.5 V
Output on-state resistance: 2.0 TYP., 3.0 MAX. (4-ch H-bridge block, sum of top and bottom stage, V
M
= 5 V)
PWM output (ch1 to ch4)
Output current
DC current:
0.3 A/ch (when each channel is used independently)
Peak current:
0.7 A/ch (when each channel is used independently)
3-ch general-purpose operational amplifier
Input offset voltage:
5 mV
Input voltage range: 0 to AV
DD
- 1.5 V
Output voltage range: 0.2 to AV
DD
- 0.2 V
1-ch current sink amplifier
Output current: 5 mA
1-ch 1/2V
DD
output amplifier
IRIS driver block supporting linear driving
Pre-driver amplifier of the IRIS driver block
Undervoltage lockout circuit
Output circuit and amplifier stop at LV
DD
= 1.7 V TYP. or less.
Overheat protection circuit
Operates at 150C or more and shuts down the output circuit.
Mounted on 48-pin plastic WQFN (7 x 7)
APPLICATIONS
Lens motor driving for DVC and DSC, etc.
ORDERING INFORMATION
Part Number
Package
Marking
Packing Type
PD168103AK9-5B4-A
Note
48-pin plastic WQFN (7 x 7)
168103A
Tray stuffing
Dry pack
Note Pb-free (This product does not contain Pb in external electrode and other parts.)
Data Sheet S17655EJ1V0DS
2
PD168103A
1. BLOCK DIAGRAM
OUT
1B
EN
12
OUT
1A
OUT
1
OUT
2A
OUT
2B
V
M12
PGND12
IN
1P
IN
1M
H-bridge Control
Amp. Control
TSD
UVLO
H-bridge
1
H-bridge
2
IN
1
IN
2
EN
34
IN
3
IN
4
GND
LV
DD
LV
DD
AV
DD
1/2AV
DD
AV
DD
OUT
3B
OUT
3A
OUT
4A
OUT
4B
V
M34
PGND34
H-bridge
3
H-bridge
4
LV
DD
RESETB
IR
IN1
OUT
4D
PGND5
Logic power
IN
REF
OUT
REF
Analog power
Amp.
ON/OFF
control
+
-
- +
AMP0
AMP1
OUT
2
IN
2P
IN
2M
AV
DD
+
-
AMP2
OUT
3
IN
3P
IN
3M
AV
DD
+
-
AMP3
OUT
4S
IN
4P
IN
4M
AV
DD
+
-
AMP4
AV
DD
GND
+
-
AMP5
IR
IN2
IN
IRP
IN
IRM
OUT
IRP
OUT
IRM
V
SUTTER
V
IRIS
IRIS Control
44
42
46
48
45
43
47
17
19
15
13
16
18
14
7
8
9
10
21
29
11
33
32
30
28
27
31
41
39
40
38
36
37
26
24
25
20
23
22
4
5
6
2
1
12
3
34
35
Cautions 1. P in pin name means plus, and M in pin name means minus.
2. A pull-down resistor (50 to 200 k
) is connected to the logic input pins (EN
12
, EN
34
, IN
1
, IN
2
, IN
3
,
and IN
4
). A pull-up resistor (50 to 200 k
) is connected to the IR
IN1
and IR
IN2
pins.
Data Sheet S17655EJ1V0DS
3
PD168103A
2. PIN FUNCTIONS
(1/2)
Pin No.
Pin Name
I/O
Function
1 LV
DD
-
Logic power supply voltage pin
2 GND
-
Logic and analog GND pin
3
RESETB
Input
Reset input pin
4 EN
12
Input
ch1 and ch2 output control input pin
5 IN
1
Input
ch1 input pin
6 IN
2
Input
ch2 input pin
7 EN
34
Input
ch3 and ch4 output control input pin
8 IN
3
Input
ch3 input pin
9 IN
4
Input
ch4 input pin
10 IR
IN1
Input
IRIS control logic input pin 1
11 IR
IN2
Input
IRIS control logic input pin 2
12 AV
DD
-
Analog power supply voltage pin
13 OUT
4B
Output
ch4 output pin B
14 PGND34
-
ch3 and ch4 GND pin
15 OUT
4A
Output
ch4 output pin A
16 VM
34
-
ch3 and ch4 power supply voltage pin
17 OUT
3B
Output
ch3 output pin B
18 PGND34
-
ch3 and ch4 GND pin
19 OUT
3A
Output
ch3 output pin A
20 OUT
4S
Output
Amplifier 4 (AMP4) source output pin (source)
21 OUT
4D
Output
Amplifier 4 (AMP4) drain output pin (sink)
22 IN
4M
Input
Amplifier 4 (AMP4) minus input pin
23 IN
4P
Input
Amplifier 4 (AMP4) plus input pin
24 IN
3P
Input
Amplifier 3 (AMP3) plus input pin
25 IN
3M
Input
Amplifier 3 (AMP3) minus input pin
26 OUT
3
Output
Amplifier 3 (AMP3) output pin
27 V
SHUTTER
-
Shutter (ON/OFF) power supply voltage pin
28 OUT
IRM
Output
IRIS minus output pin
29 PGND5
-
IRIS and shutter GND pin
30 OUT
IRP
Output
IRIS plus output pin
31 V
IRIS
-
IRIS (linear) power supply voltage pin
32 IN
IRM
Input
IRIS linear control (AMP5) minus input pin
33 IN
IRP
Input
IRIS linear control (AMP5) plus input pin
34 IN
REF
Input
1/2AV
DD
amplifier (AMP0) input pin (for capacitor connection)
Data Sheet S17655EJ1V0DS
4
PD168103A
(2/2)
Pin No.
Pin Name
I/O
Function
35 OUT
REF
Output
1/2AV
DD
amplifier (AMP0) output pin
36 IN
2P
Input
Amplifier 2 (AMP2) plus input pin
37 IN
2M
Input
Amplifier 2 (AMP2) minus input pin
38 OUT
2
Output
Amplifier 2 (AMP2) output pin
39 IN
1P
Input
Amplifier 1 (AMP1) plus input pin
40 IN
1M
Input
Amplifier 1 (AMP1) minus input pin
41 OUT
1
Output
Amplifier 1 (AMP1) output pin
42 OUT
1A
Output
ch1 output pin A
43 PGND12
-
ch1 and ch2 GND pin
44 OUT
1B
Output
ch1 output pin B
45 V
M12
-
ch1 and ch2 power supply voltage pin
46 OUT
2A
Output
ch2 output pin A
47 PGND12
-
ch1 and ch2 GND pin
48 OUT
2B
Output
ch2 output pin B
Data Sheet S17655EJ1V0DS
5
PD168103A
3. FUNCTION OPERATION TABLE
3.1 Reset Function
The internal circuit is shut off and the circuit current is kept to 1
A MAX. when the RESETB pin is made L (reset
status). In this status, the output pin goes into a Hi-Z (High impedance) state. Set the RESETB pin H for normal
usage.
Remark H: High level, L: Low level
3.2 Stepping Motor Driving Block
Table 3
-1. I/O Truth Table of the Stepping Motor Driving Block
EN
12
, EN
34
IN
1
, IN
2
, IN
3
, IN
4
OUT
1A
, OUT
2A
, OUT
3A
, OUT
4A
OUT
1B
, OUT
2B
, OUT
3B
, OUT
4B
H L
H
L
H
L
H
L L
Hi-Z
Hi-Z
H
Hi-Z
Hi-Z
Data Sheet S17655EJ1V0DS
6
PD168103A
3.3 IRIS Motor Driving Block
Table 3
-2. I/O Truth Table of the IRIS Driving Block
IR
IN1
IR
IN2
Operation Mode
Output State of H-bridge
OUT
IRP
OUT
IRM
Q1 Q2 Q3 Q4
L L
Normal
operation
ON OFF OFF ON Linear
Linear
(Amp.
control)
(Linear)
L
H Shutter OFF ON ON OFF L
H
H
L IRIS
open ON OFF OFF ON H
L
H H
Output
all
OFF
OFF OFF OFF OFF Hi-Z Hi-Z
Figure 3
-1. Description of the Operation Figure of the IRIS Motor Driving Block
IN
IRP
IN
IRM
+
-
Q4
V
IRIS
OUT
IRP
IN
IRP
IN
IRM
OUT
IRM
+
-
Normal
Shutter
OUT
IRP
OUT
IRM
V
SHUTTER
Open
All OFF
V
IRIS
OUT
IRP
OUT
IRM
V
IRIS
OUT
IRP
OUT
IRM
V
SHUTTER
Q4
V
IRIS
OUT
7A
OUT
7B
Q2
Q3
Q1
V
SHUTTER
Data Sheet S17655EJ1V0DS
7
PD168103A
4. FUNCTIONAL DEPLOYMENT
4.1 Undervoltage Lockout (UVLO) Circuit
This function is to forcibly stop the operation of the
PD168103A to prevent malfunctioning if LV
DD
drops.
When UVLO operates, the driver output and amplifier circuit are the OFF status.
The UVLO circuit detects a voltage drop if LV
DD
drops to 1.7 V TYP. in the non-reset status (RESETB = H). In the
reset status (RESETB = L), it detects a voltage drop if LV
DD
drops to 0.6 V TYP. This circuit may not operate if the
LV
DD
voltage abruptly drops for just a few
s.
4.2 Overheat Protection (TSD) Circuit
This function is to forcibly stop the operation of the driver output to protect it from destruction due to overheating if
the chip temperature of the
PD168103A rises.
The overheat protection circuit operates when the chip temperature rises to 150
C or more. When overheat is
detected, the driver output is stopped.
When RESETB = L (the reset status) or when UVLO is detected, the overheat protection circuit does not operate.
4.3 Power Up Sequence
The
PD168103A has a circuit that prevents current from flowing into the V
M
, V
SHUTTER
and V
IRIS
pins (from the next,
these are written as the motor power supply pins) when LV
DD
= 0 V or AV
DD
= 0 V. Therefore, the current that flows
into the motor power supply pins are cut off when LV
DD
= 0 V.
Because the LV
DD
pin voltage, the AV
DD
pin voltage and the motor power supply pins voltage are monitored, a
current of 1
A TYP. flows into each one of the motor power supply pins when LV
DD
is applied.
Data Sheet S17655EJ1V0DS
8
PD168103A
5. NOTE ON CORRECT USE
5.1 Pin Processing of Unused Circuit
The input/output pins of an unused circuit must be processed as specified below.
A pull-down or pull-up resistor is connected inside to the logic input pins. Connect the input pins to the GND or LV
DD
(IN
IR1
and IN
IR2
) potential when they are not used.
A pull-down resistor is not connected to the RESETB pin. Be sure to fix the RESETB pin to the LV
DD
or GND
potential when it is used.
5.2 OUT
4S
pin
Keep the voltage in the OUT
4S
pin to 2 V or less.
If an application circuit like the one shown below is used, the input voltage range of the amplifier is also 2 V or less.
IN
4P
IN
4M
+
-
OUT
4S
OUT
4D
5.3 OFFSET SHIFT OF AMP3
In case of large current with H-bridge 3, it cause to small offset shift in AMP3. Please take care to use AMP3, and
estimate actual set deeply.
Data Sheet S17655EJ1V0DS
9
PD168103A
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25
C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area
of 15%)
Parameter Symbol
Condition
Rating
Unit
Power supply voltage
LV
DD
Control
block
-0.5 to +6.0
V
AV
DD
Analog
block
-0.5 to +6.0
V
V
M12
, V
M34
Stepping
motor
block
-0.5 to +6.0
V
V
SHUTTER
, V
IRIS
IRIS
block
-0.5 to +6.0
V
Input voltage
Note1
V
IN
-0.5 to LV
DD
+ 0.5
V
Output pin voltage 1
V
OUT1
Motor
block
6.2
V
Output pin voltage 2
V
OUT2
Amplifier
block
-0.5 to AV
DD
+ 0.5
V
DC output current
I
D1(DC)
DC (stepping motor)
0.3 A/ch
I
D2(DC)
DC
(IRIS)
0.2 A/ch
Instantaneous output current
I
D(pulse)
PW < 10 ms, Duty Cycle
20%
0.7 A/ch
Power consumption
P
T
1.0
W
Peak junction temperature
Note2
T
ch(MAX)
150
C
Storage temperature
T
stg
-55 to +150
C
Notes 1. Keep V
IN
to less than 6 V.
2. The overheat protection circuit operates at T
ch
> 150
C. When overheat is detected, all the circuits are
stopped. The overheat protection circuit does not operate at reset or on detection of ULVO.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (T
A
= 25
C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper
foil area of 15%)
Parameter Symbol
Condition MIN.
TYP.
MAX.
Unit
Power supply voltage
LV
DD
Control
block
2.7 3.6 V
AV
DD
Analog
block
4.5 5.5 V
V
M12
, V
M34
Stepping
motor
block
2.7 5.5 V
V
SHUTTER
, V
IRIS
IRIS
block
2.7 5.5 V
Input voltage
V
IN
0
V
DD
V
DC output current
I
D1(DC)
DC (stepping motor, when 2 chs are
driven at same time)
-0.2
+0.2
A/ch
I
D2(DC)
DC (IRIS), maximum current when
the shutter operates
-0.1
+0.1
A/ch
Amplifier output current
I
OUT_AMP1
AMP1
to
AMP3
-5
+5
mA/ch
Amplifier output sink current
I
OUT_AMP2
AMP4
0
+5 mA
Logic input frequency
f
IN
100
kHz
Operating temperature range
T
A
-10
70
C
Caution Design each output current so that the junction temperature does not exceed 150C.
Data Sheet S17655EJ1V0DS
10
PD168103A
Electrical Characteristics (Unless otherwise specified, T
A
= 25
C, LV
DD
= 3.0 V, AV
DD
= 5.0 V, V
M
= V
SHUTTER
=
V
IRIS
= 5.0 V)
Overall and H-bridge block (stepping motor)
Parameter Symbol Condition
MIN.
TYP.
MAX.
Unit
LV
DD
pin current in standby mode
ILV
DD(STB)
RESETB = 0 V
1.0
A
AV
DD
pin current in standby mode
IAV
DD(STB)
RESETB = 0 V
1.0
A
V
M
pin current in standby mode
IV
M(STB)
RESETB = 0 V
1.0
A
LV
DD
pin current in during operation
I
DD(ACT)
RESETB = LV
DD
2.0
mA
High-level input current
I
IH
V
IN
= LV
DD
60
A
Low-level input current
I
IL
V
IN
= 0 V
-1.0
A
Input pull-down resistance
R
IND
50
200 k
High-level input voltage
V
IH
0.7
x
V
DD
V
Low-level input voltage
V
IL
0.3
x
V
DD
V
H-bridge on-state resistance
R
on
I
M
= 0.2 A, sum of upper and lower
stages
2.0
3.0
Output leakage current
Note 1
I
M(off)
Per V
M
pin, All control pins: low level
1.0
A
Low-voltage detection voltage
Note 2
V
DDS1
RESETB = H
1.7
2.5
V
Output turn-on time
t
on
R
L
= 20
0.5
1.0
s
Output turn-off time
t
off
0.1 0.4
s
Output rise time
t
r
0.05
0.2
0.4
s
Output fall time
t
f
50
100
ns
Notes 1.
PD168103A has a circuit that prevents current from flowing into the V
M
pin when LV
DD
= 0 V.
2. Unlike normal operations, after a reset the detection voltage becomes 0.6 V TYP.
Figure 6
-1. Switching Characteristic Waveform of the Stepping Motor Driving Block
100%
0%
0%
10%
10%
-10%
-10%
50%
50%
-50%
-50%
50%
90%
90%
-90%
-90%
50%
100%
100%
-100%
t
on
t
f
t
r
t
f
t
r
t
off
t
off
t
on
V
IN
I
DR
Data Sheet S17655EJ1V0DS
11
PD168103A
H-bridge block (IRIS motor)
Parameter Symbol
Condition
MIN.
TYP.
MAX.
Unit
V
IRIS
pin current in standby mode
IV
IRIS(STB)
RESETB = 0 V
1.0
A
V
SHUTTER
pin current in standby mode
IV
SHUTTER(STB)
RESETB = 0 V
1.0
A
High-level input current
I
IH
V
IN
= LV
DD
1.0
A
Low-level input current
I
IL
V
IN
= 0 V
-60
A
Input pull-up resistance
R
IND
50
200
k
High-level input voltage
V
IH
0.7
x
V
DD
V
Low-level input voltage
V
IL
0.3
x
V
DD
V
H-bridge on-state resistance
R
on1
R
L
= 50
, sum of upper and
lower stages
2.5
3.5
Output turn-on time
t
onH1
When linear driving, R
L
= 50
0.01 25 35
s
t
onH2
When full ON, R
L
= 50
0.01 1.0 2.0
s
Output turn-off time
t
offH
0.01
1.0
2.0
s
Output rise time
t
rH
60
ns
Output fall time
t
fH
80
ns
Control amplifier offset voltage
V
IO
AMP5
5
7.5
mV
Figure 6
-2. Switching Characteristic Waveform of the IRIS Motor Driving Block
100%
0%
0%
-10%
-10%
50%
50%
-50%
-50%
50%
-90%
-90%
50%
100%
100%
-100%
t
on
t
r
t
f
t
off
t
off
t
on
IR
IN2
I
IRIS
at IR
IN1
= L
Linear operation
Shutter
Linear operation
Data Sheet S17655EJ1V0DS
12
PD168103A
Operational amplifier block
Parameter Symbol Condition
MIN.
TYP.
MAX.
Unit
AV
DD
pin current in during operation
IA
DD
Output
open
3.0 mA
Input offset voltage 1
V
IO1
AMP1
to
AMP3,
AMP5
3
5 mV
Input offset voltage 2
V
IO2
AMP4
5
7 mV
Common mode input voltage range 1
V
ICM1
AMP1
to
AMP3,
AMP5
0
AV
DD
- 1.5
V
Common mode input voltage range 2
V
ICM2
AMP4
0
AV
DD
- 2.0
V
High-level output voltage
V
OH
AMP1 to AMP3, when I
OUT
= +2 mA
AV
DD
- 0.2
V
Low-level output voltage
V
OL
AMP1 to AMP3, when I
OUT
=
-2 mA
0.2
V
Large amplitude voltage gain
A
V
AMP1
to
AMP3,
DC
80
dB
Slew-rate SR
AMP1 to AMP3, A
V
= 1 dB ,R
L
10 k
0.5
V/
s
1/2 AV
DD
output voltage accuracy
V
O
AMP0, I
OUT
= 100
A
2.4 2.5 2.6
V
Data Sheet S17655EJ1V0DS
13
PD168103A
7.
TYPICAL CHARACTERISTICS (Unless otherwise specified, T
A
= 25
C, LV
DD
= 3.0 V, AV
DD
= V
M
=
V
SHUTTER
= V
IRIS
= 5.0 V)
P
T
vs. T
A
CHARACTERISTIC
R
on
vs. T
A
CHARACTERISTIC (H-bridge 1 to 4)
P
T
- Total Powe
r
Dissipation - W
0
20 30 40
10
50 60 70 80 90 100
1.2
1
0.8
0.6
0.4
0.2
0
125C/W
T
A
- Ambient Temperature -
R
on
-
H-b
r
idge On-stat
e
Re
sistan
ce -
1
1.5
2
2.5
-40
-20
0
20
40
60
80
100
OUT
4B
OUT
4A
OUT
1A
OUT
1B
OUT
4A
OUT
4B
OUT
1B
OUT
1A
T
A
- Ambient Temperature -
R
on
vs. T
A
CHARACTERISTIC (H-bridge IRIS)
I
IH
, I
IL
vs. LV
DD
CHARACTERISTIC
R
on
-
H-b
r
idge On-stat
e
Re
sistan
ce -
1
1.5
2
2.5
-40
-20
0
20
40
60
80
100
OUT
IR+
OUT
IR
-
OUT
IR
-
OUT
IR+
T
A
- Ambient Temperature -
I
IH
, I
IL
- Input Pin
Curren
t
-
A
0
10
20
30
40
50
60
70
0
1
2
3
4
5
6
7
I
IH
I
IL
LV
DD
- Power Supply Voltage of Control Block - V
V
IH
, V
IL
vs. LV
DD
CHARACTERISTIC
UNDERVOLTAGE LOCKOUT CIRCUIT
CHARACTERISTIC
V
IH
, V
IL
- I
nput Vo
ltage - V
0
1
2
3
4
5
0
1
2
3
4
5
6
7
V
IH
V
IL
LV
DD
- Power Supply Voltage of Control Block - V
V
DDS
-
Undervolt
age Dete
ction Vo
ltage - V
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
6
7
LV
DD(H
L)
LV
DD(L
H)
V
M
- Power Supply Voltage of Motor Block - V
Data Sheet S17655EJ1V0DS
14
PD168103A
R
on
vs. V
M
CHARACTERISTIC
R
on
vs. V
IRIS
, V
SHUTTER
CHARACTERISTIC
R
on
-
H-b
r
idge On-stat
e
Re
sistan
ce -
0
0.5
1
1.5
2
2.5
3
3.5
0
1
2
3
4
5
6
7
I
M
= 200 mA
V
M
- Power Supply Voltage of Motor Block - V
0
0.5
1
1.5
2
2.5
3
3.5
4
0
1
2
3
4
5
6
7
IRIS
Shutter
I
M
= 100 mA
V
IRIS
, V
SHUTTER
- Power Supply Voltage of IRIS Block - V
R
on
-
H-b
r
idge On-stat
e
Re
sistan
ce of IR
IS Block
-
T
ONH
, T
OFFH
vs. V
M
CHARACTERISTIC
T
r
, T
f
vs. V
IRIS
, V
SHUTTER
CHARACTERISTIC
(when full ON)
T
ONH
-
H
-
bridge Output Circuit Tu
rn-on Time
-
s
T
OFFH
- H-bridge
Output
Ci
rcuit Tu
rn-off Time
-
s
0
0.2
0.4
0.6
0.8
1
1.2
0
1
2
3
4
5
6
7
T
OFFH
T
ONH
R
L
= 20
V
M
- Power Supply Voltage of Motor Block - V
T
r
- IRIS H
-
bridg
e
Output
Circuit Rise Time -
s
T
f
- IR
IS H-b
r
idg
e
Output
Circuit Fall Time -
s
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0
1
2
3
4
5
6
7
R
L
= 50
T
f
T
r
V
IRIS
, V
SHUTTER
- Power Supply Voltage of IRIS Block - V
T
r
, T
f
vs. V
M
CHARACTERISTIC
T
ONH1
, T
OFFH
vs. V
IRIS
, V
SHUTTER
CHARACTERISTIC
(when Linear)
T
r
- H-bridge
Out
put Circuit Ri
se T
i
me -
s
T
f
- H
-
bridge
Out
put Circuit
Fall Time -
s
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
3
4
5
6
7
T
f
T
r
R
L
= 20
V
M
- Power Supply Voltage of Motor Block - V
T
ONH1
-
IRIS H
-
bri
dge Out
put Circu
i
t Turn-on
Time -
s
T
OFFH
- IRIS H
-
bri
dge Out
put Circu
i
t Turn-off
Time -
s
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
T
OFFH
T
ONH1
R
L
= 50
V
IRIS
, V
SHUTTER
- Power Supply Voltage of IRIS Block - V
Data Sheet S17655EJ1V0DS
15
PD168103A
T
r
, T
f
vs. V
IRIS
, V
SHUTTER
CHARACTERISTIC
(when Linear)
T
ONH1
, T
OFFH
vs. V
IRIS
, V
SHUTTER
CHARACTERISTIC
(when full ON)
T
r
- IRIS H
-
bridg
e
Output
Circuit Rise Time -
s
T
f
- IR
IS H-b
r
idg
e
Output
Circuit Fall Time -
s
0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
7
T
r
T
f
R
L
= 50
V
IRIS
, V
SHUTTER
- Power Supply Voltage of IRIS Block - V
T
ONH1
-
IRIS H
-
bri
dge Out
put Circu
i
t Turn-on
Time -
s
T
OFFH
- IRIS H
-
bri
dge Out
put Circu
i
t Turn-off
Time -
s
0
0.2
0.4
0.6
0.8
1
1.2
0
1
2
3
4
5
6
7
R
L
= 50
T
OFFH
T
ONH1
V
IRIS
, V
SHUTTER
- Power Supply Voltage of IRIS Block - V
I
M
vs. V
M
CHARACTERISTIC
ILV
DD
vs. LV
DD
CHARACTERISTIC
I
M
- V
M
Pin C
u
rre
nt when
OF
F -
A
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
RESETB: H
EN, IN: L
V
M
- Power Supply Voltage of Motor Block - V
ILV
DD
- LV
DD
Pi
n
Curren
t
-
A
0
100
200
300
400
500
600
700
0
1
2
3
4
5
6
7
RESETB: H
EN, IN: L
LV
DD
- Power Supply Voltage of Control Block - V
Data Sheet S17655EJ1V0DS
16
PD168103A
8. STANDARD CONNECTION EXAMPLE
H-bridge Control
Amp. Control
TSD
UVLO
H-bridge
1
H-bridge
2
Motor 1
Motor 2
CPU
CPU
H-REF
DR+
DR
-
LV
DD
AV
DD
1/2LV
DD
OUT
1B
OUT
1A
OUT
2A
OUT
2B
V
M12
PGND12
OUT
3B
OUT
3A
OUT
4A
OUT
4B
V
M34
PGND34
H-bridge
3
H-bridge
4
LV
DD
Logic power
Analog power
Amp.
ON/OFF
control
+
-
- +
AMP0
AMP1
AV
DD
+
-
AMP2
AV
DD
+
-
AMP3
AV
DD
+
-
AMP4
AV
DD
GND
+
-
AMP5
IRIS Control
CDS Reset
EN
34
IN
3
IN
4
IR
IN1
IR
IN2
OUT
4D
PGND5
IN
IRP
IN
IRM
OUT
IRP
OUT
IRM
V
SUTTER
V
IRIS
OUT
1
IN
1P
IN
1M
OUT
2
IN
2P
IN
2M
OUT
3
IN
3P
IN
3M
OUT
4S
IN
4P
IN
4M
RESETB
OUT
REF
IRIS-CTL
DC/DC
Converter
V
M
= 2.7 to 5.5 V
LV
DD
= 2.7 to 3.6 V
AV
DD
= 4.5 to 5.5 V
1 to 10 F
Battey
EN
34
IN
3
IN
4
IR
IN1
IR
IN2
IRIS-CTL
H-REF
H-GAIN
HALL-AD
EN
12
IN
1
IN
2
GND
LV
DD
AV
DD
IN
REF
Position Detection Circuit
AV
DD
+
-
H
Data Sheet S17655EJ1V0DS
17
PD168103A
9. PACKAGE DRAWING
P
0.08MIN.
0.08MIN.
Lp
S
S
B
A
B
y1
S
S
f
x4
A
S
y
B
S
t
x4
c2
A
c
A2
A1
c1
b1
b
A
e
P
D
D
/2
/2
4
-C0.5
36
25
1
12
37
24
48
13
HD
HD
ZE
ZD
E
E
/2
/2
HE
HE
D
E
f
HD
HE
t
A
A1
A2
b
b1
c
c1
c2
e
Lp
x
y
y1
ZD
ZE
0.64
0.23
0.05
0.50
0.05
0.08
0.10
0.625
0.625
0.20
0.03
0.14
0.16
ITEM
DIMENSIONS
0.17
0.40
0.10
0.14
0.20
6.75
6.75
0.20
7.00
7.00
0.20
0.67
0.03
P48K9-50-5B4-1
48-PIN PLASTIC WQFN (7x7)
part
terminal section
detail of
S
x
b
M
B
A
+0.08
-0.04
+0.02
-0.025
(UNIT:mm)
NOTES
1 "t" AND "f" EXCLUDES MOLD FLASH
2 ALTHOUGH THERE ARE 4 TERMINALS IN THE CORNER PART
OF A PACKAGE, THESE TERMINALS ARE NOT DESIGNED FOR
INTERCONNECTION, BUT FOR MANUFACTURING PROCESS OF
THE PACKAGE, THEREFOR DO NOT INTEND TO SOLDER THESE
4 TERMINALS, SOLDERABLITY OF THE 4 TERMINALS ARE NOT
GUARANTEED.
Data Sheet S17655EJ1V0DS
18
PD168103A
10. RECOMMENDED SOLDERING CONDITIONS
The
PD168103A should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
PD168103AK9-5B4-A
Note1
: 48-pin plastic WQFN (7 x 7)
Process Conditions
Symbol
Infrared reflow
Package peak temperature: 260
C, Time: 60 seconds MAX. (at 220C or higher) ,
Count: Three times or less, Exposure limit: 3 days
Note2
(after that, prebake at 125
C
for 10 hours) , Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended.
<Precaution>
Products other than in heat-resistant trays (such as those packaged in a magazine,
taping, or non-thermal-resistant tray) cannot be baked in their package.
IR60-103-3
Notes 1. Pb-free (This product does not contain Pb in external electrode and other parts.)
2. After opening the dry pack, store it a 25
C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet S17655EJ1V0DS
19
PD168103A
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
PD168103A
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
The information in this document is current as of June, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics
does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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