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1998
MOS INTEGRATED CIRCUIT
PD16647
402/384-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)
DATA SHEET
The mark
shows major revised points.
Document No. S13607EJ2V0DS00 (2nd edition)
Date Published August 1999 NS CP (K)
Printed in Japan
DESCRIPTION
The
PD16647 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the
driver circuit operates at 5.0 V. The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed
in 64-value outputs
-corrected by the internal D/A converter and 10 external power supplies. The clock frequency is
50 MHz MIN.
PD16647 can be used in TFT-LCD panels conforming to the SVGA standards.
FEATURES
CMOS level input
402/384 outputs
6 bits (gray scale data) x 3 dots input
64-value output by 10 external power supplies and internal D/A converter
Output dynamic range : V
SS2
+ 0.1 V to V
DD2
-
0.1 V
High-speed data transfer: f
MAX
=50 MHz MIN.(internal data transfer rate at supply voltage V
DD1
of logic circuit =3.0 V)
Level of
-corrected power supply can be inverted
Input data inversion function (INV)
Precharge-less output buffer
Logic supply voltage (V
DD1
) : 3.3 V
0.3 V
Driver supply voltage (V
DD2
) : 5.0 V
0.5 V
Slim TCP
ORDERING INFORMATION
Part Number
Package
PD16647N-xxx
TCP (TAB package)
Remark
The TCP package is a custom-ordered item. Users are requested to consult with an NEC sales
representative.
Data Sheet S13607EJ2V0DS00
4
PD16647
3. PIN DESCRIPTION
Pin Symbol
Pin Name
Description
S
1
to S
402/384
Driver output
Output 64 gray-scale analog voltages converted from digital signals.
Osel = H or open: 402 outputs (S
1
to S
402/384
)
Osel = L : 384 outputs (S
1
to S
192
, S
211/193
to S
402/384
)
S
193
to S
210
outputs are invalid in 384 outputs.
D
00
to D
05
Display data input
Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB).
D
10
to D
15
D
X0
: LSB, D
X5
: MSB
D
20
to D
25
R,/L
Shift direction select input
This pin inputs/outputs start pulses in cascade mode.
Shift direction of shift register is as follows:
R,/L = H : STHR input, S
1
S
402
, STHL output
R,/L = L : STHL input, S
402
S
1
, STHR output
STHR
Right shift start pulse I/O
R,/L = H : Inputs start pulse
R,/L = L : Outputs start pulse
STHL
Left shift start pulse I/O
R/L = H : Outputs start pulse
R/L = L : Inputs start pulse
Bcont
Bias control
This pin can be used to finely control the bias current inside the output
amplifier. In cases when fine-control is necessary, connect this pin to V
DD2
using a resistor of 10 to 100k
(per IC). When this fine-control function is
not required, short-circuit this pin to V
DD2
. Refer to 7. Bias Current Control
Function/Bcont.
CLK
Shift clock input
Inputs shift clock to shift register. Display data is loaded to data register at
rising edge of this pin. Start pulse output goes high at rising edge of 134th
clock after start pulse has been input, and serves as start pulse to driver in
next stage. 134th clock of driver in first stage serves as start pulse of driver
in next stage.
STB
Latch input
Contents of data register are latched at rising edge, transferred to D/A
converter, and output as analog voltage corresponding to display data.
Contents of internal shift register are cleared after STB has been input. One
pulse of this signal is input when
PD16647 is started, and then device
operates normally.
For STB input timing, refer to 9. Switching Characteristics Waveform.
Osel
Selection of number of outputs
Selects number of outputs. This pin is internally pulled up to V
DD1
.
Osel = H or open : 402 outputs (S
1
to S
402/384
)
Osel = L : 384 outputs (S
1
to S
192
, S
211/193
to S
402/384
)
V
0
to V
9
-corrected power supply
Inputs
-corrected power from external source.
V
SS2
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
V
DD2
or
V
SS2
V
0
V
1
V
2
V
3
V
4
V
5
V
6
V
7
V
8
V
9
V
DD2
Maintain gray scale power supply during gray scale voltage output.
INV
Data inversion input
Input data can be inverted when display data is loaded.
INV = H : Inverts and loads input data.
INV = L : Does not invert input data.
V
DD1
Logic circuit power supply
3.3 V
0.3 V
V
DD2
Driver circuit power supply
5.0 V
0.5 V
V
SS1
Logic ground
Ground
V
SS2
Driver ground
Ground
Caution
Be sure to turn on power in the order V
DD1
, logic input, V
DD2
, and gray scale power (V
0
to V
9
), and
turn off power in the reverse order, to prevent the
PD16647 from being damaged by latchup. Be
sure to observe this power sequence even during a transition period.
Data Sheet S13607EJ2V0DS00
5
PD16647
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 10 major points on the
-characteristic curve of the LCD panel are arbitrarily set by external power supplies V
0
through V
9
. If the display data is 00H or 3FH, gray scale voltage V
0
or V
9
is output. If the display data is in the range
01H to 3EH, the high-order 3 bits select an external power pair V
n+1
, V
n
. The low-order 3 bits evenly divide the range
of V
n+1
to V
n
into eight segments by means of D/A conversion (however, the ranges from V
8
to V
7
and from V
1
to V
0
are divided into seven segments) to output a 64 gray scale voltage.
D
X5
(MSB)
D
X4
D
X3
D
X2
D
X1
D
X0
(LSB)
D
X5
D
X4
D
X3
V
n+1
-V
n
0
0
0
V
1
-V
2
0
0
1
V
2
-V
3
0
1
0
V
3
-V
4
0
1
1
V
4
-V
5
1
0
0
V
5
-V
6
1
0
1
V
6
-V
7
1
1
0
V
7
-V
8
1
1
1
V
8
-V
9
V
n
V
n+1
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
V
0
V
DD2
V
1
V
2
V
3
V
4
V
5
V
6
V
7
V
8
0
7
F
17
1F
Input data (HEX)
27
2F
37
3F
V
9
V
SS2
gray scale supply specified
by 00H
7 segments
8 segments
8 segments
8 segments
8 segments
8 segments
8 segments
7 segments
gray scale supply specified
by 3FH
High-order 3 bits
:
-corrected power selected
(V
n
, V
n+1
)
Low-order 3 bits
: 3-bit D/A (range V
n
to V
n+1
is divided to 7 or 8 segments)
Figure4-1. Relationship between Input Data and
-corrected Voltage
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