Document Outline

COVER
DESCRIPTION
FEATURES
ORDERING INFORMATION
1. BLOCK DIAGRAM
2. SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT
3. PIN CONFIGURATION
4. PIN FUNCTIONS
5. FUNCTIONAL DISCRIPTION
- 5.1 Multiplexer Circuit
  - 5.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L)
  - 5.1.2 Single-side delta array mode (MP/TH = L, MP/1.5 = H)
  - 5.1.3 Double-side delta array mode (MP/TH = H, MP/1.5 = H)
  - 5.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L)
  - 5.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn
- 5.2 Sample and Hold Circuit
- 5.3 Write Operation Timing
6. ELECTRICAL SPECIFICATIONS

Document No. S15677EJ1V0DS00 (1st edition)
Date Published May 2002 NS CP(K)
Printed in Japan

SOURCE DRIVER FOR 240-OUTPUT TFT-LCD

(NAVIGATION, AUTOMOBILE LCD-TV)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD16449

The mark

shows major revised points.

2001

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

DESCRIPTION

PD16449 is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a

variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that
sample analog voltages. Because the two sample and hold circuits alternately execute sampling and holding, a
high definition can be obtained.

In addition, simultaneous sampling and successive sampling are automatically selected according to the pixel

array of the LCD panel. It is ideal for a wide range of applications, including navigation systems and automobile
LCD-TVs.

FEATURES

Can be driven on 5 V (Dynamic range: 4.3 V, V

DD2

= 5.0 V)

240-output

CLK

= 15 MHz MAX. (V

DD1

= 3.0 V)

Simultaneous/successive sampling selectable according to pixel array

Simultaneous sampling: Vertical stripe

Successive sampling: Delta array, mosaic array

Two sample and hold circuits

Low output deviation between pins (

20 mV MAX.)

Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit

Left and right shift selected by R,/L pin

TCP/COG mounting possible

Remark /xxx indicates active low signal.

ORDERING INFORMATION

Part Number

Package

PD16449N-xxx

TCP

PD16449P

Chip

Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or

product quality, so please contact one of our sales representative.

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

3. PIN CONFIGURATION

240

239

SS1

CLI3

TEST

STHR

RESET

INH

CLI1

CLI2

STHL

MP/TH

MP/1.5

R,/L

DD2

SS1

DD1

Y(+)

X(+)

SS2

Dummy

SS2

C1
C1

C2
C2

DD2

DD1

STHL

MP/TH
MP/TH

MP/1.5
MP/1.5

R,/L
R,/L

SS1

Dummy

RESET
RESET

INH
INH

CLI1
CLI1

CLI2

CLI3

TEST

STHR

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Table 3

-
-
-
-

1. Pad Layout (1/3)

No.

PAD Name

X [

Y [

No.

PAD Name

X [

Y [

-400

8033

VSS2

-400

-7807

-400

7745

VSS2

-400

-8095

-400

7457

DUMMY39

-277

-8403

-400

7169

DUMMY40

-175

-8403

-400

6881

DUMMY41

-107

-8403

-400

6593

DUMMY42

-39

-8403

-400

6305

DUMMY43

-8403

-400

6017

DUMMY44

131

-8403

-400

5729

DUMMY45

327

-8259

VDD2

-400

5441

327

-8157

VDD2

-400

5153

327

-8089

VDD2

-400

4865

327

-8021

VDD1

-400

4577

327

-7953

VDD1

-400

4289

327

-7885

VDD1

-400

4001

327

-7817

STHL

-400

3713

327

-7749

STHL

-400

3425

327

-7681

STHL

-400

3137

327

-7613

MP/TH

-400

2849

H10

327

-7545

MP/TH

-400

2561

H11

327

-7477

MP/TH

-400

2273

H12

327

-7409

MP/1.5

-400

1985

H13

327

-7341

MP/1.5

-400

1697

H14

327

-7273

MP/1.5

-400

1409

H15

327

-7205

R,/L

-400

1121

H16

327

-7137

R,/L

-400

833

H17

327

-7069

R,/L

-400

545

H18

327

-7001

RESET

-400

257

H19

327

-6933

RESET

-400

-31

H20

327

-6865

RESET

-400

-319

H21

327

-6797

INH

-400

-607

H22

327

-6729

INH

-400

-895

H23

327

-6661

INH

-400

-1183

H24

327

-6593

CLI1

-400

-1471

H25

327

-6525

CLI1

-400

-1759

H26

327

-6457

CLI1

-400

-2047

H27

327

-6389

CLI2

-400

-2335

H28

327

-6321

CLI2

-400

-2623

H29

327

-6253

CLI2

-400

-2911

H30

327

-6185

CLI3

-400

-3199

H31

327

-6117

CLI3

-400

-3487

H32

327

-6049

CLI3

-400

-3775

H33

327

-5981

TEST

-400

-4063

H34

327

-5913

TEST

-400

-4351

H35

327

-5845

TEST

-400

-4639

100

H36

327

-5777

STHR

-400

-4927

101

H37

327

-5709

STHR

-400

-5215

102

H38

327

-5641

DUMMY32

-400

-5503

103

H39

327

-5573

VSS1

-400

-5791

104

H40

327

-5505

VSS1

-400

-6079

105

H41

327

-5437

VSS1

-400

-6367

106

H42

327

-5369

VSS2

-400

-6655

107

H43

327

-5301

VSS2

-400

-6943

108

H44

327

-5233

VSS2

-400

-7231

109

H45

327

-5165

VSS2

-400

-7519

110

H46

327

-5097

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Table 3

-
-
-
-

1. Pad Layout (2/3)

No.

PAD Name

X [

Y [

No.

PAD Name

X [

Y [

111

H47

327

-5029

166

H102

327

-1289

112

H48

327

-4961

167

H103

327

-1221

113

H49

327

-4893

168

H104

327

-1153

114

H50

327

-4825

169

H105

327

-1085

115

H51

327

-4757

170

H106

327

-1017

116

H52

327

-4689

171

H107

327

-949

117

H53

327

-4621

172

H108

327

-881

118

H54

327

-4553

173

H109

327

-813

119

H55

327

-4485

174

H110

327

-745

120

H56

327

-4417

175

H111

327

-677

121

H57

327

-4349

176

H112

327

-609

122

H58

327

-4281

177

H113

327

-541

123

H59

327

-4213

178

H114

327

-473

124

H60

327

-4145

179

H115

327

-405

125

H61

327

-4077

180

H116

327

-337

126

H62

327

-4009

181

H117

327

-269

127

H63

327

-3941

182

H118

327

-201

128

H64

327

-3873

183

H119

327

-133

129

H65

327

-3805

184

H120

327

-65

130

H66

327

-3737

185

H121

327

131

H67

327

-3669

186

H122

327

132

H68

327

-3601

187

H123

327

139

133

H69

327

-3533

188

H124

327

207

134

H70

327

-3465

189

H125

327

275

135

H71

327

-3397

190

H126

327

343

136

H72

327

-3329

191

H127

327

411

137

H73

327

-3261

192

H128

327

479

138

H74

327

-3193

193

H129

327

547

139

H75

327

-3125

194

H130

327

615

140

H76

327

-3057

195

H131

327

683

141

H77

327

-2989

196

H132

327

751

142

H78

327

-2921

197

H133

327

819

143

H79

327

-2853

198

H134

327

887

144

H80

327

-2785

199

H135

327

955

145

H81

327

-2717

200

H136

327

1023

146

H82

327

-2649

201

H137

327

1091

147

H83

327

-2581

202

H138

327

1159

148

H84

327

-2513

203

H139

327

1227

149

H85

327

-2445

204

H140

327

1295

150

H86

327

-2377

205

H141

327

1363

151

H87

327

-2309

206

H142

327

1431

152

H88

327

-2241

207

H143

327

1499

153

H89

327

-2173

208

H144

327

1567

154

H90

327

-2105

209

H145

327

1635

155

H91

327

-2037

210

H146

327

1703

156

H92

327

-1969

211

H147

327

1771

157

H93

327

-1901

212

H148

327

1839

158

H94

327

-1833

213

H149

327

1907

159

H95

327

-1765

214

H150

327

1975

160

H96

327

-1697

215

H151

327

2043

161

H97

327

-1629

216

H152

327

2111

162

H98

327

-1561

217

H153

327

2179

163

H99

327

-1493

218

H154

327

2247

164

H100

327

-1425

219

H155

327

2315

165

H101

327

-1357

220

H156

327

2383

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Table 3

-
-
-
-

1. Pad Layout (3/3)

No.

PAD Name

X [

Y [

No.

PAD Name

X [

Y [

221

H157

327

2451

276

H212

327

6191

222

H158

327

2519

277

H213

327

6259

223

H159

327

2587

278

H214

327

6327

224

H160

327

2655

279

H215

327

6395

225

H161

327

2723

280

H216

327

6463

226

H162

327

2791

281

H217

327

6531

227

H163

327

2859

282

H218

327

6599

228

H164

327

2927

283

H219

327

6667

229

H165

327

2995

284

H220

327

6735

230

H166

327

3063

285

H221

327

6803

231

H167

327

3131

286

H222

327

6871

232

H168

327

3199

287

H223

327

6939

233

H169

327

3267

288

H224

327

7007

234

H170

327

3335

289

H225

327

7075

235

H171

327

3403

290

H226

327

7143

236

H172

327

3471

291

H227

327

7211

237

H173

327

3539

292

H228

327

7279

238

H174

327

3607

293

H229

327

7347

239

H175

327

3675

294

H230

327

7415

240

H176

327

3743

295

H231

327

7483

241

H177

327

3811

296

H232

327

7551

242

H178

327

3879

297

H233

327

7619

243

H179

327

3947

298

H234

327

7687

244

H180

327

4015

299

H235

327

7755

245

H181

327

4083

300

H236

327

7823

246

H182

327

4151

301

H237

327

7891

247

H183

327

4219

302

H238

327

7959

248

H184

327

4287

303

H239

327

8027

249

H185

327

4355

304

H240

327

8095

250

H186

327

4423

305

DUMMY46

327

8197

251

H187

327

4491

306

DUMMY47

131

8405

252

H188

327

4559

307

DUMMY48

8405

253

H189

327

4627

308

DUMMY49

-39

8405

254

H190

327

4695

309

DUMMY50

-107

8405

255

H191

327

4763

310

DUMMY51

-175

8405

256

H192

327

4831

311

DUMMY52

-277

8405

257

H193

327

4899

258

H194

327

4967

259

H195

327

5035

260

H196

327

5103

261

H197

327

5171

262

H198

327

5239

263

H199

327

5307

264

H200

327

5375

265

H201

327

5443

266

H202

327

5511

267

H203

327

5579

268

H204

327

5647

269

H205

327

5715

270

H206

327

5783

271

H207

327

5851

272

H208

327

5919

273

H209

327

5987

274

H210

327

6055

275

H211

327

6123

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

4. PIN FUNCTIONS

Symbol

Pin Name

Pad No.

I/O

Description

C1 to C3

Video signal input

1 to 3, 4 to 6,
7 to 9

Input

Input R, G, and B video signals.

to H

300

Video signal output

65 to 304

Output

Video signal output pins. Output sampled and held video signals during
horizontal period.

STHR,
STHL

Cascade I/O

46, 47
16 to 18

I/O

Start pulse I/O pins of sample hold timing. STHR serves as an input
pin and STHL, as an output pin, in the case of right shift. In the case of
left shift, STHL serves as an input pin, and STHR, as an output pin.

CLI1 to
CLI3

Shift clock input

34 to 38,
37 to 39,
40 to 42

Input

A start pulse is read at the rising edge of CLI1. Sampling pulse SHPn
is generated at the rising edge of CLI1 through CLI3 during successive
sampling, and at the rising edge of CLI1 during simultaneous sampling
(for details, refer to the Timing charts in 5. FUNCTIONAL
DESCRIPTION).

INH

Inhibit input

31 to 33

Input

Selects a multiplexer and one of the two sample and hold circuits at the
falling edge.

RESET

Reset input

28 to 30

Input

Resets the select counter of the multiplexer and the selector circuit of
the two sample and hold circuits when it goes high. After reset, the
multiplexer is turned OFF, so sure to input one pulse of the INH signal
before inputting the video signal. If the video signal is input without the
INH signal, sampling is not executed.
Four types of color filter arrays can be supported by combination of
MP/TH and MP/1.5.

Mode

MP/TH

MP/1.5

MP/TH

Multiplexer circuit
select input (1)

19 to 21

Input

Vertical stripe array

Single-side delta array

Mosaic array

Double-side delta array

MP/1.5

Multiplexer circuit
select input (2)

22 to 24

Input

R,/L

Shift direction
select input

25 to 27

Input

R,/L = H: Right shift: STHR

240

STHL

R,/L = L: Left shift: STHL

240

STHR

DD1

Logic power supply

13 to 15

3.0 to 5.5 V

DD2

Driver power
supply

10 to 12

5.0 V

0.5 V

SS1

Logic ground

49 to 51

Connect this pin to ground of system.

SS2

Driver ground

52 to 57

Connect this pin to ground of system.

TEST

Test

43 to 45

Fix this pin to low level.

Dummy

48, 58 to 64,
305 to 311

No dummy pins are connected with other pins inside IC.

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

5. FUNCTIONAL DISCRIPTION

5.1 Multiplexer Circuit

This circuit selects RGB video signals input to the C1 to C3 pins according to the pixel array of the liquid crystal
panel, and outputs the signals to the H

through H

240

pins.

Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and
MP/1.5 pins.

5.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L)
In this mode, the relation between video signals C1 to C3, and output pins is as shown below. This mode is used to
drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status.

Table 5

-
-
-
-

1. Relation between Video Signals C1 to C3, and Output Pins (during right shift)

Line No.

(number of INHn)

RESET

INH

240

)

239

)

238

)

237

)

...

239

)

240

)

Sampling

C1 (C3)

Sampling

C2 (C2)

Sampling

C3 (C1)

Sampling

C1 (C3)

... Sampling

C2 (C2)

Sampling

C3 (C1)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

...

Remark ( ) indicates the case of left shift.

Figure 5

-
-
-
-

1. Pixel Arrangement of Vertical Stripe Array and Multiplexer Operation

C2
C3

PD16449

Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "L"

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Figure 5

-
-
-
-

2. Timing Chart of Vertical Stripe Array

undifined

C1 (C3)

RESET

INH

240

)

Sampling
input data

Output

239

)

Sampling
input data

238

)

Sampling
inputdata

239

)

Sampling
input data

240

)

Sampling
input data

Output

C1 (C3)

C2 (C2)

C3 (C1)

C2 (C2)

C3 (C1)

undifined

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

5.1.2 Single-side delta array mode (MP/TH = L, MP/1.5 = H)

Table 5

-
-
-
-

2. Relation between Video Signals C1 to C3, and Output Pins

Line No.

(number of INHn)

RESET

INH

240

)

239

)

238

)

237

)

...

239

)

240

)

Undefined

...

Undefined

Sampling

C1 (C3)

Sampling

C2 (C2)

Sampling

C3 (C1)

Sampling

C1 (C3)

... Sampling

C2 (C2)

Sampling

C3 (C1)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

Output

C2 (C1)

Output

C3 (C3)

Output

C1 (C2)

Output

C2 (C1)

...

Output

C3 (C3)

Output

C1 (C2)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

Output

C2 (C1)

Output

C3 (C3)

Output

C1 (C2)

Output

C2 (C1)

Output

C3 (C3)

Output

C1 (C2)

...

Remark ( ) indicates the case of left shift.

Figure 5

-
-
-
-

3. Pixel Arrangement of Single-Side Delta Array and Multiplexer Operation

R B

G R B G

C2
C3

PD16449

Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "H"

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Figure 5

-
-
-
-

4. Timing Chart of Single-Side Delta Array

RESET

INH

240

)

Sampling
input data

Output

239

)

Sampling
input data

238

)

Sampling
inputdata

239

)

Sampling
input data

240

)

Sampling
input data

Output

C1 (C3)

C2 (C1)

undifined

C1 (C3)

C2 (C1)

C2 (C2)

C3 (C3)

C2 (C2)

C3 (C3)

C3 (C1)

C1 (C2)

C3 (C1)

C1 (C2)

C2 (C2)

C3 (C3)

C2 (C2)

C3 (C3)

C3 (C1)

C1 (C2)

C3 (C1)

C1 (C2)

undifined

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

5.1.3 Double-side delta array mode (MP/TH = H, MP/1.5 = H)
Because the pad pitch of the

PD16449 is designed so that the IC is mounted on one side, the output pitch must be

expanded on the TCP if the IC is mounted on both sides.

Table 5

-
-
-
-

3. Relation between Video Signals C1 to C3 and Output Pins

Line No.

(number of INHn)

RESET

INH

240

)

239

)

238

)

237

)

...

239

)

240

)

Undefined

...

Undefined

Sampling

C2 (C3)

Sampling

C3 (C2)

Sampling

C1 (C1)

Sampling

C2 (C3)

... Sampling

C3 (C2)

Sampling

C1 (C1)

Output

C2 (C3)

Output

C3 (C2)

Output

C1 (C1)

Output

C2 (C3)

...

Output

C3 (C2)

Output

C1 (C1)

Output

C1 (C1)

Output

C2 (C3)

Output

C3 (C2)

Output

C1 (C1)

...

Output

C2 (C3)

Output

C3 (C2)

Output

C2 (C3)

Output

C3 (C2)

Output

C1 (C1)

Output

C2 (C3)

...

Output

C3 (C2)

Output

C1 (C1)

Output

C1 (C1)

Output

C2 (C3)

Output

C3 (C2)

Output

C1 (C1)

...

Output

C2 (C3)

Output

C3 (C2)

...

Remark ( ) indicates the case of left shift.

Figure 5

-
-
-
-

5. Pixel Arrangement of Double-Side Delta Array and Multiplexer Operation

C2
C3

PD16449

Right shift (R,/L = "H"), MP/TH = "H", MP/1.5 = "H"

237

238

239

240

C2
C3

R
B

PD16449

Left shift (R,/L = "L"), MP/TH = "H", MP/1.5 = "H"

Data Sheet S15677EJ1V0DS

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µ
µ
µ

PD16449

Figure 5

-
-
-
-

6. Timing Chart of Both-Sides Delta Array

RESET

INH

240

)

Sampling
input data

Output

239

)

Sampling
input data

238

)

Sampling
inputdata

239

)

Sampling
input data

240

)

Sampling
input data

Output

C2 (C3)

C1 (C1)

undifined

C2 (C3)

C1 (C1)

C3 (C2)

C2 (C3)

C3(C2)

C3 (C2)

C2 (C3)

C1 (C1)

C1(C1)

C3 (C2)

C1 (C1)

C3 (C2)

C2 (C3)

C3 (C2)

C2 (C3)

C1 (C1)

C3 (C2)

C1 (C1)

C3 (C2)

undifined

Data Sheet S15677EJ1V0DS

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µ
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µ

PD16449

5.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L)

Table 5

-
-
-
-

4. Relation between Video Signals C1 to C3, and Output Pins

Line No.

(number of INHn)

RESET

INH

240

)

239

)

238

)

237

)

...

239

)

240

)

Undefined

...

Undefined

Sampling

C1 (C3)

Sampling

C2 (C2)

Sampling

C3 (C1)

Sampling

C1 (C3)

... Sampling

C2 (C2)

Sampling

C3 (C1)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

Output

C3 (C2)

Output

C1 (C1)

Output

C2 (C3)

Output

C3 (C2)

...

Output

C1 (C1)

Output

C2 (C3)

Output

C2 (C1)

Output

C3 (C3)

Output

C1 (C2)

Output

C2 (C1)

...

Output

C3 (C3)

Output

C1 (C2)

Output

C1 (C3)

Output

C2 (C2)

Output

C3 (C1)

Output

C1 (C3)

...

Output

C2 (C2)

Output

C3 (C1)

...

Remark ( ) indicates the case of left shift.

Figure 5

-
-
-
-

7. Pixel Arrangement of Mosaic Array and Multiplexer Operation

C2
C3

PD16449

Right shift (R,/L = "H"), MP/TH = "H", MP/1.5 = "L"

Data Sheet S15677EJ1V0DS

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µ
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µ

PD16449

Figure 5

-
-
-
-

8. Timing Chart of Mosaic Array

RESET

INH

240

)

Sampling
input data

Output

239

)

Sampling
input data

238

)

Sampling
inputdata

239

)

Sampling
input data

240

)

Sampling
input data

Output

C1 (C3)

C3 (C2)

undifined

C2 (C1)

C1 (C3)

C2 (C2)

C1 (C1)

C3(C3)

C3 (C3)

C2 (C2)

C3 (C1)

C3(C1)

C2 (C3)

C1 (C2)

C3 (C1)

C2 (C2)

C1 (C1)

C3 (C3)

C2 (C2)

C3 (C1)

C2 (C3)

C1 (C2)

C3 (C1)

undifined

Data Sheet S15677EJ1V0DS

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µ
µ
µ

PD16449

5.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn

(1) Simultaneous sampling ( ( ) indicates the case of left shift.)

C1 sampling

C2 sampling

C3 sampling

SHP

(SHP

240

)

STHR (STHL)

CLI1

SHP

(SHP

239

)

SHP

(SHP

238

)

SHP

(SHP

237

)

SHP

(SHP

236

)

SHP

(SHP

235

)

C1 sampling

C2 sampling

C3 sampling

Remark C1 through C3 are sampled while SHPn is high level.

(2) Successive sampling ( ( ) indicates the case of left shift.)

C1 sampling

3-phase clock

C2 samling

C3 sampling

C1 sampling

C2 sampling

C3 sampling

SHP

(SHP

240

)

STHR (STHL)

CLI3

CLI2

CLI1

SHP

(SHP

239

)

SHP

(SHP

238

)

SHP

(SHP

237

)

SHP

(SHP

236

)

SHP

(SHP

235

)

Remarks 1. Input a three-phase clock to shift clock pins CLI1 through CLI3.

2. The video signals (C1 to C3) are sampled while SHPn is high level.

Data Sheet S15677EJ1V0DS

µ
µ
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µ

PD16449

5.2 Sample and Hold Circuit

The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer
circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and change at the rising and
falling edges of the INH signal (refer to 1. BLOCK DIAGRAM.).

RESET

Data

Swa1

Swa2

Swb1

Swb2

INH

undifined

5.3 Write Operation Timing

The sampled video signals are written to the LCD panel by output currents I

VOL

and I

VOH

via output buffer. The

dynamic range is 4.3 V MIN. (V

DD2

= 5.0 V).

While INH = H, do not stop shift clocks CLI1 through CLI3.
The output operation of this IC is controlled by INH signals.
INH = Hi-Z
INH = Connected with internal circuit (switch sample and hold circuit at the falling edge.)
Therefore, performing V

COM

inversion while INH = L causes current flow to these IC output pins, which may result

in malfunction. Perform V

COM

in version during INH = H (Hi-Z) and start output operation of the next line after the V

COM

signal is stable enough to operate. Make sure to evaluate this output operation sufficiently.

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Cautions 1. Turn on power to V

DD1

, logic input, V

DD2

, and video signal input in that order to prevent

destruction due to latch-up, and turn off power in the reverse sequence. Observe this power
sequence even during the transition period.

The

µ
µ
µ
µ

PD16449 is designed to input successive signals such as chrome signals. The input band

of the video signals is designed to be 9 MHz MAX. If video signals faster than that are input,
display is not performed correctly.

Insert a bypass capacitor of 0.1

µ
µ
µ
µ

F between V

DD1

and V

SS1

and between V

DD2

and V

SS2

. If the

power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage
fluctuates.

Display may not be correctly performed if noise is superimposed on the start pulse pin.
Therefore, be sure to input a reset signal during the vertical blanking period.

Even if the start pulse width is extended by half a clock or more, sampling start timing SHP

not affected, and the sampling operation is performed normally.

When the multiplexer circuit is used in the vertical stripe mode, C1 to C3 are simultaneously
sampled at the rising edge of SHPn. Internally, however, only CLI1 is valid. Therefore, input a
shift clock to CLI1 only. At this time, keep the CLI2 and CLI3 pins to "L".
When using the multiplexer circuit in the delta array mode or mosaic array mode, C1 to C3 are
sequentially sampled. Input a three-phase clock to CLI1 through CLI3 (for the sampling timing,
refer to 5. FUNCTIONAL DESCRIPTION.).

The recommended timing of t

R-1

and PW

RES

on starting is shown below (The following timing

chart shows simultaneous sampling.).

An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH

pulse is input after reset, sampling is not performed in the correct sequence.

CLI1

RESET

INH

STHR (STHL)

SHP

to SHP

SHP

to SHP

SHP

to SHP

RES

ISETUP

IHOLD

INH

: 5 clocks MIN.

3 clocks MIN.

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

6. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

°
°
°
°

C, V

SS1

= 0 V)

Parameter

Symbol

Condition

Ratings

Unit

Logic supply voltage

DD1

0.5 to +6.0

Driver supply voltage

DD2

0.5 to +6.0

Logic input voltage

0.5 to V

DD1

+0.5

Video input voltage

C1 to C3

0.5 to V

DD2

+0.5

Logic output voltage

0.5 to V

DD1

+0.5

Driver output voltage

0.5 to V

DD2

+0.5

Driver output current

Operating temperature range

30 to +85

Storage temperature range

stg

65 to +125

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Conditions (T

= 40 to +85

°
°
°
°

C, V

SS1

= V

SS2

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Logic supply voltage

DD1

3.0

3.3

5.5

Driver supply voltage

DD2

4.5

5.0

5.5

Video input voltage

SS2

+ 0.35

DD2

0.35

Driver output voltage

SS2

+ 0.35

DD2

0.35

High level Input voltage

0.7 V

DD1

Low level Input voltage

0.3 V

DD1

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Electrical Characteristics (T

-
-
-
-

30 to +85

°
°
°
°

C, V

DD1

= 3.0 to 5.5 V, V

DD2

= 5.0 V

±
±
±
±

0.5 V, V

SS1

= V

SS2

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Maximum video signal output voltage

VOH

0.35

Minimum video signal output voltage

VOL

0.35

Logic high level output voltage

LOH

STHL, STHR pins,
I

1.0 mA

0.9 V

DD1

Logic low level output voltage

LOL

STHL, STHR pins
I

= 1.0 mA

0.1 V

DD1

Video signal high level output current

VOH

= L, V

= V

DD2

1.0 V

= V

DD2

0.5 V

0.20

0.08

Video signal low level output current

VOL

= L, V

= 1.0 V, V

= 0.5 V

0.08

0.20

Reference voltage 1

REF1

DD2

= 5.0 V, T

= 25

= 0.5 V

0.49

Reference voltage 2

REF2

DD2

= 5.0 V, T

= 25

= 2.0 V

1.99

Reference voltage 3

REF3

DD2

= 5.0 V, T

= 25

= 3.5 V

3.49

Output voltage deviation 1

VO1

DD2

= 5.0 V, T

= 25

= 0.5 V

Output voltage deviation 2

VO2

DD2

= 5.0 V, T

= 25

= 2.0 V

Output voltage deviation 3

VO3

DD2

= 5.0 V, T

= 25

= 3.5 V

Logic input leakage current

1.0

Video input leakage current

DD1

3.3 V

0.3 V

2.5

Logic dynamic current consumption

DD1

CLI

= 14 MHz

= 2.0 V, no load,

INH

= 15.4 kHz,

INH

= 5.0

DD1

5.0 V

0.5 V

4.0

Driver dynamic current consumption

DD2

CLI

= 14 MHz

= 2.0 V, no load,

INH

= 15.4 kHz,

INH

= 5.0

10.0

Remarks 1. V

: output applied voltage, V

: output voltage without load

2. The reference values are typical values only. The output deviation is only guaranteed within the chip.

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

Switching Characteristics (T

-
-
-
-

30 to +85

°
°
°
°

C, V

DD1

= 3.0 to 5.5 V, V

DD2

= 5.0 V

±
±
±
±

0.5 V, V

SS1

= V

SS2

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

PHL

= 20 pF

Start pulse propagation delay
time

PLH

= 20 pF

Clock frequency 1

CLK 1

MHz

Clock frequency 2

CLK 2

With 3-phase clock input

MHz

Logic input capacitance

Other than STHL, STHR

STHL, STHR input capacitance

STHL, STHR

Video input capacitance

C1 to C3, V

= 2.0 V

Timing Requirements (T

-
-
-
-

30 to +85

°
°
°
°

C, V

DD1

= 3.0 to 5.5 V, V

DD2

= 5.0 V

±
±
±
±

0.5 V, V

SS1

= V

SS2

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Clock pulse width

CLI

Duty = 50%

Start pulse setup time

SETUP

Start pulse hold time

HOLD

Reset pulse width

RES

INH setup time

ISETUP

INH hold time

IHOLD

Reset-INH time

R-I

INH pulse width

INH

CLK

Remark Keep the rise and fall times of the logic input signals to within t

= t

= 5 ns (10 to 90%).

As an example, the switching characteristic wave of CLI1 is defined on the next page.

Data Sheet S15677EJ1V0DS

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µ
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µ

PD16449

Switching Characteristic Waveform (Simultaneous/successive sampling)

Start Pulse Input Timing

1/f

CLI

50%

SETUP

HOLD

CLI1

STHR

(STHL)

SHP

(SHP

240

)

DD1

SS1

DD1

SS1

DD1

SS1

Start Pulse Output Timing

50%

PLH

50%

PHL

CLI1

STHL

(STHR)

DD1

SS1

Remark The input/output timing of the start pulse is the same for simultaneous/successive sampling.

Data Sheet S15677EJ1V0DS

µ
µ
µ
µ

PD16449

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

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Document Outline

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