Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- 1. BLOCK DIAGRAM
- 2. PIN CONFIGURATION ( uPD16364N-xxx: Copper foil surface, Face-up)
- 3. PIN FUNCTIONS
- 4. TRUTH TABLE
- 5. ELECTRICAL SPECIFICATIONS
- 6. RECOMMENDED SOLDERING CONDITIONS
1999
MOS INTEGRATED CIRCUIT
PD16364
160-BIT HIGH-VOLTAGE CMOS DRIVER
Document No. S14000EJ2V0DS00 (2nd edition)
Date Published November 2002 NS CP(K)
Printed in Japan
DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
DESCRIPTION
The
PD16364 is a high-voltage CMOS driver for EL display. It consists of 4
40/8
20-bit data latch, 160-bits
data latch, 160-bit level shifter, and a high-voltage CMOS driver. The logic circuit operates on 5-V power supply
(CMOS level input), so that it can be connected to a micro-controller. The driver block is comprised of 60 V, 25 mA
MAX. high-voltage output buffer, and both the logic block and driver block employ a CMOS, allowing operation with
low power consumption.
FEATURES
High-voltage Full CMOS process
High-voltage output (60 V, 25 mA MAX.)
4
40/8
20-bit data latch (4/8-bit data input)
High-speed data transfer (f
CLK
= 16 MHz: in cascade connection)
Wide operating temperature range (T
A
=
-
40 to +85C)
ORDERING INFORMATION
Part Number
Package
PD16364N -
TCP (TAB package)
Remark The TCP's external shape is customized. To order the required shape, please contact one of our sales
representatives.
The mark
5
5
5
5
shows major revised points.
Data Sheet S14000EJ2V0DS
2
PD16364
1. BLOCK DIAGRAM
Control
Circuit
DST
SCK
EIO1
EIO2
20/40-bit Latch Selector
4 X 20/8 X 20-bit Data Latch
160-bit Data Latch
20/40
160
160-bit Level Shifter
160
160-bit HIgh-Voltage CMOS Driver
160
L,/R
Data
MPX
4/8
D
0
D
7
V
DD1
V
SS1
V
DD2
V
SS2
OUT1
OUT
157
OUT
158
OC
BS
REV
OUT
159
OUT
160
OUT2 OUT3 OUT4
Remark /xxx indicates active low signal.
Data Sheet S14000EJ2V0DS
3
PD16364
2. PIN CONFIGURATION (
PD16364N-xxx: Copper foil surface, Face-up)
DUMMY
V
SS2
V
DD2
BS
L,/R
OC
REV
DST
CLK
EIO1
EIO2
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT157
OUT158
OUT159
OUT160
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
OUT156
V
DD2
V
SS2
V
DD2
V
DD2
V
SS2
V
SS2
V
SS1
V
DD1
Copper foil
suface
Remark This figure does not specify the TCP package.
Caution Be sure to use all the V
DD1
, V
DD2
, V
SS1
, and V
SS2
pins. Keep the V
SS1
and V
SS2
pins at the
same voltage level.
Data Sheet S14000EJ2V0DS
4
PD16364
3. PIN FUNCTIONS
Pin Symbol
Pin Name
I/O
Description
EIO1
Enable I/O1
I/O
L,/R pin = "L" level: Input
L,/R pin = "H" level: Output
EIO2
Enable I/O2
I/O
L,/R pin = "H" level: Input
L,/R pin = "L" level: Output
SCK
Shift Clock Input
Input
Fall edge operation. Input shift clock for 4 x 40/8 x 20-bit data latch.
DST
Data Strobe Input
Input
Fall edge operation. Data are latched to 160-bits data latch and also set
outputs of OUT1 to OUT160.
D
0
to D
7
Data Input
Input
Data input. When BS is low level, D
4
to D
7
pins should be connected to V
SS1
or V
DD1
.
L,/R
Select Left or Right
Shift
Input
Refer to 4.TRUTH TABLE
OC
Output Control
Input
When OC pin is low level, output is normal operation.
When OC pin is high level, output become low level.
REV
Invert Input Data
Input
When REV pin is low level, input data D
0
to D
7
are latched without inversion.
When REV pin is high level, input data D
0
to D
7
are inverted before latching.
BS
Bus Select
Input
When BS pin is low level, data bus is4 bits.
When BS pin is high level, data bus is 8 bits.
OUT1 to
OUT160
High-voltage output
Output
Output level is V
SS2
or V
DD2
. These outputs are changed by falling edge of
DST pin.
V
DD1
Logic power supply
Logic power supply
V
DD2
Driver power supply
Driver power supply
V
SS1
Logic ground
Grounding
V
SS2
Driver ground
Grounding
!
!
Data Sheet S14000EJ2V0DS
5
PD16364
4. TRUTH TABLE
Shift Register Block (4 x 40 data latch, BS = L)
L,/R
SCK
1
2
3
...
40
D
3
1
5
9
...
157
D
2
2
6
10
...
158
D
1
3
7
11
...
159
L level
D
0
4
8
12
...
160
D
3
160
156
152
...
4
D
2
159
155
151
...
3
D
1
158
154
150
...
2
H level
D
0
157
153
149
...
1
Shift Register Block (8 x 20 data latch, BS = H)
L,/R
SCK
1
2
3
...
20
D
7
1
9
17
...
153
D
6
2
10
18
...
154
D
5
3
11
19
...
155
D
4
4
12
20
...
156
D
3
5
13
21
...
157
D
2
6
14
22
...
158
D
1
7
15
23
...
159
L level
D
0
8
16
24
...
160
D
7
160
152
144
...
8
D
6
159
151
143
...
7
D
5
158
150
142
...
6
D
4
157
149
141
...
5
D
3
156
148
140
...
4
D
2
155
147
139
...
3
D
1
154
146
138
...
2
H level
D
0
153
145
137
...
1
Control Block
L,/R
EIO1
EIO2
H level
Out
In
L level
In
Out
Driver Block
OC
REV
Dn
Driver Output
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
L
H
x
x
L (All driver outputs are L.)
!
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