1999
MOS INTEGRATED CIRCUIT
PD16315
1/4- to 1/12-DUTY FIP
TM
(VFD) CONTROLLER/DRIVER
DATA SHEET
Document No. S14074EJ1V0DS00 (1st edition)
Date Published February 2003 NS CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
DESCRIPTION
The
PD16315 is a FIP (Fluorescent Indicator Panel, or Vacuum Fluorescent Display) controller/driver that is driven on a
1/4- to 1/12- duty factor. It consists of 16 segment output lines, 4 grid output lines, 8 segment/grid output drive lines, a
display memory, a control circuit, and a key scan circuit. Serial data is input to the
PD16315 through a three-line serial
interface. This FIP controller/driver is ideal as a peripheral device for a single-chip microcomputer.
FEATURES
Multiple display modes: 16-segment & 12-digit to 24-segment & 4-digit
Key scanning: 16 x 2 matrix
Dimming circuit: 8 steps
High-withstanding-voltage output: V
DD
-
35 V MAX.
LED ports: 4 chs., 20 mA MAX.
No external resistors necessary for driver outputs: P-ch open-drain + pull-down resistor output
Serial interface: CLK, STB, D
IN
, D
OUT
ORDERING INFORMATION
Part Number
Package
PD16315GB-3BS
44-pin Plastic QFP (10 x 10)
Data Sheet S14074EJ1V0DS
2
PD16315
1. BLOCK DIAGRAM
D
IN
D
OUT
CLK
STB
R
OSC
Key1, Key2
LED
1
LED
4
V
DD
V
SS
V
EE
(+5 V)
(0 V)
(
-
30 V)
Seg
1
/KS
1
Seg
16
/KS
16
Seg
17
/Grid
12
Seg
24
/Grid
5
Grid
4
Grid
1
24
16
8
8
8
12
2
4
Serial
interface
OSC
Display memory
24 bits x 12 words
Key data memory (2 x 16 bits)
4-bit latch
12-bit shift register
24-bit output latch
Command decoder
Dimming circuit
Timing generator
key scan
Gr
id dr
iv
er
Data selector
Multiple
x
ed dr
iv
er
Segment dr
iv
er
Data Sheet S14074EJ1V0DS
3
PD16315
2. PIN CONFIGURATION (Top View)
44-pin Plastic QFP (10 x 10)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
LED
1
LED
2
LED
3
LED
4
OSC
D
OUT
D
IN
CLK
STB
KEY
1
KEY
2
V
SS
V
DD
Seg
1
/KS
1
Seg
2
/KS
2
Seg
3
/KS
3
Seg
4
/KS
4
Seg
5
/KS
5
Seg
6
/KS
6
Seg
7
/KS
7
Seg
8
/KS
8
Seg
9
/KS
9
Seg
19
/Grid
10
Seg
18
/Grid
11
Seg
17
/Grid
12
V
EE
Seg
16
/KS
16
Seg
15
/KS
15
Seg
14
/KS
14
Seg
13
/KS
13
Seg
12
/KS
12
Seg
11
/KS
11
Seg
10
/KS
10
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
V
SS
V
DD
Gr
id
1
Gr
id
2
Gr
id
3
Gr
id
4
Seg
24
/Gr
id
5
Seg
23
/Gr
id
6
Seg
22
/Gr
id
7
Seg
21
/Gr
id
8
Seg
20
/Gr
id
9
Caution Use all of the power supply pins.
Data Sheet S14074EJ1V0DS
4
PD16315
3. PIN FUNCTION
Symbol
Pin Name
Pin No.
I/O
Description
D
IN
Data input
7
Input
Input serial data at rising edge of shift clock, starting from the low
order bit.
D
OUT
Data output
6
Output
Output serial data at the falling edge of the shift clock, starting
from low order bit. This is N-ch open-drain output pin.
STB
Strobe
9
-
Initializes serial interface at the rising or falling edge of the
PD16315. It then waits for reception of a command. Data input
after STB has fallen is processed as a command. While
command data is processed, current processing is stopped, and
the serial interface is initialized. While STB is high, CLK is
ignored.
CLK
Clock input
8
Input
Reads serial data at the rising edge, and outputs data at the
falling edge.
OSC
Oscillator pin
5
-
Connect resistor to this pin to determine the oscillation frequency
to this pin. Connect resistor between this pin and GND (V
SS
).
Seg
1
/KS
1
to
Seg
16
/KS
16
High-withstanding-voltage
output (Segment)
14 to 29
Output
Segment output pins (Dual function as key source)
Grid
1
to Grid
4
High-withstanding-voltage
output (grid)
39 to 42
Output
Grid output pins
Seg
17
/Grid
12
to
Seg
24
/Grid
5
High-withstanding-voltage
output (segment/grid)
31 to 38
Output
These pins are selectable for segment or grid driving.
LED
1
to LED
4
LED output
1 to 4
Output
CMOS output, +20 mA MAX.
KEY
1
, KEY
2
Key data input
10, 11
Input
Data input to these pins is latched at the end of the display cycle.
V
DD
Logic power
13, 43
-
5 V
10%
V
SS
Logic ground
12, 44
-
Connect this pin to system GND.
V
EE
Pull-down level
30
-
V
DD
-
35 V MAX.
Data Sheet S14074EJ1V0DS
5
PD16315
4. DISPLAY RAM ADDRESS AND DISPLAY MODE
The display RAM stores the data transmitted to the
PD16315 through the serial communication. The addresses are
allocated in 8-bit units.
Seg
1
Seg
4
Seg
8
Seg
12
Seg
16
Seg
20
Seg
24
00H
L
00H
U
01H
L
01H
U
02H
L
02H
U
DIG
1
03H
L
03H
U
04H
L
04H
U
05H
L
05H
U
DIG
2
06H
L
06H
U
07H
L
07H
U
08H
L
08H
U
DIG
3
09H
L
09H
U
0AH
L
0AH
U
0BH
L
0BH
U
DIG
4
0CH
L
0CH
U
0DH
L
0DH
U
0EH
L
0EH
U
DIG
5
0FH
L
0FH
U
10H
L
10H
U
11H
L
11H
U
DIG
6
12H
L
12H
U
13H
L
13H
U
14H
L
14H
U
DIG
7
15H
L
15H
U
16H
L
16H
U
17H
L
17H
U
DIG
8
18H
L
18H
U
19H
L
19H
U
1AH
L
1AH
U
DIG
9
1BH
L
1BH
U
1CH
L
1CH
U
1DH
L
1DH
U
DIG
10
1EH
L
1EH
U
1FH
L
1FH
U
20H
L
20H
U
DIG
11
21H
L
21H
U
22H
L
22H
U
23H
L
23H
U
DIG
12
b0
b3
b4
b7
XXH
L
XXH
U
Lower 4 bits
Higher 4 bits
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