NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module
Preliminary
08 / 2001
1
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
32Mx64 bit One Bank Unbuffered SDRAM Module
based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
Features
l
168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
l
Intended for PC133 applications
- Clock Frequency: 133MHz
- Clock Cycle: 7.5ns
- Clock Assess Time: 5.4ns
l
Inputs and outputs are LVTTL (3.3V) compatible
l
Single 3.3V
0.3V Power Supply
l
Single Pulsed RAS interface
l
SDRAMs have 4 internal banks
l
Module has 1 physical bank
l
Fully Synchronous to positive Clock Edge
l
Data Mask for Byte Read/Write control
l
Auto Refresh (CBR) and Self Refresh
l
Automatic and controlled Precharge commands
l
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
l
Suspend Mode and Power Down Mode
l
8192 Refresh cycles distributed across 64ms
l
Gold contacts
l
SDRAMs in TSOP Type II Package
l
Serial Presence Detect with Write Protect
Description
NT256S64V88A0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMM) which is organized as 16Mx64
high-speed memory arrays and is configured as one 16M x 64 physical bank. The DIMM uses eight 32Mx8 SDRAMs in 400mil TSOP II
packages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
supports the JEDEC 1N rule while allowing very low burst power.
All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK2). Internal operating modes are defined by combinations
of RAS , CAS , WE , S0 / S2 , DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 15-bit
address bus accepts address information in a row / column multiplexing arrangement.
Prior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.
Ordering Information
Speed
Part Number
Organization
MHz.
CL
t RCD
t RP
Leads
Power
143MHz
3
3
3
NT256S64V88A0G-7K
133MHz
2
2
2
133MHz
3
3
3
NT256S64V88A0G-75B
100MHz
2
2
2
125MHz
3
3
3
NT256S64V88A0G-8B
32Mx64
100MHz
2
2
2
Gold
3.3V
* CL =
CAS Latency
NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module
Preliminary
08 / 2001
2
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Description
CK0, CK2
Clock Inputs
DQ0-DQ63
Data input/output
CK1, CK3
Unused (terminated) Clock Inputs
CB0-CB7
Check Bit Data input/output
CKE0
Clock Enable
DQMB0-DQMB7
Data Mask
RAS
Row Address Strobe
V
DD
Power (3.3V)
CAS
Column Address Strobe
V
SS
Ground
WE
Write Enable
NC
No Connect
S0 , S2
Chip Selects
SCL
Serial Presence Detect Clock Input
A0-A9, A11, A12
Address Inputs
SDA
Serial Presence Detect Data input/output
A10 / AP
Address Input/Autoprecharge
SA0-2
Serial Presence Detect Address Inputs
BA0, BA1
SDRAM Bank Address Inputs
WP
Serial Presence Detect Write Protect Input
Pinout
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
V
SS
85
V
SS
29
DQMB1
113
DQMB5
57
DQ18
141
DQ50
2
DQ0
86
DQ32
30
S0
114
NC
58
DQ19
142
DQ51
3
DQ1
87
DQ33
31
NC
115
RAS
59
V
DD
143
V
DD
4
DQ2
88
DQ34
32
V
SS
116
V
SS
60
DQ20
144
DQ52
5
DQ3
89
DQ35
33
A0
117
A1
61
NC
145
NC
6
V
DD
90
V
DD
34
A2
118
A3
62
NC
146
NC
7
DQ4
91
DQ36
35
A4
119
A5
63
NC
147
NC
8
DQ5
92
DQ37
36
A6
120
A7
64
V
SS
148
V
SS
9
DQ6
93
DQ38
37
A8
121
A9
65
DQ21
149
DQ53
10
DQ7
94
DQ39
38
A10/AP
122
BA0
66
DQ22
150
DQ54
11
DQ8
95
DQ40
39
BA1
123
A11
67
DQ23
151
DQ55
12
V
SS
96
V
SS
40
V
DD
124
V
DD
68
V
SS
152
V
SS
13
DQ9
97
DQ41
41
V
DD
125
*CK1
69
DQ24
153
DQ56
14
DQ10
98
DQ42
42
CK0
126
A12
70
DQ25
154
DQ57
15
DQ11
99
DQ43
43
V
SS
127
V
SS
71
DQ26
155
DQ58
16
DQ12
100
DQ44
44
NC
128
CKE0
72
DQ27
156
DQ59
17
DQ13
101
DQ45
45
S2
129
NC
73
V
DD
157
V
DD
18
V
DD
102
V
DD
46
DQMB2
130
DQMB6
74
DQ28
158
DQ60
19
DQ14
103
DQ46
47
DQMB3
131
DQMB7
75
DQ29
159
DQ61
20
DQ15
104
DQ47
48
NC
132
NC
76
DQ30
160
DQ62
21
CB0
105
CB4
49
V
DD
133
V
DD
77
DQ31
161
DQ63
22
CB1
106
CB5
50
NC
134
NC
78
V
SS
162
V
SS
23
V
SS
107
V
SS
51
NC
135
NC
79
CK2
163
*CK3
24
NC
108
NC
52
CB2
136
CB6
80
NC
164
NC
25
NC
109
NC
53
CB3
137
CB7
81
WP
165
SA0
26
V
DD
110
V
DD
54
V
SS
138
V
SS
82
SDA
166
SA1
27
WE
111
CAS
55
DQ16
139
DQ48
83
SCL
167
SA2
28
DQMB0
112
DQMB4
56
DQ17
140
DQ49
84
V
DD
168
V
DD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
*CK1 and CK3 are terminated .
NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module
Preliminary
08 / 2001
3
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
SDRAM DIMM Block Diagram
(1 Bank, 32Mx8 SDRAMs)
S0
DQMB0
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D0
DQMB4
DQM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D4
DQMB1
DQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D1
DQMB5
DQM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D5
S2
DQMB2
DQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U2
DQMB6
DQM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D6
DQMB3
DQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D3
DQMB7
DQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
D7
RAS
CAS
CKE0
WE
A0-A12
BA0
BA1
RAS : SDRAMs D0-D7
CAS : SDRAMs D0-D7
CKE0 : SDRAMs D0-D7
WE : SDRAMs D0-D7
A0-A12 : SDRAMs D0-D7
BA0 : SDRAMs D0-D7
BA1 : SDRAMs D0-D7
SPD
A0
A1
A2
SCL
WP
SA0 SA1 SA2
V
DD
V
SS
D0 - D7
D0 - D7
SDA
0.1uF
3.3pF
CK0
SDRAM
SDRAM
SDRAM
SDRAM
3.3pF
CK2
SDRAM
SDRAM
SDRAM
SDRAM
CK1,CK3
10pF
* All resistor values are 10 ohms except as shown.
*
47k
0.33uF
CK0
CK2
CLK : SDRAMs D0-D1, D4-D5, 3.3pF Cap.
CLK : SDRAMs D2-D3, D6-D7, 3.3pF Cap.
NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module
Preliminary
08 / 2001
4
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0 , CK2
Input
Pulse
Positive
Edge
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
their associated clock.
CKE0
Input
Level
Active
High
Activates the SDRAM CK0 and CK2 signals when high and deactivates them when low.
By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or
the Self-Refresh mode.
S0 , S2
Input
Pulse
Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
RAS
,
CAS
,
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, RAS
,
CAS
,
WE define the
operation to be executed by the SDRAM.
BA0, BA1
Input
Level
-
Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11, A12
Input
Level
-
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
DQ0 - DQ63,
CB0 - CB7
Input
/Output
Level
-
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQMB0 -DQMB7
Input
Pulse
Active
High
The Data input/output mask places the DQ buffers in a high impedance state when
sampled high. In Read mode, DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM has a latency of zero and
operates as a byte mask by allowing input data to be written if it is low but blocks the
Write operation if DQM is high.
SA0 SA2
Input
Level
-
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
Input
/Output
Level
-
Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
SCL
Input
Pulse
-
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the "high" state, a pull-up resistor is recommended on
the system board.
WP
Input
Level
Active
High
Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.
V
DD
, V
SS
Supply
Power and ground for the module.
NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module
Preliminary
08 / 2001
5
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Notes
V
DD
Power Supply Voltage
-0.3 to +4.6
V
IN
Input Voltage
-0.3 to V
DD
+0.3
V
OUT
Output Voltage
-0.3 to V
DD
+0.3
V
1
T
A
Operating Temperature (ambient)
0 to +70
C
1
T
STG
Storage Temperature
-55 to +125
C
1
P
D
Power Dissipation
5.1
W
1
I
OUT
Short Circuit Output Current
50
mA
1
1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
(T
A
=0 to 70
C)
Rating
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
V
DD
Power Voltage
3.0
3.3
3.6
V
1
V
IH
Input High Voltage
2.0
-
V
DD
+ 0.3
V
1,2
V
IL
Input Low Voltage
-0.3
-
0.8
V
1,3
V
OH
Output High Voltage
2.4
-
-
V
V
OL
Output Low Voltage
-
-
0.4
V
I
IL
Input Leakage current
-10
-
10
uA
1. All voltages referenced to V
SS
.
2. V
IH
(max) = V
DD
/ V
DDQ
+ 1.2V for pulse width
5ns
3.
V
IL
(min) = V
SS
/ V
SSQ
- 1.2V for pulse width
5ns .
Capacitance
(T
A
=25 C , f =1MHz, V
DD
=3.3 0.3V)
Symbol
Parameter
Max.
Unit
C
I1
Input Capacitance (A0-A9, A10/AP, A11, BA0, BA1, RAS
,
CAS
,
WE )
74
C
I2
Input Capacitance (CKE0)
54
C
I3
Input Capacitance ( S0 - S2 )
30
C
I4
Input Capacitance (CK0 - CK3)
40
C
I5
Input Capacitance (DQMB0 - DQMB7)
17
C
I6
Input Capacitance (SA0 - SA2, SCL, WP)
9
C
IO1
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
10
C
IO2
Input/Output Capacitance (SDA)
11
pF
DC Output Load Circuit
VOH(DC) = 2.4V,IOH= -2mA
VOL(DC) = 0.4V,IOL= -2mA
3.3 V
1200 ohms
870 ohms
50 pF
Output
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