3UHOLPLQDU\
MTL113
Single-chip SXGA LCD Controller with RSDS
sales@myson.com.tw
www.myson.com.tw
Rev. 0.9 April 2003
page 1 of 111
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
GENERAL DESCRIPTION
The MTL113 Singal-chip SXGA LCD controller is a
low-cost input format converter for TFT-LCD Monitor
or LCD TV application which accepts 15-pin D-sub
RGB graphic signals, YUV signals from digital video
decoder or digital RGB graphic signals from
PanelLink TMDS receiver. It includes a RGB/YUV
input processor, video scaling up and down
processor, OSD output display processor,
programmable timing controller and RSDS interface
in 208-pin PQFP package.
FEATURES
General
Auto configuration of sampling clock frequency,
phase, H/V center, as well as white balance.
Auto detection of present or non-present or over
range sync signals and their polarities.
Composite sync separation and odd/even field
detection of interlaced video.
No external memory required.
On-chip output PLL provide clock frequency fine-
tune (inverse, duty cycle and delay).
Serial 2-wire I
2
C host interface.
Parallel 6-wire or 10-wire data transfer host
interface.
Embedded OSD engine.
Embedded 8-bit resolution ADC.
Embedded programmable timing controller.
Embedded power on reset circuit.
2.5V/3.3V supplier in 208-pin PQFP package.
Input Processor
ADC sample rate and Digital Single RGB (24-bit)
input rates up to 135MHz.
Support both non-interlaced and interlaced RGB
graphic input signals.
Support sync on green input format.
YUV 4:2:2 or YUV 4:1:1 (CCIR601/CCIR656)
interlaced video input.
Glue-less connection to Philips SAA711x digital
video decoder
Built-in YUV to RGB color space converter.
Compliant with digital LVDS/PanelLink TMDS
input interface.
PC input resolution up to SXGA 1280X1024 @
75Hz.
Video Processor
Independent programmable Horizontal and
Vertical scaling up ratios from 1 to 32
Support scaling down ratios from 1 to 1/2.
Flexible de-interlacing unit for digital YUV video
input data.
Zoom to full screen resolution of de-interlaced
YUV video data stream.
Built-in programmable gain control for white
balance alignments.
Built-in programmable 10-bit gamma correction
table.
Built-in programmable temporal color dithering
Built-in programmable interpolation look-up table.
Built-in programmable sharpening & smoothing
filters for edge enhancement.
Support smooth panning under viewing window
change.
Output Processor
Single pixel (18/24-bit) or Dual pixel (36/48-bit)
per clock digital RGB output.
Built-in output timing generator with
programmable clock and H/V sync.
Support VGA/SVGA/XGA/SXGA display
resolution.
Overlay input interface with external OSD
controller.
Double scan capability for interlaced input.
Support RSDS(Reduced Swing Differential
Signaling) output format
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