This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
1/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
FEATURES
GENERAL DESCRIPTION
BLOCK DIAGRAM
IEEE802.3 Clause 9 and IEEE802.3u Cluse 27
compliant.
Provide 8 RMII (Reduced Media Independent
Interface) ports.
Provide 2 inter_repeater stacking bus for 10M
and 100M port expansion each.
Support stacking to 4 units without any external
arbitration logic ( if use external arbitration
logic, theoretically can stack to 6 units and up) .
Build_in 2 port switch controller, support up to
2048 MAC addresses filtering database.
Optional back_pressure flow control
Optional up_link_switch port function (in slave
hub), support 100FX 2km distance extension in
100FD mode.
Meet Class_2 repeater specification for
100M_hub.
Use simple and low cost asynchronous SRAM
(high speed ASRAM 128k*8 : one pcs only)
128 pin PQFP package, 5V operation voltage.
8 Port 10M/100M Hub With 2 port Switch
The MTD658 is a highly integrated, 10M/
100M dual speed hub with build_in 2 port switch.
Support 8 RMII ports for 10M/100M operation,
and really meet 100M_hub class_2 spec when
connect with external QPHYceivers.
The MTD658 provides two Inter-repeater
stacking bus for 10M and 100M expansion each,
easily stack to 4 units without any external arbi-
tration logic. If using external arbitration logic and
proper bus driver, can stack to 6 units and up.
The build_in 2 port switch, support 2k MAC
addresses filtering, and use low cost asynchro-
nous high speed SRAM (128k*8) one pcs only for
packet buffering. This 2 port switch can also be
configured to be up_link switch when hub is
under slave mode.
The MTD658 also support an simple and
effective LED display function, provide 10M_col,
100M_col, memory_test_fail, and per port's parti-
tion status.
ASRAM Interface
RMII7
RMII6
RMII5
RMII4
RMII3
RMII2
RMII1
RMII0
10M
Hub
100M
Hub
Two Port
Switch
Uplink Switch Enable(10/100,FD/HD)
10M_HD
100M_HD
Port
Switch
Logic
10M
Inter Hub Bus
100M
Inter Hub Bus
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
2/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
SYSTEM DIAGRAM
MTD658
MTD658
QUAD
PHYsceiver
QUAD
PHYsceiver
ASRAM
(128kx8)
10M
Inter Hub Bus
100M
Inter Hub Bus
10M
Inter Hub Bus
100M
Inter Hub Bus
MTD658
MTD658
10M
Inter Hub Bus
100M
Inter Hub Bus
10M
Inter Hub Bus
100M
Inter Hub Bus
RMII0-3
RMII4-7
DB25 Connector
QUAD
Transformer
QUAD
Transformer
RJ45
RJ45
3/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
1
0
2
1
0
1
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
A
1
1
A
5
A
9
A
6
A
8
A
7
A
1
3
A
1
2
W
E
B
A
1
4
G
N
D
A
1
5
A
1
6
I
R
E
Q
1
0
_
O
U
T
I
R
E
Q
1
0
_
I
N
0
I
R
E
Q
1
0
_
I
N
1
I
R
E
Q
1
0
_
I
N
2
I
C
O
L
B
1
0
I
A
C
K
B
1
0
I
C
L
K
1
0
G
N
D
I
D
A
T
1
0
I
R
E
Q
1
0
0
_
O
U
T
I
R
E
Q
1
0
0
_
I
N
0
I
R
E
Q
1
0
0
_
I
N
1
I
R
E
Q
1
0
0
_
I
N
2
I
C
O
L
B
1
0
0
I
A
C
K
B
1
0
0
G
N
D
I
C
L
K
1
0
0
V
C
C
I
D
A
T
1
0
0
_
0
I
D
A
T
1
0
0
_
1
I
D
A
T
1
0
0
_
2
I
D
A
T
1
0
0
_
3
I
M
A
S
T
E
R
F
D
7
U
P
S
W
E
N
VCC
A4
GND
OEB
A3
A10
A2
A1
D7
A0
D6
D0
D5
D1
GND
D4
D2
D3
VCC
SYSCLK
GND
LEDDAT
LEDCLK
MDC
MDIO
RSTB
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
C
R
S
D
V
0
T
X
D
0
_
1
V
C
C
T
X
D
0
_
0
T
X
E
N
0
R
X
D
0
_
0
R
X
D
0
_
1
C
R
S
D
V
1
T
X
D
1
_
1
T
X
D
1
_
0
T
X
E
N
1
R
X
D
1
_
0
R
X
D
1
_
1
G
N
D
C
R
S
D
V
2
T
X
D
2
_
1
T
X
D
2
_
0
T
X
E
N
2
R
X
D
2
_
0
R
X
D
2
_
1
C
R
S
D
V
3
T
X
D
3
_
1
T
X
D
3
_
0
T
X
E
N
3
R
X
D
3
_
0
R
X
D
3
_
1
S
P
D
3
S
P
D
2
S
P
D
1
S
P
D
0
V
C
C
G
N
D
C
R
S
D
V
4
T
X
D
4
_
1
T
X
D
4
_
0
T
X
E
N
4
R
X
D
4
_
0
R
X
D
4
_
1
MTD658
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
SPD4
SPD5
SPD6
SPD7
GND
VCC
RXD7_1
RXD7_0
TXEN7
TXD7_0
TXD7_1
CRSDV7
RXD6_1
RXD6_0
TXEN6
TXD6_0
TXD6_1
CRSDV6
GND
VCC
RXD5_1
RXD5_0
TXEN5
TXD5_0
TXD5_1
CRSDV5
4/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
2.0 PIN DESCRIPTIONS
RMII Port Interface Pins
Name
Pin Number
I/O
Descriptions
CRSDV0
1
I
Port0 RMII receive interface signal, CRSDV0 is asserted high when
port0 media is non_idle.
RXD0_0
RXD0_1
6
7
I
I
Port0 RMII receive data bit_0.
Port0 RMII receive data bit_1.
TXEN0
5
O
Port0 RMII transmit enable signal.
TXD0_0
TXD0_1
4
2
O
O
Port0 RMII transmit data bit_0.
Port0 RMII transmit data bit_1.
CRSDV1
8
I
Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
RXD1_0
RXD1_1
12
13
I
I
Port1 RMII receive data bit_0.
Port1 RMII receive data bit_1.
TXEN1
11
O
Port1 RMII transmit enable signal.
TXD1_0
TXD1_1
10
9
O
O
Port1 RMII transmit data bit_0.
Port1 RMII transmit data bit_1.
CRSDV2
15
I
Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
RXD2_0
RXD2_1
19
20
I
I
Port2 RMII receive data bit_0.
Port2 RMII receive data bit_1.
TXEN2
18
O
Port2 RMII transmit enable signal.
TXD2_0
TXD2_1
17
16
O
O
Port2 RMII transmit data bit_0.
Port2 RMII transmit data bit_1.
CRSDV3
21
I
Port3 RMII receive interface signal, CRSDV3 is asserted high when
port3 media is non_idle.
RXD3_0
RXD3_1
25
26
I
I
Port3 RMII receive data bit_0.
Port3 RMII receive data bit_1.
TXEN3
24
O
Port3 RMII transmit enable signal.
TXD3_0
TXD3_1
23
22
O
O
Port3 RMII transmit data bit_0.
Port3 RMII transmit data bit_1.
CRSDV4
33
I
Port4 MII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
RXD4_0
RXD4_1
37
38
I
I
Port4 RMII receive data bit_0.
Port4 RMII receive data bit_1.
TXEN4
36
O
Port4 RMII transmit enable signal.
TXD4_0
TXD4_1
35
34
O
O
Port4 RMII transmit data bit_0.
Port4 RMII transmit data bit_1.
CRSDV5
39
I
Port5 RMII receive interface signal, CRSDV5 is asserted high when
port5 media is non_idle.
RXD5_0
RXD5_1
43
44
I
I
Port5 RMII receive data bit_0.
Port5 RMII receive data bit_1.
TXEN5
42
O
Port5 RMII transmit enable signal.
TXD5_0
TXD5_1
41
40
O
O
Port5 RMII transmit data bit_0.
Port5 RMII transmit data bit_1.
5/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
Note: Asynchronous SRAM acess time: 10/12 ns (max)
CRSDV6
47
I
Port6 RMII receive interface signal, CRSDV6 is asserted high when
port6 media is non_idle.
RXD6_0
RXD6_1
51
52
I
I
Port6 RMII receive data bit_0.
Port6 RMII receive data bit_1.
TXEN6
50
O
Port6 RMII transmit enable signal.
TXD6_0
TXD6_1
49
48
O
O
Port6 RMII transmit data bit_0.
Port6 RMII transmit data bit_1.
CRSDV7
53
I
Port7 RMII receive interface signal, CRSDV7 is asserted high when
port7 media is non_idle.
RXD7_0
RXD7_1
57
58
I
I
Port7 RMII receive data bit_0.
Port7 RMII receive data bit_1.
TXEN7
56
O
Port7 RMII transmit enable signal.
TXD7_0
TXD7_1
55
54
O
O
Port7 RMII transmit data bit_0.
Port7 RMII transmit data bit_1.
High Speed Asynchronous SRAM Interface Pins
Name
Pin Number
I/O
Descriptions
WEB
94
O
ASRAM control pin for write (low active).
OEB
106
O
ASRAM control pin for read (low active).
D[7:0]
111,113,115,
118,120,119,
116,114
I/O ASRAM data bus
A[16:0]
90,91,93,96,
95,102,108,
100,98,97,99
,101,104,107
,109,110,112
O
ASRAM address bus
RMII Port Interface Pins
Name
Pin Number
I/O
Descriptions
6/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
10M Inter-Bus Interface pins
Name
Pin Number
I/O
Descriptions
IMASTER
67
I
Master hub selection:
when high: means hub internal inter_bus arbiter is enabled and hub
internal two_port switch is well conneted to 10M_hub core and
100M_hub core .
when low: means hub internal inter_bus arbiter is disabled and hub
internal two_port switch is not connected to 10M_hub core and
100M_hub core.
IACKB10
84
I/O 10M Inter-Bus port access acknowledge signal (low active). For master
hub, this pin is output; for slave hub is input, or while EXT_ARB
jumper was set to "1", this pin is input from an external arbitration
device.
ICOLB10
85
I/O 10M Inter-Bus collision signal (low active). For master hub, this pin can
output multi hub collision event to inform all slave hub ; for slave hub,
this pin is an input, or while EXT_ARB jumper was set to "1", this pin
is input from an external arbitration device.
IREQ10_IN0
88
I
10M Inter-Bus port access request input.
IREQ10_IN1
87
I
10M Inter-Bus port access request input.
IREQ10_IN2
86
I
10M Inter-Bus port access request input.
IREQ10_OUT
89
O
10M Inter-Bus port access request output.
ICLK10
83
I/O 10M Inter-Bus port clock.
IDAT10
81
I/O 10M Inter-Bus port data bit
100M Inter-Bus Interface pins
Name
Pin Number
I/O
Descriptions
IACKB100
75
I/O 100M Inter-Bus port access acknowledge signal (low active). For master
hub, this pin is output; for slave hub is input, or while EXT_ARB
jumper was set to "1", this pin is input from an external arbitration
device.
ICOLB100
76
I/O 100M Inter-Bus collision signal (low active). For master hub, this pin
can output multi hub collision event to inform all slave hub ; for slave
hub, this pin is an input, or while EXT_ARB jumper was set to "1", this
pin is input from an external arbitration device.
IREQ100_IN0
79
I
100M Inter-Bus port access request input.
IREQ100_IN1
78
I
100M Inter-Bus port access request input.
IREQ100_IN2
77
I
100M Inter-Bus port access request input.
IREQ100_OUT
80
O
100M Inter-Bus port access request output.
ICLK100
73
I/O 100M Inter-Bus port clock.
IDAT100_0
71
I/O 100M Inter-Bus port data bit 0.
IDAT100_1
70
I/O 100M Inter-Bus port data bit 1.
IDAT100_2
69
I/O 100M Inter-Bus port data bit 2.
IDAT100_3
68
I/O 100M Inter-Bus port data bit 3.
7/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
LED Interface Pins
Name
Pin Number
I/O
Descriptions
LEDDAT
124
I/O
LED display serial data out; mapping for LEDCLK signal's burst clock
, its serial out data sequence is : ( first bit be shifted out is from b00, and
end of burst bit is b23)
b00: port0 partition b08: 10hub_col b16: port0 rx_activity
b01: port1 partition b09: 100hub_col b17: port1 rx_activity
b02: port2 partition b10: asram_test_fail b18: port2 rx_activity
b03: port3 partition b11: port3 partition b19: port3 rx_activity
b04: port4 partition b12: port4 partition b20: port4 rx_activity
b05: port5 partition b13: port5 partition b21: port5 rx_activity
b06: port6 partition b14: port6 partition b22: port6 rx_activity
b07: port7 partition b15: port7 partition b23: port7 rx_activity
LEDCLK
125
I/O
LED display clock signal, the signal is a discontinued clock for LED
data serial shift out. Every clock burst have 24 cycles ( period : 160 ns),
and the clock burst will be repeated with every 42ms.
Miscellaneous Pins
Name
Pin Number
I/O
Descriptions
RSTB
128
I
System reset input, low active.
SYSCLK
122
I
50MHz system clock input
MDC
126
I/O MII management clock inout
MDIO
127
I/O MII management data inout
UPSWEN
65
I
Up_link switch port enabling : one of internal two_port switch port will
connect to 100M_hub domain, and another port will redirect to RMII
port7.
FD7
66
I
When up_link switch port enabling, this pin is port7's full_deplex indi-
cator, input from PHY. When hign , indicate port7 in running on
full_duplex mode. When low, indicate on half_duplex mode.
SPD0
30
I
Port0 speed indicator, input from PHY.
SPD0 input low: 100M , input high: 10M.
SPD1
29
I
Port1 speed indicator, input from PHY.
SPD1 input low: 100M , input high: 10M.
SPD2
28
I
Port2 speed indicator, input from PHY.
SPD2 input low: 100M , input high: 10M.
SPD3
27
I
Port3 speed indicator, input from PHY.
SPD3 input low: 100M , input high: 10M.
SPD4
64
I
Port4 speed indicator, input from PHY.
SPD4 input low: 100M , input high: 10M.
SPD5
63
I
Port5 speed indicator, input from PHY.
SPD5 input low: 100M , input high: 10M.
8/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
SPD6
62
I
Port6 speed indicator, input from PHY.
SPD6 input low: 100M , input high: 10M.
SPD7
61
I
Port7 speed indicator, input from PHY.
SPD7 input low: 100M , input high: 10M.
VCC
3,31,45,59,
72,103,121
PWR Power pins
GND
14,32,46,60,
74,82,92,105
,117,123
GND Ground pins
Power On Configuration Set Up Table
Name
Pin Number
I/O
Descriptions
TXEN2
18
I/O Back_pressure disable : ( power on external jumper configuration )
- external pull_low (default ) : normal mode (back_pressure enbale)
- external pull_high: back_pressure disable
TXEN5
42
I/O Auto MII_setting bypass : ( power on external jumper configuration )
- external pull_low (default ) : normal mode ( auto MII_setting); after
power_on, MTD658 will auto setup PHY devices be forced in half_
duplex mode for repeater apllication.
- external pull_high: auto MII_setting bypass
MDC
126
I/O 1522 bytes packet accept enable : ( power on external jumper configura-
tion )
- external pull_low (default ) : normal mode ( <=1518 bytes packet
accept)
- external pull_high: <= 1522 bytes packet accept
LEDDAT
124
I/O External arbiter enable : ( power on external jumper configuration )
- external pull_low (default ) : normal mode (inter_repeater bus use
internal arbiter)
- external pull_high: inter_repeater bus use external arbiter .
Miscellaneous Pins
Name
Pin Number
I/O
Descriptions
9/17
MTD658 Revision 1.0 22/06/99
MTD658
(Preliminary)
MYSON
TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTIONS
The MTD658 is conformed to IEEE802.3 chapter 9 and IEEE802.3u clause 27 specifications. The
MTD658 provides 8 Redused MII interfaces and an embedded two port switch to construct a 10M/
100M dual speed Hub application. Two Inter-Bus are also provided for stackable 10M/100M dual speed
Hub application. The MTD658 functions are described as follows:
3.1 Repeat and data handling
8 independent RMII ports integrated with IEEE802.3 chapter 9 and IEEE802.3u clause 27 repeater
functions simultaneously. MTD658 embedded two Hub cores (10M and 100M) ,and each dedicated
RMII interface port can get per port's speed information from per port speed input pin, and then
MTD658 will switch individual port to their appropriated Hub core functions (10M or 100M).
The MTD658 receive packets from each RMII ports, and redirect port's input packet to 10M or 100M
Hub core according each port's speed. The internal IEEE802.3 chapter 9 or IEEE802.3u clause 27
repeater main state machine will starts to repeat the input packet to all ports except the input port. If
larger than or equal to two ports have input packet simultaneously, this will be treated as a collision,
and MTD658 will assert an arbitrary JAM pattern to all ports' output until collision event disappear and
network is idle.
3.2 Partition
The MTD658 provides 10M/100M auto partition/reconnection functions to guarantee the network seg-
ment performance by means of dectecting a consecutive collisions. Each dedicated RMII port has
implement a individual 10M/100M auto partition/reconnection state machine. If port's consecutive colli-
sion number over or equal to CClimit (10M CClimit default is 32, 100M CClimit default is 64), this port
will be partitioned. Reconnection will occurs after a larger than 512 bit time packet was received or
transmitted from this partitioned port without any collision.
When port is under partition state, MTD658 will not accept any input messages from this port (just mon-
itor input message), but will continue output repeated messages to this partition port.
Some new partition criterions are also implement, such as long_collision_partition event,
jabber_partition event. In 10M/100M partition state machine, longer than 1024 bit time continueous col-
lision will force port enter partition state. In 100M partition state machine, if port enter jabber_on state,
this port will be partitioned. In 10M, jabber_partition function is not implemented.
3.3 Jabber
The jabber protect function is used to prevent an illegally long packet reception. After the MTD658
received a longer than 65536 +/- 6.25% bit times packet, this receive port`s receive/transmit path will be
inhibited until carrier is no longer detected.
3.4 MII Setting
Due to HUB is an half duplex device, the MTD658 need to force all connected phsical devices to work
in half duplex environment. The MTD658 will setting all PHY's SMI register 4's half/full duplex bit during
power on, and than restart auto-negotiation procedure to work in half duplex mode, and the PHY's
device ID should be set by PCB maker from 5'h04 - 5'h0b(port0-7).
3.5 Inter-Bus Interface
Two Inter-Bus Interface are provided by the MTD658, One is 10M Inter-Bus Interface, the other is 100M
Inter-Bus Interface. The Inter-Bus interface is designed for stackable hub application. For each domain,
up to 4 MTD658s can be stacked through this Inter-Bus without any external arbitration logic. The Inter-
Bus Interface includes IMASTER, IDATA (100M: use IDAT<3:0>, 10M: use only IDAT), REQOUT,
REQIN0-2, ICLK, IACKB, ICOLB pins. IMASTER decide which MTD658 can arbitrate the Inter-Bus,
and only one MTD658's IMASTER can be tie high in a stackable Hub. IDATA are synchronous with
ICLK. The MTD658 output REQOUT to inform Inter-Bus Interface that it need the Inter-Bus right. When
IACKB is asserted by Inter-Bus master after REQOUT asserted, the MTD658 which asserted
REQOUT will get the bus right and put the transmit data into IDATA. If the MTD658 did not assert
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REQOUT , but IACKB is asserted, means this MTD658 can get data from IDATA bus. When only one
MTD658 output REQOUT to Inter-Bus Interface, IACKB will be asserted by Inter-Bus master device, If
larger than two MTD658's REQOUT were asserted, Inter-Bus master will not assert IACKB , but will
assert ICOLB to inform all the connected MTD658s.
The Inter-Bus interface can also be programmed to EXT_ARB mode, using LEDDAT pin's jumper set-
ting. In this mode, Inter-Bus interface need an external arbitration logic to arbitrate Inter-Bus operation.
And in this mode, the stackable capability is not limitted by the MTD658's REQIN pins number.
3.6 10M/100M packet Switch
The MTD658 inplements a 10/100M two port switch for 10M/100M packet switching. Total 2K address
entrys are provided for packets' SA learning and DA routing; and alsoprovide automatic aging function
( aging time = 300secs). The input packet from 10MHub ( or 100M Hub) will be stored to external
memory first, while packet is good for forward ( CRC chech ok, 64Bytes < length > 1518Bytes, and not
local packets ) , than forward this packet to 100M Hub (or 10M Hub).
3.7 Uplink Switch Port
The MTD658 can config one switch port as an uplink switch port. When UPSWEN pin is high, and
IMASTER pin is low, one of the intenal switch port is connect to 100M HUB, the other is connected to
RMII port 7. In uplink switch mode, port 7 can work in 10M/100M(from SPEED7 pin), half/full
duplex(from P7FULL pin) mode.
3.8 Memory Interface
The MTD658 use asynchronous SRAM as two port switchs' packet buffers, total has 128K byte exter-
nal memory for packet buffering.
3.9 MII management
The MTD658 can be managed through MDC, MDIO pins. The MTD658 implements
3
MII registers for
function control and status report (see Section 4.0 on page ).
The management frame format is compliant to IEEE802.3u clause 22, and the device ID is fixed to
5'h1f internally.
3.10 LED display
The MTD658 implements three display modes, port RX activity, 10/100M domain collision, port parti-
tion. The LED data pin LEDDAT is high actived.
One strobe pin LEDCLK(24 burst clock/per 42ms) is used to latch serial LEDDAT information, and user
can shift the latched data into byte aligned shift register to drive LEDs.
4.0 Registers
The MTD658 implements
3
MII registers, define as following tables:
TABLE 1. MII registers
REG
NO
Bits
Name
R/W
Descriptions
Default
0
CtlReg0
R/W
CONTROL REGISTER 0
0
Reserved.
1'b0
1
DisPar10
Set this bit will disable 10M hub core partition function.
1'b0
2
DisPar100
Set this bit will disable 100M hub core partition function.
1'b0
3
DisJab10
Set this bit will disable 10M hub core Jabber function.
1'b0
4
DisJab100
Set this bit will disable 100M hub core Jabber function.
1'b0
5-8
Reserved
4'b000
9
CClimit100
Set "1" will program 100M partition cclimit to 128.
1'b0(64)
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"R/W" means read/writable.
10
CClimit10
Set "1" will program 10M partition cclimit to 64.
1'b0(32)
11-15
Reserved
2'b00
1
CtlReg1
R/W
CONTROL REGISTER 1
16'h0000
0-7
DisPort
Set bits "1" disable port 0-7 RMII ports.
8'h000
8-15
Reserved.
2
Reserved
3
Reserved
4
AgeReg
R/W
AGE REGISTER
TABLE 1. MII registers
REG
NO
Bits
Name
R/W
Descriptions
Default
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5.0 Electrical Characteristics
5.1 Absolute Maximum Ratings
5.2 Recommended Operating Conditions
5.3 DC Electrical Characteristics
(Under recommended operating conditions and Vcc = 4.75 ~ 5.25V, Tj = 0 to +115
o
C)
Symbol
Parameter
RATING
Unit
V
CC
Power Supply Voltage
-0.3 to 6.0
V
V
IN
Input Voltage
-0.3 to Vcc+0.3
V
V
OUT
Output Voltage
-0.3 to Vcc+0.3
V
T
STG
Storage Temperature
-55 to 150
C
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Commercial Power Supply Voltage
4.75
5
5.25
V
Industrial Power Supply Voltage
4.5
5
5.5
V
V
IN
Input Voltage
0
-
Vcc
V
T
OPR
Commercial Junction Operating Temperature
0
25
115
C
Industrial Junction Operating Temperature
-40
25
125
C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
IL
Input Leakage Current
no pull-up or down
-1
1
uA
I
OZ
Tri-state Leakage Current
-10
10
uA
C
IN
Input Capacitance
3
pF
C
OUT
Output Capacitance
3
pF
C
BID3
Bi-direction buffer Capacitance
3
pF
V
IL
Input Low Voltage
CMOS
0.3*Vcc
V
V
IH
Input High Voltage
CMOS
0.7*Vcc
V
V
OH
Output High Voltage
I
OL
=2,4,8,12,16,24mA
0.4
V
V
OL
Output Low Voltage
I
OH
=2,4,8,12,16,24mA
3.5
V
R
I
Input Pull-up/down resistance
V
IL
=0V or V
IH
=V
CC
50
KOhm
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5.4 Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T1
RMII input setup time
1
nS
T2
RMII input hold time
1
nS
T3
RMII output setup time
3
nS
T4
RMII output hold time
5
nS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T5
WEB pulse width
11.5
16
nS
T6
OEB pulse width
20
nS
T7
Write Address setup time
10
18.5
nS
T8
Write Address hold time
1.5
7
nS
T9
Write Data setup time
10
12
nS
T10
Write Data hold time
1
4
nS
T11
Read Address setup time
19.5
nS
T12
Read Address hold time
0
nS
FIGURE 1. RMII timing
REFCLK
CRSDV
TXEN
TXD[1:0]
RXD[1:0]
T1
T2
T3
T4
Valid
Valid
FIGURE 2. Memory Interface Timing
WEB
A[16:0]
T9
T5
T7
T8
Valid
OEB
T6
Valid
D[7:0]
Valid
Valid
T10
T11
T12
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Note 1 : In 10M/100M Inter-Bus interface, T15-T18 have the same value.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T13
Inter-Bus output setup time(100M)
15
20
nS
Inter-Bus output setup time(10M)
50
nS
T14
Inter-Bus output hold time(100M)
20
25
nS
Inter-Bus output hold time(10M)
50
nS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T15
Inter-Bus master REQOUT asserted
to IACKB asserted propogation delay
7
20
nS
1
T16
Inter-Bus master REQOUT deas-
serted to IACKB deasserted propo-
gation delay
0
1
5
nS
1
T17
Inter-Bus master REQIN asserted to
IACKB deasserted(ICOLB asserted)
propogation delay(SOJ)
5
17
nS
1
T18
Inter-Bus master REQOUT deas-
serted to IACKB asserted(ICOLBde-
asserted) propogation delay(EOJ)
0
1
5
nS
1
FIGURE 3. Inter-Bus Interface timing I
ICLK100,
T13
T14
IDATA100,
Valid
IDAT10
ICLK10
FIGURE 4. Inter-Bus Interface timing II
IMASTER
REQOUT100,
REQIN100,
IACKB100,
ICOLB100,
T15
T17
T16
T18
REQOUT10
REQIN10
IACKB10
ICOLB10
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Note 2 : In 10M/100M Inter-Bus interface, T19-T22 have the same value.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T19
Inter-Bus slave REQOUT asserted to
IACKB asserted propogation delay
5
20
nS
2
T20
Inter-Bus slave REQOUT deasserted
to IACKB deasserted propogation
delay
5
20
nS
2
T21
Inter-Bus slave REQIN asserted to
IACKB deasserted(ICOLB asserted)
propogation delay(SOJ)
5
20
nS
2
T22
Inter-Bus slave REQOUT deasserted
to IACKB asserted(ICOLBdeas-
serted) propogation delay(EOJ)
5
20
nS
2
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T23
MDC clock cycle
400
nS
T23
MDIO input setup time
10
nS
FIGURE 5. Inter-Bus Interface timing III
IMASTER
REQOUT100,
REQIN100,
IACKB100,
ICOLB100,
T19
T21
T20
T22
REQOUT10
REQIN10
IACKB10
ICOLB10
FIGURE 6. MII Management timing
MDC
T24
T25
MDIO
Valid
MDC
T26
T27
MDIO
Valid
T23
Input Timing
Output Timing
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T25
MDIO input hold time
10
nS
T26
MDIO output setup time
182
194
nS
T27
MDIO output hold time
206
218
nS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
T28
24 LED burst clocks duration
3.84
uS
T29
LED burst clock cycle time
42
mS
T30
LED burst clock cycle
160
nS
T31
LEDDAT to LEDCLK setup time
80
nS
T32
LEDDAT to LEDCLK setup time
80
nS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
FIGURE 7. LED output timing
LEDCLK
LEDDAT
....
....
LEDCLK
T28
T29
T30
T31
T32
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6.0 128 pin PQFP Package Data
103
128
1
38
39
64
65
102
Seating Plane
See Detail A
A
A
1
A
2
e
B
D
1
D
E
1
E
L
L1
z
Detail A
Note:
1.Dimension D1 & E1 do not include mold protrusion.
But mold mismatch is included. Allowable protrusion is .25mm/.010" per side.
2.Dimension B does not include dambar protrusion. Allowable dambar protru-
sion .08mm/.003". Total in excess of the B dimemsion at maximum material
condition. Dambar cannot be located on the lower radius or the foot.
3.Controlling dimension : Millimeter.
Symbol
Dimension in inch
Dimension in mm
Min
Norm
Max
Min
Norm
Max
A
-
-
0.134
-
-
3.40
A1
0.010
-
-
0.25
-
-
A2
0.107 0.112 0.117
2.73
2.85
2.97
B
0.007 0.009 0.011
0.17
0.22
0.27
C
0.004
-
0.008
0.09
-
0.20
D
0.906 0.913 0.921 23.00 23.20 23.40
D
1
0.783 0.787 0.791 19.90 20.00 20.10
E
0.669 0.677 0.685 17.00 17.20 17.40
E
1
0.547 0.551 0.555 13.90 14.00 14.10
e
0.020 BSC
0.50 BSC
L
0.029 0.035 0.041
0.73
0.88
1.03
L1
0.063 BSC
1.60 BSC
y
-
-
0.004
-
-
0.10
z
0
o
-
7
o
0
o
-
7
o
y
See Detail B
Detail B
C
B
With Plating
Base Metal
Gage Plane
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