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CS5865
Preliminary
GENERAL DESCRIPTION
FEATURES
Sales@myson.com.tw
www.myson.com.tw
Rev.0.92 July 2003
page 1 of 43
Myson Century, Inc.
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
TFT Source Driver with Timing Controller (362 Outputs)
Tailored for small-sized panel color TFT LCD
driver with timing controller
Output : 360 (+2) output channels
6-bit resolution 64 gray scale
Data latch edge selectable
Power for LCD driving : 4.5 ~ 5.5V
Power for digital interface : 2.5 ~ 3.6V
Power for level shift circuit : 4.0 ~ 6.0 V
Operating frequency : DC ~ 10MHz
Output dynamic range : 0.1V ~ AVDD-0.1V
Output deviation : 20mV
Output settling time : 15~30us
Cascade function with bi-directional shift control
With DC to DC control circuit for LCD power and
LED FLU (excluding AGB mode)
With level shift circuit for Vcom swing
V0~ V6 for adjusting Gamma correction
COG package
Line inversion
With standby-mode
Resolution support: 160x160x100Hz up to
480x480x40Hz (for DE mode)
The CS5865 is a source driver IC with timing
controller for small-sized color TFT LCD panels. It
provides selectable 360 or 240 output channels for
application. The circuit architecture with a special
method is designed to lower power dissipation. For
better performance, a small output deviation is
designed in the CS5865.
The CS5865 also provides 7 sections of voltage-
reference of gamma correction and the power
dissipation on the gamma correction resistors is also
concerned, thereby making the CS5865 more
suitable for small-size color TFT panels.
*This datasheet, which contains proprietary and trade secret information of MYSON CENTURY, INC., is confidential and
subject to various privileges against unauthorized disclosure.
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BLOCK DIAGRAM
page 2 of 43
CS5865
Preliminary
6
6
6
6
6
6
YX1' YX1 YY1 YZ1 ................... YY120 YZ120 YZ120'
..............................
..............................
.......................
1 ................................... 120
INV
Dx5-Dx0;x:X,Y,Z
DCLK
LD (LP)
POL (REV)
SP
Hsync
Vsync (SPS)
DCLK
ENAB
HTEST0
HTEST1
HTEST2
VTEST0
VTEST1
VTEST2
MODE
PS0
RES
FDCLK
CLS
MOD
RST
STB
UD
LR
CHSEL
DRVDEL
MODESEL
XDOFF
UD
FG
STVU
STVD
STHR
STHL
DIO1
DIO2
SHUD
ENCOM
SHUD
STB
POL
ENCOM
DVCC
(3.3V)
DGND
(0V)
AVDD
(3.3V)
AGND
(0V)
AVDD1
AGND1
(ADJ)
FB
DRV
AVDD2
AGND2
COMO
DIO2
DIO1
SP
POL
LD
INV
DATA
DCLK
LR
STB
SP
POL
V0 -V6
VCDC
DIS
LD
7
18
Timing Signal
Generator
CRTL Interface
Shift Register (120-bit)
Driving Buffer
DAC
Line Latch
(120 x 3ch x 6bits x 2)
DC/DC converter
control circuit
Common
circuit
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