MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
8-Bit Serial-Input/Serial or
Parallel-Output Shift Register
with Latched 3-State Outputs
HighPerformance SiliconGate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8bit shift register and an 8bit Dtype latch
with threestate parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
-- Improved Propagation Delays
-- 50% Lower Quiescent Power
-- Improved Input Noise and Latchup Immunity
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SQH
A
VCC = PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
MC54/74HC595A
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
QA
VCC
SQH
RESET
SHIFT CLOCK
QE
QD
QC
QB
GND
QH
QG
QF
D SUFFIX
SOIC PACKAGE
CASE 751B05
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F01
J SUFFIX
CERAMIC PACKAGE
CASE 62010
1
16
MC54/74HC595A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
35
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage
(Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage, QA QH
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
6.0 mA
|Iout|
v
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum LowLevel Output
Voltage, QA QH
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
6.0 mA
|Iout|
v
7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC595A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS
(Continued)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VOH
Minimum HighLevel Output
Voltage, SQH
Vin = VIH or VIL
IIoutI
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL IIoutI
v
4.0 mA
IIoutI
v
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum LowLevel Output
Voltage, SQH
Vin = VIH or VIL
IIoutI
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL IIoutI
v
4.0 mA
IIoutI
v
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum ThreeState Leakage
Current, QA QH
Output in HighImpedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
0.5
5.0
10
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
lout = 0
A
6.0
4.0
40
160
A
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPHL
Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA QH
(Figures 3 and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA QH
(Figures 4 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA QH
(Figures 4 and 8)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
tTLH,
tTHL
Maximum Output Transition Time, QA QH
(Figures 3 and 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance (Output in
HighImpedance State), QA QH
--
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Package)*
300
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
MC54/74HC595A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
4
TIMING REQUIREMENTS
(Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
25
_
C to
55
_
C
v
85
_
C
v
125
_
C
Unit
tsu
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
FUNCTION TABLE
Operation
Inputs
Resulting Function
Operation
Reset
Serial
Input
A
Shift
Clock
Latch
Clock
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQH
Parallel
Outputs
QA QH
Reset shift register
L
X
X
L, H,
L
L
U
L
U
Shift data into shift
register
H
D
L, H,
L
D
SRA;
SRN
SRN+1
U
SRG
SRH
U
Shift register remains
unchanged
H
X
L, H,
L, H,
L
U
U
U
U
Transfer shift register
contents to latch register
H
X
L, H,
L
U
SRN
LRN
U
SRN
Latch register remains
unchanged
X
X
X
L, H,
L
*
U
*
U
Enable parallel outputs
X
X
X
X
L
*
**
*
Enabled
Force outputs into high
impedance state
X
X
X
X
H
*
**
*
Z
SR = shift register contents
D = data (L, H) logic level
X = don't care
* = depends on Reset and Shift Clock inputs
LR = latch register contents
U = remains unchanged
Z = high impedance
** = depends on Latch Clock input
MC54/74HC595A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
5
MOTOROLA
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low tohigh transition on this
input causes the data at the Serial Input pin to be shifted into
the 8bit shift register.
Reset (Pin 10)
Activelow, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A lowtohigh transition on this
input latches the shift register data.
Output Enable (Pin 13)
Activelow Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QAQH) into the high
impedance state. The serial output is not affected by this
control unit.
OUTPUTS
QA QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3state, latch outputs.
SQH (Pin 9)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8bit shift register. This output does not
have threestate capability.
MC54/74HC595A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
6
SWITCHING WAVEFORMS
SERIAL
INPUT A
50%
50%
LATCH
CLOCK
VCC
GND
VALID
tsu
th
Figure 5.
SHIFT
CLOCK
OUTPUT
SQH
tr
tf
VCC
GND
90%
50%
10%
90%
50%
10%
tPLH
tPHL
tTLH
tTHL
tw
1/fmax
RESET
OUTPUT
SQH
SHIFT
CLOCK
tw
50%
50%
50%
VCC
GND
VCC
GND
tPHL
trec
tsu
50%
50%
VCC
GND
LATCH
CLOCK
QAQH
OUTPUTS
50%
tPLH
tPHL
tTLH
tTHL
90%
50%
10%
VCC
GND
VCC
GND
SHIFT
CLOCK
LATCH
CLOCK
Figure 3.
VCC
GND
tw
Figure 1.
Figure 2.
Figure 4.
Figure 6.
OUTPUT Q
OUTPUT Q
50%
50%
90%
10%
tPZL
tPLZ
tPZH
tPHZ
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
OUTPUT
ENABLE
50%
TEST CIRCUITS
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 k
Figure 7.
Figure 8.
MC54/74HC595A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
7
MOTOROLA
D
R
Q
SRA
D
Q
LRA
D
Q
SRB
D
Q
LRB
R
D
Q
SRC
D
Q
LRC
R
D
Q
SRD
D
Q
LRD
R
D
Q
SRE
D
Q
LRE
R
D
Q
SRF
D
Q
LRF
R
D
Q
SRG
D
Q
LRG
R
D
Q
SRH
D
Q
LRH
R
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
LATCH
CLOCK
SERIAL
DATA
INPUT A
SHIFT
CLOCK
RESET
13
12
14
11
10
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL
DATA
OUTPUT SQH
PARALLEL
DATA
OUTPUTS
MC54/74HC595A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
8
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATA
OUTPUT SQH
NOTE:
implies that the output is in a highimpedance
state.
MC54/74HC595A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
9
MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 62010
ISSUE V
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R
19.05
6.10
--
0.39
1.40
0.21
3.18
19.93
7.49
5.08
0.50
1.65
0.38
4.31
0
0.51
15
1.01
1.27 BSC
2.54 BSC
7.62 BSC
MIN
MIN
MAX
MAX
INCHES
MILLIMETERS
DIM
0.750
0.240
--
0.015
0.055
0.008
0.125
0.785
0.295
0.200
0.020
0.065
0.015
0.170
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
0
0.020
15
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
1
8
9
16
A
B
C
K
N
G
E
F
D
16 PL
T
SEATING
PLANE
M
L
J
16 PL
0.25 (0.010)
T
A
M
S
0.25 (0.010)
T
B
M
S
MIN
MIN
MAX
MAX
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
A
B
1
8
9
16
F
H
G
D
16 PL
S
C
T
SEATING
PLANE
K
J
M
L
T
A
0.25 (0.010)
M
M
0.25 (0.010)
T
B
A
M
S
S
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
9
16
A
B
D
16 PL
K
C
G
T
SEATING
PLANE
R
X 45
M
J
F
P
8 PL
0.25 (0.010)
B
M
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
MC54/74HC595A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
10
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28
0.007
0.011
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE W.
_
_
_
_
SECTION NN
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X
L/2
U
S
U
0.15 (0.006) T
S
U
0.15 (0.006) T
S
U
M
0.10 (0.004)
V
S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
16X REF
K
N
N
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