MC8051M36
36-Mbit: 1Mx36
Symmetric Pipelined Burst SRAM
DS16, Rev 1.2 - 12/18/2001
Preliminary Information
Page 1
2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
M S
YS
O
High Performance
133-200MHz Speed grades
3-1-1-1 Burst Read
3-1-1-1 Burst Write
3-1-1-1-1-1-1-1... pipelined operation
Symmetric Pipeline
No bus turnaround latency allowing 100% bus efficiency
Low Power
Low active power
Ultra low power ZZ standby mode
1.8V 5% Core power supply (V
DD
)
1.8, 2.5 or 3.3V I/O power supply (V
DDQ
)
Compatibility
Individual Byte Write masking
Interleaved and burst address support
Three chip enable inputs
Clock Enable and Suspend
Applications
Ideal for high speed, low power data and tele-
communications applications
______________________________________________
Overview
The MoSys MC8051M36 is a high performance, low power
symmetric pipelined-burst-SRAM (SPSRAM). Fabricated us-
ing an advanced low power, high performance CMOS process
The MoSys MC8051M36 supports SPSRAM operating modes
at maximum burst frequency including indefinite pipelined read
or write (3-1-1-1-1-1-1...)
The MC8051M36 is packaged in a standard 100 lead LQFP.
Lowest Power
The MC8051M36 affords systems dramatic power savings
due to the benefits of its proprietary MoSys technology.
Making it ideal for convection cooled applications, as well as
applications requiring a large amount of SRAM.
Part Number Designation
Example: MC8051M36L-7R5VI
Device Designation: MC8:, Series: 05
Organization: 1M36
Package Type: L=LQFP
Speed: 7R5 133MHz
6
166MHz
5
200MHz
Temp: I = Industrial Temperature
I/O V:
V = 2.5-3.3V
Parameter
Symbol
-7R5
-6
-5
Units
Cycle Time
tKC
7.5
6
5
ns
Access Time
tKQ
4.2
3.5
3.0
ns
Clock to High-Z
tKQHZ
3.8
3.1
2.9
ns
1
DQP3
80
DQP2
10
VSSQ
71
VSSQ
19
DQ26
62
CE
2#
DQ7
39
2
DQ17
79
DQ16
11
VDDQ
70
A6
VDDQ
31
LB
O
#
20
VDDQ
61
VD
D
VDDQ
40
VSS
3
DQ18
78
DQ15
12
DQ23
69
A7
DQ10
DQ9
32
A5
21
VSSQ
60
VSS
VSSQ
41
VD
D
4
VDDQ
77
VDDQ
13
DQ24
68
CE
1#
33
A4
22
DQ27
59
CLK
DQ6
42
5
VSSQ
76
VSSQ
14
VDD
67
CE
2
VSS
34
A3
23
DQ28
58
WE
#
DQ5
43
6
DQ19
75
DQ14
15
VDD
66
BW
4
#
VDD
35
A2
24
DQ29
57
CK
E
#
DQ4
44
A1
0
28
DQ31
53
A1
7
DQ2
48
A1
4
7
DQ20
74
DQ13
16
VDD
65
BW
3
#
VDD
36
A1
25
DQ30
56
OE
#
DQ3
45
A1
1
29
DQ32
52
A8
DQ1
49
A1
5
8
DQ21
73
DQ12
17
VSS
64
BW
2
#
ZZ
37
A0
26
VSSQ
55
AD
V/
L
D
#
VSSQ
46
A1
2
30
DQP4
51
A9
DQP1
50
A1
6
9
DQ22
72
DQ11
18
DQ25
63
BW
1
#
DQ8
38
100
91
82
99
90
81
98
89
97
88
96
87
95
86
94
85
93
84
92
83
27
VDDQ
54
A1
8
VDDQ
47
A1
3
100 Pin LQFP
20 mm x 14 mm body
0.65 mm nominal pin pitch
NC
NC
NC
A1
9
MC8051M36
36-Mbit: 1Mx36
Symmetric Pipelined Burst SRAM
DS16, Rev 1.2 - 12/18/2001
Preliminary Information
Page 2
2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
M S
YS
O
DESELECT
BEGIN
READ
BEGIN
WRITE
BURST
READ
BURST
WRITE
BURST
DS
WRITE
BURST
BURST
READ
DS
DS
WRITE
READ
READ
WRITE
BURST
BURST
READ
WRITE
WRITE
READ
DS
DS
Functional Block Diagram
Command Action
DS DESELECT
READ Begin
READ
WRITE Begin
WRITE
BURST Begin
READ
Begin WRITE
Continue DESELECT
State Diagram
1Mx36 Bit
Memory Array
Control Logic
Mux
Output Register
MODE
A[19:0]
CE1#, CE2, CE2#
WE#
CKE#
ADV/LD#
BW[4:1]#
CLK
OE#
DQ[32:1]
DQP[4:1]
Input Register
Address
Control
D
D
D
Q
Q
Q
Q
D
MC8051M36
36-Mbit: 1Mx36
Symmetric Pipelined Burst SRAM
DS16, Rev 1.2 - 12/18/2001
Preliminary Information
Page 3
2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
M S
YS
O
Command Truth Table
CE1# CE2 CE2# ZZ ADV/
LD#
WE# BWx# OE#
CKE#
CLK Address
Used
Operation
H X X L L X X X L !
None Deselect
X L X L L X X X L !
None Deselect
X X H L L X X X L !
None Deselect
X X X L H X X X L !
None Continue
Deselect
L H L L L H X L L !
External Read
Start
X X X L H X X L L !
Next Read
Burst
L H L L L H X H L !
External Dummy
Read
X X X L H X X H L !
Next Dummy
Read
L H L L L L L X L !
External Write
Start
X X X L H X L X L !
Next Write
Burst
L H L L L L H X L !
None Write
Abort
X
X
X
L
H X H X
L
!
Next Write
Abort
X X X L X X X X H !
Current
Ignore Clock
X X X H X X X X X X None
Sleep
Partial Read/Write Truth Table
WE# BW4# BW3# BW2# BW1#
Operation
H X X X X
READ
L
L
H
H
H
WRITE DQ[32:25] & DQP[4]
L
H
L
H
H
WRITE DQ[24:17] & DQP[3]
L
H
H
L
H
WRITE DQ[16:9] & DQP[2]
L
H
H
H
L
WRITE DQ[8:1] & DQP[1]
L
L
L
L
L
WRITE All DQ & DQP
L H H H H
WRITE
Abort/NOP
Address Burst Sequence Tables
A[1:0] A[1:0] A[1:0] A[1:0]
Linear
Address,
LBO#=L
00 01 10 11
1
st
Address
01 10 11 00
2
nd
Address
10 11 00 01
3
rd
Address
11 00 01 10
4
th
Address
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved
Address,
LBO#=H
00 01 10 11
1
st
Address
01 00 11 10
2
nd
Address
10 11 00 01
3
rd
Address
11 10 01 00
4
th
Address
MC8051M36
36-Mbit: 1Mx36
Symmetric Pipelined Burst SRAM
DS16, Rev 1.2 - 12/18/2001
Preliminary Information
Page 4
2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
M S
YS
O
Pin Description
Pin Number
Symbol
Type
Description
43, 84, 83, 50, 49, 48, 47, 46, 45, 44, 81, 82, 99,
100, 32, 33, 34, 35, 36 ,37
A[19:0] Input
Processor
Addresses
96,95, 94, 93
BW[4:1]#
Input
Processor host bus byte enables
88 WE#
Input
Read/Write
Control
87 CKE#
Input
Clock
Enable
89
CLK
Input
Processor host bus clock
98 CE1#
Input
Chip
enable
97
CE2
Input
Chip enable for depth expansion
92
CE2#
Input
Chip enable for depth expansion
86
OE#
Input
Asynchronous output enable
85
ADV/LD#
Input
Address Advance/Load# control
64
ZZ
Input
Low power sleep mode
31
LBO#
Input
Linear Burst Order
29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9, 8, 7, 6, 3,
2, 79, 78, 75, 74, 73, 72, 69, 68, 63, 62, 59, 58,
57, 56, 53, 52
DQ[32:1]
I/O
Data I/O pins
30, 1, 80, 51
DQP[4:1]
-
Data Parity I/O pins
38, 39, 42
NC
-
unused
14, 15, 16, 41, 65, 66, 91
VDD
1.8 Volts
Power
17, 40, 67, 90
VSS
Ground
Ground
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
1.8, 2.5 or 3.3 Volts I/O Buffer Supply
5, 10, 21, 26, 55, 60, 71, 76
VSSQ
Ground
I/O Buffer Ground
Absolute Maximum Ratings
Symbol Parameter
Min
Max
Units
VDD
Core Supply Voltage
2.5
V
VDDQ
I/O Supply Voltage
VDDQ VDD +1.8,
VDDQ 3.6
V
Vih
Input High Voltage
VDDQ +0.3
V
Vil
Input Low Voltage
VSSQ-0.3
V
Ts Storage
Temperature
-65
150
C
Notes: Max Vih is not to exceed maximum VDDQ
Capacitance
Symbol Parameter
Typ
Max
Units
CI Input
Capacitance
3
4
pF
CIO I/O
Capacitance
4
5
pF
LQFP Thermal Resistance
Symbol Parameter
Typ
Units
JA
Junction to Ambient
45
C/W
JC
Junction to Case
9
C/W
MC8051M36
36-Mbit: 1Mx36
Symmetric Pipelined Burst SRAM
DS16, Rev 1.2 - 12/18/2001
Preliminary Information
Page 5
2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
M S
YS
O
Recommended Operating Conditions, VDDQ=1.8V
Symbol Parameter
Condition
Min
Max
Units
VDD
Supply Voltage
1.8V 5%
1.71
1.89
V
VDDQ
I/O Supply Voltage
1.8V 5%
1.71
1.89
V
Vih
Input High Voltage
1.2
V
DDQ
+ 0.3
V
Vil
Input Low Voltage
-0.3
0.5
V
Voh
Output High Voltage
Ioh = -1 mA
1.5
V
Vol
Output Low Voltage
Iol = 1 mA
0.2
V
Toprc
Commercial Operating Temp.
0
70
C
Topri
Industrial Operating Temp.
-40
85
C
Recommended Operating Conditions, VDDQ=2.5V or 3.3V
Symbol Parameter
Condition
Min
Max
Units
VDD
Supply Voltage
1.8V 5%
1.71
1.89
V
VDDQ
I/O Supply Voltage
2.5V - 5%/+38%
2.375
3.465
V
Vih
Input High Voltage
1.7
V
DDQ
+ 0.3
V
Vil
Input Low Voltage
-0.3
0.7
V
Voh
Output High Voltage
Ioh = -1 mA
2.0
V
Vol
Output Low Voltage
Iol = 1 mA
0.4
V
Toprc
Commercial Operating Temp.
0
70
C
Topri
Industrial Operating Temp.
-40
85
C
Absolute Maximum AC Operating Conditions
Symbol Parameter
Min
Max
Units
Vih
Input High Voltage
-
V
DDQ
+0.5 V
Vil
Input Low Voltage
V
SSQ
0.5
-
V
tOVR
Overshoot/Undershoot Voltage Duration
0.2*tCY
ns
tSET
Overshoot/Undershoot Settling Time
0.8*tCY
ns
Maximum DC Current Requirements
Symbol Condition Current
Units
I
DD
Operating current, device selected; all inputs < Vil or > Vih; cycle time > 7.5ns, VDD= max, 0 pF
load
250 mA
I
DD1
Idle current; ADV/LD#, GW#, BW#s, CKE# and all other inputs > 2.8 volts; cycle time > tKC min,
VDD= max, 0 pF load
50 mA
I
DDZ
Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max
20
mA
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