MOSEL VITELIC
1
V826632K24S
32M x 64 HIGH PERFORMANCE
UNBUFFERED DDR SDRAM MODULE
PRELIMINARY
V826632K24S Rev. 1.2 January 2003
Features
184 Pin Unbuffered 33,554,432 x 64 bit
Organization DDR SDRAM Modules
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V ( 0.2V) Power Supply
Single +2.6V ( 0.1V) Power Supply for DDR400
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Description
The V826632K24S memory module is organized
33,554,432 x 64 bits in a 184 pin memory module.
The 32M x 64 memory module uses 8 Mosel-Vitelic
32M x 8 DDR SDRAM. The x64 modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
Component Used
D3
C0
B1
B0
t
CK
Clock Frequency
(max.)
200
(PC400)
166
(PC333)
143
(PC266A)
133
(PC266B)
t
AC
Clock Cycle Time
CAS Latency = 2.5
6
6
7
7.5
t
AC
Clock Cycle Time
CAS Latency = 3
5
-
-
-
Module Speed
D4
D3
D0
C0
B1
B0
A1
Units
t
CK
Clock Frequency
(max.)
200
(PC400C)
200
(PC400B)
200
(PC400A)
166
(PC333)
143
(PC266A)
133
(PC266B)
125
(PC200)
MHz
t
AC
Clock Cycle Time
CAS Latency = 2
7.5
7.5
7.5
7.5
7.5
10
10
ns
t
AC
Clock Cycle Time
CAS Latency = 2.5
6
6
5
6
7
7.5
8
ns
t
AC
Clock Cycle Time
CAS Latency = 3
5
5
5
-
-
-
-
ns
t
RCD
tRP parameter
4
3
3
3
2
3
2
CLK
t
RP
tRCD parameter
4
3
3
3
2
3
2
CLK
2
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
Part Number Information
V 8 2 66 32 K 2 4 S X T G - XX
DDR SDRAM
2.5V
WIDTH
DEPTH
184 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 8K
4 BANKS
STTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G = GOLD
SPEED
A1 (100MHz@2-2-2)
MOSEL VITELIC
MANUFACTURED
B0 (133MHz@2.5-3-3)
B1 (133MHz@2-2-2)
C0 (166MHz@2.5-3-3)
D3 (200MHz@3-3-3)
D4 (200MHZ@3-4-4)
2.6V for DDR400
D0 (200MHZ@2.5-3-3)
MOSEL VITELIC
V826632K24S
3
V826632K24S Rev.1.2 January 2003
CS0
Serial PD
A0
A1
A2
SA0
SA1
SA2
SCL
BA0-BA1 BA0-BA1 : SDRAMs D0 - D7
A0 - A12 A0 - A12 : SDRAMs D0 - D7
RAS RAS : SDRAMs D0 - D7
CAS CAS : SDRAMs D0 - D7
CKE0 CKE : SDRAMs D0 - D7
WE WE : SDRAMs D0 - D7
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ,DQS, DM/DQS resistors : 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ) :
STRAP OUT (OPEN): VDD=VDDQ
STRAP IN (
V
SS
): VDD VDDQ
Strap: see Note 4
D0
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQS0
DM0
SDA
V
DD
/V
DDQ
V
REF
0.1uF 0.1uF
0.1uF
V
SS
D0 - D7
D0 - D7
D0 - D7
D0 - D7
V
DDID
DM
DQS
D4
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQS4
DM4
DM
DQS
D1
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQS1
DM1
DM
DQS
D5
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQS5
DM5
DM
DQS
D2
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQS2
DM2
DM
DQS
D6
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQS6
DM6
DM
DQS
D3
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQS3
DM3
DM
DQS
D7
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQS7
DM7
DM
DQS
Clock Wiring
Clock Input
SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
3 SDRAMs
2 SDRAMs
3 SDRAMs
Block Diagram
4
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
Pin Configurations (Front Side/Back Side)
Notes:
* These pins are not used in this module.
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Pin Names
Pin Pin
Description
CK1, CK1, CK2, CK2 Differential
Clock
Inputs
CS0
Chip Select Input
CKE0
Clock Enable Input
RAS, CAS, WE Commend
Sets
Inputs
A0 ~ A12
Address
BA0, BA1
Bank Address
DQ0~DQ63 Data
Inputs/Outputs
DQS0~DQS7 Data
Strobe
Inputs/Outputs
DM0~DM7 Data-in
Mask
VDD Power
Supply
Key
Key
VDDQ DQs
Power
Supply
VSS Ground
VREF Reference
Power
Supply
VDDSPD
Power Supply for SPD
SA0~SA2 E
2
PROM Address Inputs
SCL E
2
PROM Clock
SDA E
2
PROM Data I/O
VDDID VDD
Identification
Flag
DU
Do not Use
NC No
Connection
Pin Pin
Description
MOSEL VITELIC
V826632K24S
5
V826632K24S Rev.1.2 January 2003
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ 2-2-2)
B0 (PC2100B @ 2.5-3-3)
B1 (PC2100A @ 2-2-2)
C0 (PC2700 @ 2.5-3-3)
D0 (PC3200 @ 2.5-3-3)
D3 (PC3200 @ 3-3-3)
D4 (PC3200 @ 3-4-4)
Byte
# Function
described
Function Supported
Hex value
A1
B0 B1 C0
D0
D3
D4
A1
B0 B1
C0
D0
D3
D4
0
Defines # of Bytes written into serial memory at
module manufacturer
128bytes 80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
10
0Ah
5
# of module Rows on this assembly
1 Bank
01h
6
Data width of this assembly
64 bits
40h
7
.........Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at highest CAS Latency
8ns 7.5ns 7ns
6ns
5ns
5ns
5ns
80h 75h 70h 60h 50h
50h
50h
10
DDR SDRAM Access time from clock at highest CL 0.8
ns
0.75
ns
0.75
ns
0.70
ns
0.65
ns
0.65
ns
0.65
ns
80h 75h 75h 70h 65h
65h
65h
11
DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00h
12
Refresh rate & type
7.8us & Self refresh
82h
13
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
N/A
00h
15
Minimum clock delay for back-to-back random col-
umn
address
t
CCD
=1CLK 01h
16
DDR SDRAM device attributes : Burst lengths sup-
ported
2,4,8 0Eh
17
DDR SDRAM device attributes : # of banks on each
DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes : CAS Latency sup-
ported
2,2.5,3
0Ch
0Ch
0Ch
0Ch
1Ch
1Ch
1Ch
19
DDR SDRAM device attributes : CS Latency
0CLK
01h
20
DDR SDRAM device attributes : WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Differential clock /
non Registered
20h
22
DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23
DDR SDRAM cycle time at second highest CL
10ns 10ns 7.5ns 7.5ns 5.0ns 6.0ns 6.0ns A0h A0h 75h 75h 50h
60h
60h
24
DDR SDRAM Access time from clock at highest CL 0.8
ns
0.75
ns
0.75
ns
0.70
ns
0.65
ns
0.70
ns
0.70
ns
80h 75h 75h 70h 65h
70h
70h
6
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
25
DDR SDRAM cycle time at third highest CL
-
-
-
-
7.5ns 7.5ns 7.5ns 00h 00h 00h 00h 75h
75h
75h
26
DDR SDRAM Access time from clock at third high-
est CL
- - - -
0.75
ns
0.75
ns
0.75
ns
00h
00h
00h
00h
75h
75h
75h
27
Minimum row precharge time (=t
RP
)
20ns 20ns 15ns 18ns 15ns 15ns 20ns
50h 50h 3Ch
48h 3Ch
3Ch
50h
28
Minimum row activate to row active delay(=t
RRD
) 15ns
15ns
15ns
12ns 10ns 10ns 10ns 3Ch
3Ch
3Ch
30h
28h
28h
28h
29
Minimum RAS to CAS delay(=t
RCD
) 20ns
20ns
15ns
18ns 15ns 15ns 20ns
50h
50h
3Ch
48h
3Ch
3Ch
50h
30
Minimum active to precharge time(=t
RAS
) 50ns
45ns
45ns
42ns 40ns 40ns 40ns
32h
2Dh
2Dh
2Ah
28h
28h
28h
31
Module ROW density
256MB
40h
32
Command and address signal input setup time
1.1ns 0.9ns 0.9ns 0.75
ns
0.6ns 0.6ns 0.6ns B0h 90h 90h
75h
60h
60h
60h
33
Command and address signal input hold time
1.1ns 0.9ns 0.9ns 0.75
ns
0.6ns 0.6ns 0.6ns B0h 90h 90h
75h
60h
60h
60h
34
Data signal input setup time
0.6ns 0.5ns 0.5ns 0.45
ns
0.4ns 0.4ns 0.4ns 60h 50h 50h
45h
40h
40h
40h
35
Data signal input hold time
0.6ns 0.5ns 0.5ns 0.45
ns
0.4ns 0.4ns 0.4ns 60h 50h 50h
45h
40h
40h
40h
36-40 Superset information (may be used in future)
00h
41
SDRAM device minimum active to active/auto-re-
fresh time
(=t
RC
)
70ns 65ns 65ns 60ns 60ns 60ns 60ns
46h 41h 41h
3Ch
3Ch
3Ch
3Ch
42
SDRAM device minimum active to autorefresh to
active/auto-refresh time (=t
RFC
)
80ns 75ns 75ns 72ns 70ns 70ns 70ns
50h 4Bh 4Bh
48h
46h
46h
46h
43
SDRAM device maximum device cycle time (=t
CK
MAX
)
12ns 12ns 12ns 12ns 12ns 12ns 12ns
30h 30h 30h
30h
30h
30h
30h
44
SDRAM device maximum skew between DQS and
DQ signals (=t
DQSQ
)
0.6ns 0.5ns 0.5ns 0.45
ns
0.4ns 0.4ns 0.4ns 3Ch 32h 32h
2Dh
28h
28h
28h
45
SDRAM device maximum read datahold skew fac-
tor (=t
QHS
)
1ns 0.75
ns
0.75
ns
0.60
ns
0.55
ns
0.55
ns
0.55
ns
A0h 75h 75h
60h
55h
55h
55h
46-61 Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
00h
00h
00h
11h
11h
11h
63
Checksum for Bytes 0 ~ 62
-
E7h 22h CAh
4Bh
A3h
BEh
E6h
64
Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71 ....... Manufacturer JEDEC ID code
00h
Byte
# Function
described
Function Supported
Hex value
A1
B0 B1 C0
D0
D3
D4
A1
B0 B1
C0
D0
D3
D4
Serial Presence Detect Information (cont.)
MOSEL VITELIC
V826632K24S
7
V826632K24S Rev.1.2 January 2003
DC Operating Conditions
(T
A
= 0 to 70C, Voltage referenced to V
SS
= 0V)
Notes: 1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with <= 5ns of duration.
72
Manufacturing location
02=Taiwan 05=China 0A=S-CH
73-90 Module part number (ASCII)
V826632K24S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
-
94
Manufacturing date (Year)
-
-
95~98 Assembly serial #
-
-
99~12
7
Manufacturer specific data (may be used in future)
Undefined
00h
128~2
55
Open for customer use
Undefined
00h
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
2.3
2.5
2.7
V
Power Supply Voltage for DDR400
V
DD
2.5
2.6
2.7
V
Power Supply Voltage
V
DDQ
2.3
2.5
2.7
V
1
Power Supply Voltage for DDR400
V
DDQ
2.5
2.6
2.7
V
1
Input High Voltage
V
IH
V
REF
+ 0.15
-
V
DDQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
-
V
REF
- 0.15
V
2
I/O Termination Voltage
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
Reference Voltage
V
REF
V
DDQ/2
- 0.05
-
V
DDQ/2
+ 0.05
V
Input Leakage Current
I
I
-2
-
2
A
Output Leakage Current
IO
z
-5
-
5
A
Output High Current (V
OUT
= 1.95V)
IO
H
-16.8
-
-
mA
Output Low Current (V
OUT
= 0.35V)
IO
L
16.8
-
-
mA
Byte
# Function
described
Function Supported
Hex value
A1
B0 B1 C0
D0
D3
D4
A1
B0 B1
C0
D0
D3
D4
8
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
AC Operating Conditions
(T
A
= 0 to 70 C, Voltage referenced to V
SS
= 0V)
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
AC Operating Test Conditions
(T
A
= 0 to 70C, Voltage referenced to V
SS
= 0V)
Parameter Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH(AC)
V
REF
+ 0.31
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
V
IL(AC)
V
REF
- 0.31
V
Input Differential Voltage, CK and CK inputs
V
ID(AC)
0.7
V
DDQ
+ 0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
V
IX(AC)
0.5*V
DDQ
-0.2
0.5*V
DDQ
+0.2
V
2
Parameter Value
Unit
Reference Voltage
V
DDQ
x 0.5
V
Termination Voltage
V
DDQ
x 0.5
V
AC Input High Level Voltage (V
IH
, min)
V
REF
+ 0.31
V
AC Input Low Level Voltage (V
IL
, max)
V
REF
- 0.31
V
Input Timing Measurement Reference Level Voltage
V
REF
V
Output Timing Measurement Reference Level Voltage
V
TT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (R
T
) 50
ohm
Series Resistor (R
S
)
25 ohm
Output Load Capacitance for Access Time Measurement (C
L
) 30
pF
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
MOSEL VITELIC
V826632K24S
9
V826632K24S Rev.1.2 January 2003
Input/Output Capacitance
(V
DD
= 2.5V, V
DD
= 2.6V, V
DDQ
= 2.5V, V
DDQ
= 2.6V, T
A
= 25C, f = 1MHz)
DDR SDRAM Module I
DD
Spec Table
Parameter
Symbol Min
Max
Unit
Input capacitance (A
0
~ A
11
, BA
0
~ BA
1
, RAS, CAS, WE) CIN
1
29 34 pF
Input capacitance (CKE
0
) CIN
2
29 34 pF
Input capacitance (CS
0
) CIN
3
26 30 pF
Input capacitance (CLK
1
, CLK
2
) CIN
4
30 32 pF
Data & DQS input/output capacitance (DQ
0
~DQ
63
) C
OUT
8 9 pF
Input capacitance (DM0~DM8)
CIN
5
8 9 pF
Symbol
A1
PC1600@CL=2
B0
PC2100B@CL=2.5
B1
PC2100A@CL=2
C0
PC2700A@CL=2.5
D0/D3/D4
PC3200@CL=3
Unit
IDD0
720
800
800
880
960
mA
IDD1
800
960
960
1120
1280
mA
IDD2P
60
60
60
60
60
mA
IDD2F
200
250
250
280
330
mA
IDD2Q
130
170
170
190
220
mA
IDD3P
240
260
260
300
340
mA
IDD3N
360
380
380
480
580
mA
IDD4R
1200
1520
1520
1840
2160
mA
IDD4W
1040
1360
1360
1680
2000
mA
IDD5
1440
1520
1520
1600
1680
mA
IDD6
Normal
48
48
48
48
48
mA
Low power
29
29
29
29
29
mA
IDD7
2000
2400
2400
2800
3200
mA
10
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
AC Characteristics
(AC operating conditions unless otherwise noted)
Parameter
Sym-
bol
(PC400A)
D0
(PC400B)
D3
(PC400C)
D4
(PC333)
C0
(PC266A)
B1
(PC266B)
B0
(PC200)
A1
Units
Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Row Cycle Time
t
RC
60
- 60
- 60
- 60
- 65
- 65 - 70 - ns
Auto Refresh Row Cycle Time
t
RFC
70
- 70
- 70
- 72
- 75 - 75 - 80 - ns
Row Active Time
t
RAS
40
120K 40
120K 40
120K 42 120K 45 120K 45 120K
50
120K ns
Row Address to Column Address
Delay
t
RCD
15
- 15
- 20
- 18
- 15
- 20 -
20
- ns
Row Active to Row Active Delay
t
RRD
10
-
10
-
10
-
12
-
15
-
15
-
15
-
ns
Column Address to Column Ad-
dress Delay
t
CCD
1 - 1 - 1 - 1 - 1 - 1 -
1
-
tCK
Row Precharge Time
t
RP
15
- 15
- 20
- 18
- 15
- 20 -
20
- ns
Write Recovery Time
t
WR
15
- 15
- 15
- 15
- 15 - 15 - 15 - ns
Last Data-In to Read Command
t
DRL
1 - 1 - 1 - 1 - 1 - 1 -
1
-
tCK
Auto Precharge Write Recovery +
Precharge Time
t
DAL
35 - 35 - 35 - 35 - 35 - 35 -
35
- ns
System Clock Cy-
cle Time
CAS Latency
= 3
t
CK
5
12
5
12
5
12
-
12
-
12
-
12
-
12
ns
CAS Latency
= 2.5
5
12 6
12 6
12 6 12 7 12 7.5 12 8 12
ns
CAS Latency
= 2
7.5 12 7.5 12 7.5 12 7.5 12 7.5 12 10 12
10 12 ns
Clock High Level Width
t
CH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
0.45
0.55 tCK
Clock Low Level Width
t
CL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
0.45
0.55 tCK
Data-Out edge to Clock edge
Skew
t
AC
-0.65 0.65 -0.65 0.65 -0.65 0.65 -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 tCK
DQS-Out edge to Clock edge
Skew
t
DQSCK
-0.60 0.60
-0.60 0.60
-0.60 0.60 -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 tCK
DQS-Out edge to Data-Out edge
Skew
t
DQSQ
- 0.40 - 0.40 - 0.40 - 0.45 - 0.5 -
0.5
- 0.6
tCK
Data-Out hold time from DQS
t
QH
t
HPmin
-
0.75ns
- t
HPmin
-
0.75ns
- t
HPmin
-
0.75ns
- t
HPmin
-
0.75n
s
- t
HPmin
-
0.75n
s
- t
HPmin
-
0.75n
s
- t
HP-
min
-
0.75
ns
- tCK
1
Clock Half Period
t
HP
t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- tCK
1
Input Setup Time (fast slew rate)
t
IS
0.6 - 0.6 - 0.6 - 0.75 - 0.9 - 0.9 -
1.1
- tCK
2,3,5,
6
MOSEL VITELIC
V826632K24S
11
V826632K24S Rev.1.2 January 2003
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Input Hold Time (fast slew rate)
t
IH
0.6
- 0.6
- 0.6
- 0.75
- 0.9 - 0.9 - 1.1 - tCK
2,3,5,
6
Input Setup Time (slow slew rate)
t
IS
0.75 - 0.75 - 0.75 - 0.8 - 1.0 - 1.0 - 1.1 - tCK
2,4,5,
6
Input Hold Time (slow slew rate)
t
IH
0.75
- 0.75
- 0.75
- 0.8
- 1.0 - 1.0 - 1.1 - tCK
2,4,5,
6
Input Pulse Width
t
IPW
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 2.2 - 2.2 - - - tCK
6
Write DQS High Level Width
t
DQSH
0.35
0.35
0.35
0.35
0.35
0.35
0.35
tCK
Write DQS Low Level Width
t
DQSL
0.35
0.35
0.35
0.35
0.35
0.35
0.35
tCK
CLK to First Rising edge of DQS-
In
t
DQSS
0.72 1.25 0.72 1.25 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25
0.75
1.25 tCK
Data-In Setup Time to DQS-In
(DQ & DM)
t
DS
0.40 - 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - 0.6 - tCK
7
Data-in Hold Time to DQS-In (DQ
& DM)
t
DH
0.40 - 0.40 - 0.40 - 0.45
- 0.5 - 0.5 - 0.6 - tCK
7
DQ & DM Input Pulse Width
t
DIPW
1.75 - 1.75 - 1.75 - 1.75 - 1.75 - 1.75 - 2 - tCK
Read DQS Preamble Time
t
RPRE
0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read DQS Postamble Time
t
RPST
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Write DQS Preamble Setup Time t
WPRES
0 - 0 - 0 - 0 - 0 - 0 -
0
-
tCK
Write DQS Preamble Hold Time t
WPREH
0.25 - 0.25 - 0.25 - 0.25 - 0.25 - 0.25 -
0.25
- tCK
Write DQS Postamble Time
t
WPST
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Mode Register Set Delay
t
MRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
tCK
Power Down Exit Time to any
command
t
XPDN
1 - 1 - 1 - 1 - 1 - 1 -
1
-
tCK
Exit Self Refresh to Non-Read
Command
t
XSNR
200 - 200 - 200 - 200 - 200 - 200
-
200
- tCK
8
Average Periodic Refresh Interval t
REFI
- 7.8
- 7.8
- 7.8
- 7.8
- 7.8
- 7.8
-
7.8
us
Parameter
Sym-
bol
(PC400A)
D0
(PC400B)
D3
(PC400C)
D4
(PC333)
C0
(PC266A)
B1
(PC266B)
B0
(PC200)
A1
Units
Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
AC Characteristics (cont.)
12
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
Absolute Maximum Ratings
Parameter Symbol
Rating
Unit
Ambient Temperature
T
A
0
~
70
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
relative to V
SS
V
DD
-0.5 ~ 3.6
V
Voltage on V
DDQ
relative to V
SS
V
DDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
I
OS
50 mA
Power Dissipation
P
D
6
W
Soldering Temperature Time
T
SOLDER
260 10
C Sec
Note: Operation at above absolute maximum rating can adversely affect device reliability
MOSEL VITELIC
V826632K24S
13
V826632K24S Rev.1.2 January 2003
Package Dimensions
Tolerances :
0.005(.13) unless otherwise specified.
The used device is 8Mx16 SDRAM, TSOP.
SDRAM Part NO : K4H281638B-TC
5.25
0.006
5.077
i
0.050
0.0078
0.006
(0.20
0.15)
0
.
10
0
M
in
(
2
.
3
0
Mi
n
)
0
.
39
3
(
10.
00
)
(1.270)
0.
100
(
2.
50
)
Detail B
A
B
0.089
(2.26)
(128.950)
(133.350
0.15
)
0.250
(6.350
)
Detail A
0.157
(4.00)
0.071
(1.80)
0.039
0.002
(1.000
0.050)
(3.80)
2.175
(6.62)
(64.77)
(49.53)
(
17
.
80
)
2.55
1.95
0.26
2.500
0
.
7
0.10
C
B A
0.10 M C
B
A
0.1496
(3.00)
0.118
(2.00)
0.0787
(4.00)
0.1575
1.25
0.006
(31.75
0.15)
(4
.
00
)
(
2X
)
0
.
15
7
0.098 Max
0.050
0.0039
(1.270
0.10)
(2.47 Max)
M
M
Units: Inches (Millimeters)
14
V826632K24S Rev. 1.2 January 2003
MOSEL VITELIC
V826632K24S
C
L
= 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533
U
UNBUFFERED DIMM
PC2100
08
SPD Revision
0
V826632K24SXXX-XX 256MB CLXX
PC2100U-2533-080-A
XXXX-XXXXXXX
Assembly in Taiwan
A
Gerber file
-
-
-
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2100 or PC1600
CAS Latency
C
L
= 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533
U
UNBUFFERED DIMM
PCXXXX
0
SPD Revision
V826632K24SXXX-XX 256MB CLXX
PCXXXXU-2533-0-XX
XXXX-XXXXXXX
Assembly in Taiwan
X
-
-
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2700
or PC3200
CAS Latency
X
-
Gerber file used for this design
"A" : Reference design for raw card A is used for this assembly
"B" : Reference design for raw card B is used for this assembly
"C" : Reference design for raw card C is used for this assembly
"Z" : None of the reference design were used for this assembly
Revision number of the reference design used
"1" : 1st Revision
"2" : 2nd Revision
blank : not applicable
MOSEL VITELIC
V826632K24S
15
V826632K24S Rev.1.2 January 2003
WORLDWIDE OFFICES
Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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