MOSEL VITELIC
1
V436616Y24VATG-75
3.3 VOLT 16M x 64 HIGH PERFORMANCE
133 MHZ SDRAM
UNBUFFERED SODIMM
PRELIMINARY
V436616Y24VATG-75 Rev. 1.3 October 2001
Features
s
JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
s
Serial Presence Detect with E
2
PROM
s
Nonbuffered
s
Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
s
Single +3.3V ( 0.3V) Power Supply
s
All Device Pins are LVTTL Compatible
s
8192 Refresh Cycles every 64 ms
s
Self-Refresh Mode
s
Internal Pipelined Operation; Column Address
can be changed every System Clock
s
Auto Precharge and Piecharge all Banks by A10
s
Data Mask Function by DQM
s
Mode Register Set Programming
s
Programmable (CAS Latency:2, 3 Clocks)
Description
The V436616Y24VATG-75 memory module is
organized 16,777,216 x 64 bits in a 144 pin
SODIMM. The 16M x 64 memory module uses 4
Mosel-Vitelic 16M x 16 SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
Part Number
Speed
Grade
Configuration
V436616Y24VATG-75
-75
(133 MHz)
16M x 64
1
Pin 2 on Backside
Pin 144 on Backside
59
61
143
16M x 16
16M x 16
16M x 16
16M x 16
2
V436616Y24VATG-75 Rev. 1.3 October 2001
MOSEL VITELIC
V436616Y24VATG-75
Pin Configurations (Front Side/Back Side)
Note:
1. RAS, CAS, WE CASx, CSx are active low signals.
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
A12
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0A12, BA0, BA1
Address, Bank Select
DQ0DQ63
Data Inputs/Outputs
RAS
Row Address Strobes
CAS
Column Address Strobes
WE
Write Enable
CS0, CS1
Chip Select
DQMB0DQMB7
Output Enable
CKE0, CKE1
Clock Enable
CLK0, CLK1
Clock
SDA
Serial Input/Output
SCL
Serial Clock
VDD
Power Supply
VSS
Ground
NC
No Connect (Open)
4
V436616Y24VATG-75 Rev. 1.3 October 2001
MOSEL VITELIC
V436616Y24VATG-75
Serial Presence Detect Information
A serial presence detect storage device -
E
2
PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD-Table for 75 modules:
Byte Number
Function Described
SPD Entry Value
Hex Value
16Mx64
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
13
0D
4
Number of Column Addresses (for x16 SDRAM)
9
09
5
Number of DIMM Banks
1
01
6
Module Data Width
64
40
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
none
00
12
Refresh Rate/Type
Self-Refresh,7.8
s
82
13
SDRAM width, Primary
x16
10
14
Error Checking SDRAM Data Width
n/a / x16
00
15
Minimum Clock Delay from Back to Back Random
Column Address
t
ccd
= 1 CLK
01
16
Burst Length Supported
1, 2, 4, 8
0F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL =2, 3
06
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
22
SDRAM Device Attributes: General
Vcc tol 10%
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
10. 0 ns
A0
24
Maximum Data Access Time from Clock for CL = 2
5.4 ns
54
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
20 ns
14
28
Minimum Row Active to Row Active Delay t
RRD
15 ns
0F
29
Minimum RAS to CAS Delay t
RCD
20 ns
14
30
Minimum RAS Pulse Width t
RAS
45 ns
2D
MOSEL VITELIC
V436616Y24VATG-75
5
V436616Y24VATG-75 Rev. 1.3 October 2001
DC Characteristics
T
A
= 0
C to 70
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
0.3V
31
Module Bank Density (Per Bank)
128 Mbyte
20
32
SDRAM Input Setup Time
1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup Time
1.5 ns
15
35
SDRAM Data Input Hold Time
0.8 ns
08
62-61
Superset Information (May be used in Future)
00
62
SPD Revision
Revision 2
02
63
Checksum for Bytes 0 - 62
1D
64
Manufacturer's JEDEC ID Code
Mosel Vitelic
40
65-71
Manufacturer's JEDEC ID Code (cont.)
00
72
Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436616Y24VATG-75
91-92
PCB Identification Code
Current PCB Revision
93
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 = MSB
99-125
Reserved
00
126
Intel Specification for Frequency
64
127
Reserved
00
128+
Unused Storage Location
00
Symbol
Parameter
Limit Values
Unit
Min.
Max.
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
V
IL
Input Low Voltage
0.5
0.8
V
V
OH
Output High Voltage (I
OUT
= 4.0 mA)
2.4
--
V
V
OL
Output Low Voltage (I
OUT
= 4.0 mA)
--
0.4
V
I
I(L)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
40
40
A
I
O(L)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
40
40
A
SPD-Table for 75 modules: (Continued)
Byte Number
Function Described
SPD Entry Value
Hex Value
16Mx64
PDF 
ZIP