DESCRIPTION
The 4501 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
two 8-bit timers (each timer has a reload register), interrupts, and
10-bit A-D converter.
The various microcomputers in the 4501 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
q
Minimum instruction execution time ................................ 0.68
s
(at 4.4 MHz oscillation frequency, in high-speed mode)
q
Supply voltage ......................................................... VRST to 5.5 V
(VRST: detection voltage of voltage drop detection circuit)
Product
M34501M2-XXXFP
M34501M4-XXXFP
M34501E4FP (Note)
ROM type
Mask ROM
Mask ROM
One Time PROM
Package
20P2N-A
20P2N-A
20P2N-A
RAM size
(
4 bits)
128 words
256 words
256 words
ROM (PROM) size
(
10 bits)
2048 words
4096 words
4096 words
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
q
Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
q
Interrupt ........................................................................ 4 sources
q
Key-on wakeup function pins ................................................... 12
q
Input/Output port ...................................................................... 14
q
A-D converter .................. 10-bit successive comparison method
q
Watchdog timer
q
Clock generating circuit (ceramic resonator/RC oscillation)
q
LED drive directly enabled (port D)
q
Power-on reset circuit
q
Voltage drop detection circuit ........................... VRST: Typ. 3.5 V
(Ta = 25 C)
APPLICATION
Electrical household appliance, consumer electronic products, of-
fice automation equipment, etc.
Note: Shipped in blank.
PIN CONFIGURATION
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
2
0
P1
2
/CNTR
P1
3
/INT
D
0
D
1
P0
3
P0
2
P0
1
P0
0
P1
1
P1
0
O
u
t
l
i
n
e
2
0
P
2
N
-
A
2
3
4
5
6
7
8
9
1
0
1
M
3
4
5
0
1
M
x
-
X
X
X
F
P
M
3
4
5
0
1
E
4
F
P
P
2
1
/
A
I
N
1
X
I
N
X
O
U
T
C
N
V
S
S
V
S
S
V
D
D
P
2
0
/
A
I
N
0
R
E
S
E
T
D
3
/
K
D
2
/
C
Pin configuration (top view) (4501 Group)
2
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
BLOCK DIAGRAM
Block diagram (4501 Group)
R
A
M
R
O
M
M
e
m
o
r
y
I
/
O
p
o
r
t
I
n
t
e
r
n
a
l
p
e
r
i
p
h
e
r
a
l
f
u
n
c
t
i
o
n
s
T
i
m
e
r
T
i
m
e
r
1
(
8
b
i
t
s
)
S
y
s
t
e
m
c
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
T
i
m
e
r
2
(
8
b
i
t
s
)
1
2
8
,
2
5
6
w
o
r
d
s
4
b
i
t
s
2
0
4
8
,
4
0
9
6
w
o
r
d
s
1
0
b
i
t
s
4
5
0
0
S
e
r
i
e
s
C
P
U
c
o
r
e
R
e
g
i
s
t
e
r
B
(
4
b
i
t
s
)
R
e
g
i
s
t
e
r
A
(
4
b
i
t
s
)
R
e
g
i
s
t
e
r
D
(
3
b
i
t
s
)
R
e
g
i
s
t
e
r
E
(
8
b
i
t
s
)
S
t
a
c
k
r
e
g
i
s
t
e
r
S
K
(
8
l
e
v
e
l
s
)
I
n
t
e
r
r
u
p
t
s
t
a
c
k
r
e
g
i
s
t
e
r
S
D
P
(
1
l
e
v
e
l
)
A
L
U
(
4
b
i
t
s
)
X
I
N
-
X
O
U
T
W
a
t
c
h
d
o
g
t
i
m
e
r
(
1
6
b
i
t
s
)
(
1
0
b
i
t
s
2
c
h
)
A
-
D
c
o
n
v
e
r
t
e
r
P
o
r
t
P
0
4
P
o
r
t
P
1
4
P
o
r
t
P
2
2
P
o
r
t
D
4
P
o
w
e
r
-
o
n
r
e
s
e
t
c
i
r
c
u
i
t
V
o
l
t
a
g
e
d
r
o
p
d
e
t
e
c
t
i
o
n
c
i
r
c
u
i
t
3
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PERFORMANCE OVERVIEW
Function
111
0.68
s (at 4.4 MHz oscillation frequency, in high-speed mode)
2048 words
10 bits
4096 words
10 bits
128 words
4 bits
256 words
4 bits
Four independent I/O ports.
Input is examined by skip decision.
Ports D
2
and D
3
are equipped with a pull-up function and a key-on wakeup function. Both func-
tions can be switched by software.
Ports D
2
and D
3
are also used as ports C and K, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P1
2
and P1
3
are also used as CNTR and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
1-bit I/O; Port C is also used as port D
2
.
1-bit I/O; Port K is also used as port D
3
.
1-bit I/O; CNTR pin is also used as port P1
2
.
1-bit input; INT pin is also used as port P1
3
.
Two independent I/O ports. A
IN0
A
IN1
is also used as ports P2
0
, P2
1
, respectively.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has a event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 channel (A
IN0
pin, A
IN1
pin)
4 (one for external, two for timer, one for A-D)
1 level
8 levels
CMOS silicon gate
20-pin plastic molded SOP (20P2N-A)
20 C to 85 C
VRST to 5.5 V (VRST: detected voltage of voltage drop detection circuit. Refer to the voltage
drop detection circuit characteristics.)
1.7 mA (at V
DD
= 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors
in the cut-off state)
0.1
A (at room temperature, V
DD
= 5 V, output transistors in the cut-off state)
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes
Input/Output
ports
M34501M2
M34501M4/E4
M34501M2
M34501M4/E4
I/O
I/O
I/O
I/O
I/O
I/O
Timer I/O
Interrupt input
Analog input
Timers
A-D converter
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
dissipation
(typical value)
ROM
RAM
D
0
D
3
P0
0
P0
3
P1
0
P1
3
P2
0
, P2
1
C
K
CNTR
INT
A
IN0
, A
IN1
Timer 1
Timer 2
Analog input
Sources
Nesting
Active mode
RAM back-up mode
4
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PIN DESCRIPTION
Name
Power supply
Ground
CNV
SS
Reset input/output
System clock input
I/O port D
I/O
I/O port P1
I/O port P2
I/O port C
I/O port K
Timer input/output
Interrupt input
Analog input
Pin
V
DD
V
SS
CNV
SS
RESET
X
IN
D
0
D
3
P0
0
P0
3
P1
0
P1
3
P2
0
, P2
1
Port C
Port K
CNTR
INT
A
IN0
A
IN1
Input/Output
--
--
--
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNV
SS
to V
SS
and apply "L" (0V) to CNV
SS
certainly.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the
voltage drop detection circuit cause the system to be reset, the RESET pin outputs
"L" level.
I/O pins of the system clock generating circuit. When using a ceramic resonator, connect
it between pins X
IN
and X
OUT
. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to X
IN
, and leave X
OUT
pin open.
Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-
put latch. For input use, set the latch of the specified bit to "1." Input is examined by
skip decision. The output structure is N-channel open-drain. Ports D
2
and D
3
are
equipped with a pull-up function and a key-on wakeup function. Both functions can
be switched by software.
Ports D
2
and D
3
are also used as ports C and K, respectively.
Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to "1." The output structure is N-channel open-drain. Port P0 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to "1." The output structure is N-channel open-drain. Port P1 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P1
2
and P1
3
are also used as CNTR and INT, respectively.
Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch
is set to "1." The output structure is N-channel open-drain. Port P2 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
1-bit I/O port. Port C can be used as inputs when the output latch is set to "1." The
output structure is N-channel open-drain. Port C has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port C is also used
as port D
2
.
1-bit I/O port. Port K can be used as inputs when the output latch is set to "1." The
output structure is N-channel open-drain. Port K has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port K is also used
as port D
3
.
CNTR pin has the function to input the clock for the timer 2 event counter, and to out-
put the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port
P1
2
.
INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software. This pin is also used as port P1
3
.
A-D converter analog input pins. A
IN0
and A
IN1
are also used as ports P2
0
and P2
1
,
respectively.
Notes 1: Pins except above have just single function.
2: The input/output of D
2
, D
3
, P1
2
and P1
3
can be used even when C, K, INT and CNTR (input) are selected.
3: The input of P1
2
can be used even when CNTR (output) is selected.
4: The input/output of P2
0
, P2
1
can be used even when A
IN0
, A
IN1
are selected.
Pin
D
2
D
3
P1
2
P1
3
Multifunction
C
K
CNTR
INT
MULTIFUNCTION
Pin
C
K
CNTR
INT
Multifunction
D
2
D
3
P1
2
P1
3
Pin
P2
0
P2
1
Multifunction
A
IN0
A
IN1
Pin
A
IN0
A
IN1
Multifunction
P2
0
P2
1
X
OUT
System clock output
Output
5
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
DEFINITION OF CLOCK AND CYCLE
q
Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
External ceramic resonator
External RC oscillation
Clock (f(X
IN
)) by the external clock
Clock (f(RING)) of the ring oscillator which is the internal oscil-
lator.
q
System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bits 2 and 3 of the clock con-
trol register MR.
Register MR
System clock
(Note 1)
f(X
IN
) or f(RING)
f(X
IN
)/2 or f(RING)/2
f(XIN)/4 or f(RING)/4
f(XIN)/8 or f(RING)/8
Table Selection of system clock
PORT FUNCTION
Port
Port D
Port P0
Port P1
Port P2
I/O
unit
1
4
4
2
Control
instructions
SD, RD
SZD, CLD
SCP, RCP
SNZCP
IAK, OKA
OP0A
IAP0
OP1A
IAP1
OP2A
IAP2
Control
registers
PU2, K2
PU0, K0
PU1, K1
W6, I1
PU2, K2
Q1
Output structure
N-channel open-drain
N-channel open-drain
N-channel open-drain
N-channel open-drain
Input
Output
I/O
(4)
I/O
(4)
I/O
(4)
I/O
(2)
Remark
Pin
D
0
, D
1
D
2
/C
D
3
/K
P0
0
P0
3
P1
0
, P1
1
P1
2
/CNTR,
P1
3
/INT
P2
0
/A
IN0
P2
1
/A
IN1
Notes 1: The ring oscillator clock is f(RING), the clock by the ce-
ramic resonator, RC oscillation or external clock is f(X
IN
).
2: The default mode is selected after system is released
from reset and is returned from RAM back-up.
MR
2
0
1
0
1
MR
3
0
0
1
1
Operation mode
High-speed mode
Middle-speed mode
Low-speed mode
Default mode
q
Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
q
Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
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