1
MT9075B
E1 Single Chip Transceiver
Features
Combined PCM 30 framer, Line Interface Unit
(LIU) and link controllers in a 68 pin PLCC or
100 pin MQFP package
Selectable bit rate data link access with
optional S
a
bits HDLC controller (HDLC0) and
channel 16 HDLC controller (HDLC1)
LIU dynamic range of 20 dB
Enhanced performance monitoring and
programmable error insertion functions
Low jitter DPLL for clock generation
Operating under synchronized or free run mode
Two-frame receive elastic buffer with controlled
slip direction indication
Selectable transmit or receive jitter attenuator
Intel or Motorola non-multiplexed parallel
microprocessor interface
CRC-4 updating algorithm for intermediate path
points of a message-based data link application
ST-BUS/GCI 2.048 Mbit/s backplane bus for
both data and signalling
Applications
E1 add/drop multiplexers and channel banks
CO and PBX equipment interfaces
Primary Rate ISDN nodes
Digital Cross-connect Systems (DCS)
Description
The MT9075B is a single chip device which
integrates an advanced PCM 30 framer with a Line
Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane
and provides selectable rate data link access with
optional HDLC controllers for S
a
bits and channel 16.
The LIU interfaces the framer functions to the PCM
30 transformer-isolated four wire line.
The MT9075B meets or supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also meets or supports ETSI
ETS 300 011, ETS 300 166 and ETS 300 233 as well
as BS 6450.
Figure 1 - Functional Block Diagram
ST-BUS
Interface
CAS
Buffer
ST Loop
PL Loop
National
DG Loop
Alarm Detection, 2 Frame Slip Buffer
ST-BUS
Interface
Microprocessor
Interface
TAIS
Line
Driver
TTIP
Pulse
Generator
Clock,Data
Recovery
Rx Equalizer
& Data Slicer
OSC1
OSC2
RTIP
M/S
CSTi
DSTi
CSTo
DSTo
E2o
RRING
TRING
Bit Buffer
F0b C4b
RxMF
LOS
TxMF
Transmit Framing, Error and
Test Signal Generation
Data Link,
HDLC0,
HDLC1
Receive Framing, Performance Monitoring,
RxDLCLK RxDL
TxDL TxDLCLK
R/W
/
WR
CS
DS/RD
IRQ
D7~D0
~AC0
RxFP/Rx64kCK
Jitter Attenuator
& Clock Control
AC4
RM Loop
MT Loop
Tdi
Tdo
Tms
Tclk
Trst
IEEE 1149.1
MS/FR
INT/MOT
DS5025
ISSUE 2
October 1998
Preliminary Information
Ordering Information
MT9075BP
68Pin PLCC
MT9075BL
100 Pin MQFP
-40
C to 85
C
MT9075B
Preliminary Information
2
Figure 2 - Pin Connections
60
27
TAIS
CS
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Trst
Tclk
Tms
Tdo
Tdi
GNDATx
TRING
TTIP
VDDATx
VDD
RxFP/Rx64KCK
F0b
VSS
IC
E2o
RESET
IRQ
D0
D1
D2
D3
VSS
IC
INT/MOT
VDD
D4
D5
D6
D7
R/W/WR
AC0
DS/
RD
DSTi
CSTi
CSTo
BL/
FR
DSTo
OSC2
OSC1
VSS
VDD
TxDL
TxDLCK
IC
IC
VSS
VDD
LOS
AC1
AC2
AC3
AC4
GNDARx
RTIP
RRING
VDDARx
BS/
LS
TxMF
NC
NC
RxDCLK
RxDL
RxMF
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C4b
VDD
100 PIN MQFP (JEDEC MO-112)
68 PIN PLCC
NC
NC
NC
NC
NC
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
22
24
26
28
30
32
34
36
38
40
44
46
48
42
82
100
98
96
94
92
88
86
84
90
20
18
16
14
12
10
8
6
4
2
LOS
IC
NC
IC
TCDLCK
TXDL
BL/
FR
VDD
VSS
OSC1
OSC2
NC
VSS
VDD
CST
o
CSTi
DST
o
DSTi
DS/
RD
NC
NC
NC
NC
NC
NC
NC
TAIS
Tclk
Tms
Tdo
Tdi
GNDATx
F0b
C4b
E2o
NC
TRING
TTIP
VDDATx
VDD
VSS
IC
RxFP/Rx64KCK
NC
Trst
NC
BL
/
LS
AC
2
AC
1
RXDL
RXDLCK
IC
IC
VSS
VDD
VD
ARx
R
TIP
RxMF
TxMF
NC
AC
3
AC
4
NC
NC
NC
GND
ARx
RRING
NC
NC
NC
NC
NC
NC
NC
NC
CS
RESET
IRQ
D0
D1
D2
D3
VSS
INT/MOT
D6
R/W/WR
IC
VDD
D4
D5
D7
NC
AC0
NC
NC
Preliminary Information
MT9075B
3
Pin Description
Pin #
Name
Description
PLCC MQFP
1
66
OSC1
Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2 where a
crystal is used, or is directly driven when a 20.000 MHz oscillator is employed (see
Figures 6 and 7). CMOS input switching level.
2
67
OSC2
Oscillator Output. Not suitable for driving other devices.
3
68
V
SS
Negative Power Supply (Input). Digital ground.
4
69
V
DD
Positive Power Supply (Input). Digital supply (+5V
5%).
5
70
CSTo
Control ST-BUS Output. CSTo carries one of the following two serial streams for CAS
and CCS respectively:
(i) A 2.048 Mbit/s ST-BUS status stream which contains the 30 receive signalling nibbles
(ABCDZZZZ or ZZZZABCD). The most significant nibbles of each ST-BUS time slot are
valid and the least significant nibbles of each ST-BUS time slot are tristated when control
bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the valid
and tristated nibbles is reversed.
(ii) A 64 kb/s output when the 64 KHz common channel signalling option is selected
(page 01H, address 1AH, bit 0, 64KCCS =1) for channel 16.
6
71
CSTi
Control ST-BUS Input. CSTi carries one of the following two serial streams for CAS and
CCS respectively:
(i) A 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit signalling
nibbles (ABCDXXXX or XXXXABCD) when page 01H, address 1AH, bit 3, RPSIG=0.
When RPSIG=1 this pin has no function. The most significant nibbles of each ST-BUS
time slot are valid and the least significant nibbles of each ST-BUS time slot are ignored
when control bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position
of the valid and ignored nibbles is reversed.
(ii) A 64 kb/s input when the 64 KHz common channel signalling option is selected (page
01H, address 1AH, bit 0, 64KCCS =1) for channel 16.
7
72
DSTo
Data ST-BUS Output. A 2.048 Mbit/s serial stream which contains the 30 PCM or
data channels received on the PCM 30 line.
8
73
DSTi
Data ST-BUS Input. A 2.048 Mbit/s serial stream which contains the 30 PCM or data
channels to be transmitted on the PCM 30 line.
9
74
DS/RD
Data/Read Strobe (Input).
In Motorola mode (DS), this input is the active low data strobe of the microprocessor
interface.
In Intel mode (RD), this input is the active low read strobe of the microprocessor
interface.
10
83
CS
Chip Select (Input). This active low input enables the non-multiplexed parallel
microprocessor interface of the MT9075B. When CS is set to high, the microprocessor
interface is idle and all bus I/O pins will be in a high impedance state.
11
84
RESET
RESET (Input). This active low input puts the MT9075B in a reset condition. RESET
should be set to high for normal operation. The MT9075B should be reset after power-
up. The RESET pin must be held low for a minimum of 1
sec. to reset the device
properly.
12
85
IRQ
Interrupt Request (Output). A low on this output pin indicates that an interrupt request
is presented. IRQ is an open drain output that should be connected to V
DD
through a
pull-up resistor. An active low CS signal is not required for this pin to function.
13 -
16
86-
89
D0 - D3
Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the
bidirectional data bus of the microprocessor interface (D0 is the least significant bit).
MT9075B
Preliminary Information
4
17
90
VSS
Negative Power Supply (Input). Digital ground.
18
91
IC
Internal Connection. Tie to V
SS
(Ground) for normal operation.
19
92
INT/MOT Intel/Motorola Mode Selection (Input). A high on this pin configures the processor
interface for the Intel parallel non-multiplexed bus type. A low configures the processor
interface for the Motorola parallel non-multiplexed type.
20
93
VDD
Positive Power Supply (Input). Digital supply (+5V
5%).
21 -
24
94-
97
D4 - D7
Data 4 to Data 7 (Three-state I/O). These signals combined with D0-D3 form the
bidirectional data bus of the microprocessor interface (D7 is the most significant bit).
25
98
R/W/WR Read/Write/Write Strobe (Input).
In Motorola mode (R/W), this input controls the direction of the data bus D[0:7] during
a microprocessor access. When R/W is high, the parallel processor is reading data
from the MT9075B. When low, the microprocessor is writing data to the MT9075B.
For Intel mode (WR), this active low write strobe configures the data bus lines as
output.
26 -
30
99,
8-11
AC0 -
AC4
Address/Control 0 to 4 (Inputs). Address and control inputs for the microprocessor
interface. AC0 is the least significant input.
31
12
GNDARx Receive Analog Ground (Input). Analog ground for the LIU receiver.
32
33
13
14
RTIP
RRING
Receive TIP and RING (Inputs). Differential inputs for the receive line signal - must be
transformer coupled (See Figure 4).
34
15
VDDARx Receive Analog Power Supply (Input). Analog supply for the LIU receiver (+5V
5%).
35
16
VDD
Positive Power Supply (Input). Digital supply (+5V
5%).
36
17
VSS
Negative Power Supply (Input). Digital ground.
37
18
IC
Internal Connection. Must be left open for normal operation.
38
19
IC
Internal Connection. Must be left open for normal operation.
39
20
RxDLCLK Receive Data Link Clock (Output). A gapped clock signal derived from a 2.048 Mbit/s
clock, available for an external device to clock in RxDL data (at 4, 8, 12, 16 or 20 kHz) on
the rising edge.
40
21
RxDL
Receive Data Link (Output). A 2.048 Mbit/s data stream containing received line data
after HDB3 decoding. This data is clocked out with the rising edge of E2o.
41
22
TxMF
Transmit Multiframe Boundary (Input). An active low input used to set the transmit
multiframe boundary (CAS or CRC multiframe). The MT9075B will generate its own
multiframe if this pin is held high. This input is usually pulled high for most applications.
42
23
RxMF
Receive Multiframe Boundary (Output). An output pulse delimiting the received
multiframe boundary. The next frame output on the data stream (DSTo) is basic frame
zero on the PCM 30 link. This receive multiframe signal can be related to either the
receive CRC multiframe (page 01H, address 10H, bit 6, MFSEL=1) or the receive
signalling multiframe (MFSEL=0).
43
24
BS/LS
System Bus Synchronous/Line Synchronous Selection (Input). If high, C4b and F0b
will be inputs; if low, C4b and F0b will be outputs.
44
32
E2o
2.048 MHz Extracted Clock (Output). The clock extracted from the received signal
and used internally to clock in data received on RTIP and RRING.
Pin Description (continued)
Pin #
Name
Description
PLCC MQFP
Preliminary Information
MT9075B
5
45
33
C4b
4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and
transmit serial PCM data of the MT9075B. In the free-run (BL/FR=0) or line synchronous
mode (BL/FR=1 and BS/LS=0) this signal is an output, while in the system bus
synchronous mode (BS/LS=1) this signal is an input clock.
46
34
F0b
Frame Pulse (Input/Output). This is the ST-BUS or GCI frame synchronization
signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the
PCM30 link. In the free-run (BL/FR=0) or loop synchronous mode (BL/FR=1 and BS/
LS=0) this signal is an output, while in the Bus Synchronous mode (BL/FR=1 and BS/
LS=0) this signal is an input. The GCI/ST-BUS selection is made under software control.
Page 02H, address 13H, bit 0, GCI/ST=1 selects GCI frame pulse; GCI/ST=0 selects ST-
BUS.
47
35
RxFP/
Rx64KCK
Receive Frame Pulse/Receive CCS Clock (Output). An 8kHz pulse signal, which is
low for one extracted clock period. This signal is synchronized to the receive PCM 30
basic frame boundary.
When 64KCCS (page 01H, address 1AH, bit 0) is set to 1, this pin outputs a 64 kHz clock
derived by dividing down the extracted 2.048 MHz clock. This clock is used to clock CCS
data out of pin CSTo in the CCS mode.
48
36
IC
Internal Connection. Must be left open for normal operation.
49
37
V
SS
Negative Power Supply (Input). Digital ground.
50
38
V
DD
Positive Power Supply (Input). Digital supply (+5V
5%).
51
39
VDD
ATx
Transmit Analog Power Supply (Input). Analog supply for the LIU transmitter (+5V
5%).
52
53
40
41
TTIP
TRING
Transmit TIP and RING (Outputs). Differential outputs for the transmit line signal - must
be transformer coupled (See Figure 4).
54
42
GND
ATx
Transmit Analog Ground (Input). Analog ground for the LIU transmitter.
55
43
Tdi
IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high.
56
44
Tdo
IEEE 1149.1 Test Data Output. If not used, this pin should be left unconnected.
57
45
Tms
IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled high.
58
46
Tclk
IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high.
59
47
Trst
IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low.
60
48
TAIS
Transmit Alarm Indication Signal (Input). An active low on this input causes the
MT9075B to transmit an AIS (all ones signal) on TTIP and TRING pins. TAIS should be
set to high for normal data transmission.
61
57
LOS
Loss of Signal or Synchronization (Output). When high, and LOS/LOF (page 02H
address 13H bit 2) is zero, this signal indicates that the receive portion of the MT9075B is
either not detecting an incoming signal (bit LLOS on page 03H address 18H is one) or is
detecting a loss of basic frame alignment condition (bit SYNC on page 03H address 10H
is one). If LOS/LOF=1, a high on this pin indicates a loss of signal condition.
62
58
IC
Internal Connection. Tie to V
SS
(Ground) for normal operation.
59
NC
No Connection. Leave open for normal operation.
63
60
IC
Internal Connection. Tie to V
SS
(Ground) for normal operation.
Pin Description (continued)
Pin #
Name
Description
PLCC MQFP
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