MT9041B

T1/E1 System Synchronizer

Features

Supports AT&T TR62411 and Bellcore
GR-1244-CORE Stratum 4 Enhanced and
Stratum 4 timing for DS1 Interfaces

Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 Interfaces

Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals

Provides C1.5, C2, C3, C4, C8 and C16 output
clock signals

Provides 3 different styles of 8 KHz framing
pulses

Attenuates wander from 1.9 Hz

Applications

Synchronization and timing control for
multitrunk T1 and E1 systems

ST-BUS clock and frame pulse sources

Description

The MT9041B T1/E1 System Synchronizer contains
a digital phase-locked loop (DPLL), which provides
timing and synchronization signals for multitrunk T1
and E1 primary rate transmission links.

The MT9041B generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.

The MT9041B is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE Stratum 4 Enhanced,
Stratum 4, and ETSI ETS 300 011. It will meet the
jitter tolerance, jitter transfer, intrinsic jitter, frequency
accuracy, capture range and phase change slope
requirements for these specifications.

Ordering Information

MT9041BP

28 Pin PLCC

-40 to +85

Figure 1 - Functional Block Diagram

Mode Select

Divider

Output

Interface

Circuit

FS1

FS2

RST

VDD

VSS

C3o

C1.5o

C2o

C4o

C8o

C16o

F0o

F8o

F16o

REF

OSCi

OSCo

Phase

Detector

Filter

DCO

Loop

DS5059

ISSUE 3

Septemner 1999

Advance Information

MT9041B

Advance Information

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

Ground. 0 Volts.

IC0

Internal Connect. Connect to Vss

No Connect. Connect to Vss

REF

Reference (TTL Input). PLL reference clock.

Positive Supply Voltage. +5V

nominal.

OSCo

Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 6. For clock oscillator operation, this pin is left
unconnected, see Figure 5.

OSCi

Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is
connected to a clock source, see Figure 5.

F16o

Frame Pulse ST-BUS 16.384Mb/s (CMO7S Output). This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 16.384Mb/s. See Figure 11.

F0o

Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.

F8o

Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high
framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS
operation at 8.192Mb/s. See Figure 11.

C1.5o

Clock 1.544MHz (CMOS Output). This output is used in T1 applications.

C3o

Clock 3.088MHz (CMOS Output). This optional output is used in T1 applications.

C2o

Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.

C4o

Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.

Ground. 0 Volts.

C8o

Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.

C16o

Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/
s.

Positive Supply Voltage. +5V

nominal.

8
9

VSS

IC0

REF

VDD

OSCo

OSCi

F16o

F0o
F8o

C1.5o

IC0

IC1

IC0

FS2

FS1

RST

12 13 14 15 16 17 18

C2o

VSS

C8o

C16

VDD

C4o

C3o

MT9041B

Advance Information

MT9041B

IC0

Internal Connect. Connect to Vss

IC1

Internal Connect. Leave open Circuit

IC0

Internal Connect. Connect to Vss

IC0

Internal Connect. Connect to Vss

Mode/Control Select (TTL Input). This pin, determines the device's state (Normal, or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.

IC0

Internal Connect. Connect to Vss

IC0

Internal Connect. Connect to Vss

FS2

Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three
possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the REF input. See
Table 1.

FS1

Frequency Select 1 (TTL Input). See pin description for FS2.

RST

Reset (Schmitt Input). A logic low at this input resets the MT9041B. To ensure proper
operation, the device must be reset after reference signal frequency changes and power-up.
The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame
and clock outputs are at logic high. Following a reset, the input reference source and output
clocks and frame pulses are phase aligned as shown in Figure 10.

Pin Description (continued)

Pin #

Name

Description

Functional Description

The MT9041B is a System Synchronizer, providing
timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital
Transmission links.

Figure 1 is a functional block diagram which is
described in the following sections.

Frequency Select MUX Circuit

The MT9041B operates on the falling edges of one
of three possible input reference frequencies (8kHz,
1.544MHz or 2.048MHz). The frequency select
inputs (FS1 and FS2) determine which of the three
frequencies may be used at the reference input
(REF). A reset (RST) must be performed after every
frequency select input change. Operation with FS1
and FS2 both at logic low is reserved and must not
be used. See Table 1.

Table 1 - Input Frequency Selection

Digital Phase Lock Loop (DPLL)

The DPLL of the MT9041B consists of a Phase
Detector, Limiter, Loop Filter, Digitally Controlled
Oscillator, and a Control Circuit (see Figure 3).

Phase Detector - the Phase Detector compares the
primary reference signal (REF) with the feedback
signal from the Frequency Select MUX circuit, and
provides an error signal corresponding to the phase
difference between the two. This error signal is
passed to the Limiter circuit. The Frequency Select
MUX allows the proper feedback signal to be
externally selected (e.g., 8kHz, 1.544MHz or
2.048MHz).

Limiter - the Limiter receives the error signal from
the Phase Detector and ensures that the DPLL
responds to all input transient conditions with a
maximum output phase slope of 5ns per 125us. This

FS2

FS1

Input Frequency

Reserved

8kHz

1.544MHz

2.048MHz

MT9041B

Advance Information

is well within the maximum phase slope of 7.6ns per
125us or 81ns per 1.326ms specified by Bellcore
GR-1244-CORE Stratum 4E.

Loop Filter - the Loop Filter is similar to a first order
low pass filter with a 1.9 Hz cutoff frequency for all
three reference frequency selections (8kHz,
1.544MHz or 2.048MHz). This filter ensures that the
jitter transfer requirements in ETS 300 011 and AT&T
TR62411 are met.

Control Circuit - the Control Circuit sets the mode
of the DPLL. The two possible modes are Normal
and Freerun.

Digitally Controlled Oscillator (DCO) - the DCO
receives the limited and filtered signal from the Loop
FIlter, and based on its value, generates a
corresponding digital output signal. The
synchronization method of the DCO is dependent on
the state of the MT9041B.

In Normal Mode, the DCO provides an output signal
which is frequency and phase locked to the selected
input reference signal.

In Freerun Mode, the DCO is free running with an
accuracy equal to the accuracy of the OSCi 20MHz
source.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output
Interface Circuit to provide the output signals shown
in Figure 4. The Output Interface Circuit uses two
Tapped Delay Lines followed by a T1 Divider Circuit
and an E1 Divider Circuit to generate the required
output signals.

Two tapped delay lines are used to generate a
16.384MHz and a 12.352MHz signals.

The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and three frame pulse

outputs. The C8o,

C4o and C2o clocks are

generated by simply dividing the C16o clock by two,
four and eight respectively. These outputs have a
nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384MHz signal to
generate two clock outputs. C1.5o and C3o are
generated by dividing the internal C12 clock by four
and eight respectively. These outputs have a nominal
50% duty cycle.

Figure 4 - Output Interface Circuit Block

Diagram

The frame pulse outputs (F0o, F8o, F16o) are
generated directly from the C16 clock.

The T1 and E1 signals are generated from a
common DPLL signal. Consequently, the clock
outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o and
F16o are locked to one another for all operating
states, and are also locked to the selected input
reference in Normal Mode. See Figures 11 and 12.

Tapped

Delay

Line

From

DPLL

T1 Divider

E1 Divider

16MHz

12MHz

C3o

C1.5o

C2o
C4o
C8o
C16o
F0o
F8o
F16o

Tapped

Delay

Line

Figure 3 - DPLL Block Diagram

Control

Circuit

Feedback Signal

from

Frequency Select MUX

DPLL Reference

Output Interface Circuit

REF Reference

Limiter

Loop Filter

Digitally

Controlled

Oscillator

Phase

Detector

Advance Information

MT9041B

All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g. 30pF) loads.

Master Clock

The MT9041B can use either a clock or crystal as
the master timing source. For recommended master
timing circuits, see the Applications - Master Clock
section.

Control and Modes of Operation

The MT9041B can operate either in Normal or
Freerun modes.

As shown in Table 2, pin MS selects between
NORMAL and FREERUN modes.

Normal Mode

Normal Mode is typically used when a slave clock
source synchronized to the network is required.

In Normal Mode, the MT9041B provides timing
(C1.5o, C2o, C3o, C4o, C8o and C16o) and frame
synchronization (F0o, F8o, F16o) signals, which are
synchronized to reference input (REF). The input
reference signal may have a nominal frequency of
8kHz, 1.544MHz or 2.048MHz.

From a reset condition, the MT9041B will take up to
25 seconds for the output signal to be phase locked
to the reference.

The reference frequencies are selected by the
frequency control pins FS2 and FS1 as shown in
Table 1.

Freerun Mode

Freerun Mode is typically used when a master clock
source is required, or immediately following system
power-up before network synchronization is
achieved.

In Freerun Mode, the MT9041B provides timing and
synchronization signals which are based on the
master clock frequency (OSCi) only, and are not
synchronized to the reference signal (REF).

The accuracy of the output clock is equal to the
accuracy of the master clock (OSCi). So if a

32ppm

output clock is required, the master clock must also
be

32ppm. See Applications - Crystal and Clock

Oscillator sections.

MT9041B Measures of Performance

The following are some synchronizer performance
indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the
synchronizing circuit and is measured at its output. It
is measured by applying a reference signal with no
jitter to the input of the device, and measuring its
output jitter. Intrinsic jitter may also be measured
when the device is in a non-synchronizing mode, i.e.
free running mode, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with
various bandlimiting filters depending on the
applicable standards.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to
operate properly (i.e., remain in lock and or regain
lock), in the presence of large jitter magnitudes at
various jitter frequencies applied to its reference.
The applied jitter magnitude and jitter frequency
depends on the applicable standards.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the
magnitude of jitter at the output of a device for a
given amount of jitter at the input of the device. Input
jitter is applied at various amplitudes and
frequencies, and output jitter is measured with
various filters depending on the applicable
standards.

Description of Operation

NORMAL

FREERUN

Table 2 - Operating Modes

MT9041B

Advance Information

For the MT9041B, two internal elements determine
the jitter attenuation. This includes the internal 1.9Hz
low pass loop filter and the phase slope limiter. The
phase slope limiter limits the output phase slope to
5ns/125us. Therefore, if the input signal exceeds this
rate, such as for very large amplitude low frequency
input jitter, the maximum output phase slope will be
limited (i.e., attenuated) to 5ns/125us.

The MT9041B has nine outputs with three possible
input frequencies for a total of 27 possible jitter
transfer functions. However, the data sheet section
on AC Electrical Characteristics - Jitter Transfer
specifies transfer values for only three cases, 8kHz
to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to
2.048MHz. Since all outputs are derived from the
same signal, these transfer values apply to all
outputs.

It should be noted that 1UI at 1.544MHz is 644ns,
which is not equal to 1UI at 2.048MHz, which is
488ns. Consequently, a transfer value using different
input and output frequencies must be calculated in
common units (e.g. seconds) as shown in the
following example.

What is the T1 and E1 output jitter when the T1 input
jitter is 20UI (T1 UI Units) and the T1 to T1 jitter
attenuation is 18dB?

Using the above method, the jitter attenuation can be
calculated for all combinations of inputs and outputs
based on the three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all
combinations of inputs (8kHz, 1.544MHz, 2.048MHz)
and outputs (8kHz, 1.544MHz, 2.048MHz,
4.096MHz, 8.192MHz, 16.384MHz) for a given input
signal (jitter frequency and jitter amplitude) are the
same.

Since intrinsic jitter is always present, jitter
attenuation will appear to be lower for small input
jitter signals than for large ones. Consequently,
accurate jitter transfer function measurements are

usually made with large input jitter signals (e.g. 75%
of the specified maximum jitter tolerance).

Frequency Accuracy

Frequency accuracy is defined as the absolute
tolerance of an output clock signal when it is not
locked to an external reference, but is operating in a
free running mode. For the MT9041B, the Freerun
accuracy is equal to the Master Clock (OSCi)
accuracy.

Capture Range

Also referred to as pull-in range. This is the input
frequency range over which the synchronizer must
be able to pull into synchronization. The MT9041B
capture range is equal to

230ppm minus the

accuracy of the master clock (OSCi). For example, a

32ppm master clock results in a capture range of

198ppm.

Lock Range

This is the input frequency range over which the
synchronizer must be able to maintain
synchronization. The lock range is equal to the
capture range for the MT9041B.

Phase Slope

Phase slope is measured in seconds per second and
is the rate at which a given signal changes phase
with respect to an ideal signal. The given signal is
typically the output signal. The ideal signal is of
constant frequency and is nominally equal to the
value of the final output signal or final input signal.

Phase Continuity

Phase continuity is the phase difference between a
given timing signal and an ideal timing signal at the
end of a particular observation period. Usually, the
given timing signal and the ideal timing signal are of
the same frequency. Phase continuity applies to the
output of the synchronizer after a signal disturbance
due to a reference switch or a mode change. The
observation period is usually the time from the
disturbance, to just after the synchronizer has settled
to a steady state.

In the case of the MT9041B, the output signal phase
continuity is maintained to within

5ns at the

instance (over one frame) of mode changes. The
total phase shift may accumulate up to

200ns over

OutputT 1

InputT 1

-------

OutputT 1

---------

2.5UI T 1

(

)

OutputE1

OutputT 1

644ns

(

)

488ns

(

)

-------------------

3.3UI T 1

(

)

OutputE1

OutputT 1

1UIT 1

(

)

1UIE1

(

)

----------------------

Advance Information

MT9041B

many frames. The rate of change of the

200ns

phase shift is limited to a maximum phase slope of
approximately 5ns/125us. This meets the Bellcore
GR-1244-CORE maximum phase slope requirement
of 7.6ns/125us (81ns/1.326ms).

Phase Lock Time

This is the time it takes the synchronizer to phase
lock to the input signal. Phase lock occurs when the
input signal and output signal are not changing in
phase with respect to each other (not including jitter).

Lock time is very difficult to determine because it is
affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter

Although a short lock time is desirable, it is not
always possible to achieve due to other synchronizer
requirements. For instance, better jitter transfer
performance is achieved with a lower frequency loop
filter which increases lock time. And better (smaller)
phase slope performance (limiter) results in longer
lock times. The MT9041B loop filter and limiter were
optimized to meet the AT&T TR62411 jitter transfer
and phase slope requirements. Consequently, phase
lock time, which is not a standards requirement, may
be longer than in other applications. See AC
Electrical Characteristics - Performance for
maximum phase lock time.

MT9041B and Network Specifications

The MT9041B fully meets all applicable PLL
requirements (intrinsic jitter, jitter tolerance, jitter
transfer, frequency accuracy, capture range and
phase change slope) for the following specifications.

1. Bellcore GR-1244-CORE Issue 1, June 1995 for

Stratum 4 Enhanced and Stratum 4

2. AT&T TR62411 (DS1) December 1990 for Stratum

4 Enhanced and Stratum 4

3. ANSI T1.101 (DS1) February 1994 for Stratum 4

Enhanced and Stratum 4

4. ETSI 300 011 (E1) April 1992 forSingle Access

and Multi Access

5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993

Applications

This section contains MT9041B application specific
details for clock and crystal operation, reset
operation and power supply decoupling.

Master Clock

The MT9041B can use either a clock or crystal as
the master timing source.

In Freerun Mode, the frequency tolerance at the
clock outputs is identical to the frequency tolerance
of the source at the OSCi pin. For applications not
requiring an accurate Freerun Mode, tolerance of the
master timing source may be

100ppm. For

applications requiring an accurate Freerun Mode,
such as Bellcore GR-1244-CORE, the tolerance of
the master timing source must be no greater than

32ppm.

Another consideration in determining the accuracy of
the master timing source is the desired capture
range. The sum of the accuracy of the master timing
source and the capture range of the MT9041B will
always equal

230ppm. For example, if the master

timing source is

100ppm, then the capture range

will be

130ppm.

Clock Oscillator - when selecting a Clock Oscillator,
numerous parameters must be considered. These
include absolute frequency, frequency change over
temperature, output rise and fall times, output levels
and duty cycle. See AC Electrical Characteristics.

Figure 5 - Clock Oscillator Circuit

+5V

20MHz OUT

GND

0.1uF

+5V

OSCo

MT9041B

OSCi

No Connection

MT9041B

Advance Information

For applications requiring

32ppm clock accuracy,

the following clock oscillator module may be used.

CTS CXO-65-HG-5-C-20.0MHz

Frequency:

20MHz

Tolerance:

25ppm 0C to 70C

Rise & Fall Time:

8ns (0.5V 4.5V 50pF)

Duty Cycle:

45% to 55%

The output clock should be connected directly (not
AC coupled) to the OSCi input of the MT9041B, and
the OSCo output should be left open as shown in
Figure 5.

Crystal Oscillator - Alternatively, a Crystal
Oscillator may be used. A complete oscillator circuit
made up of a crystal, resistor and capacitors is
shown in Figure 6.

Figure 6 - Crystal Oscillator Circuit

The accuracy of a crystal oscillator depends on the
crystal tolerance as well as the load capacitance
tolerance. Typically, for a 20MHz crystal specified
with a 32pF load capacitance, each 1pF change in
load capacitance contributes approximately 9ppm to
the frequency deviation. Consequently, capacitor
tolerances, and stray capacitances have a major
effect on the accuracy of the oscillator frequency.

The trimmer capacitor shown in Figure 6 may be
used to compensate for capacitive effects. If
accuracy is not a concern, then the trimmer may be
removed, the 39pF capacitor may be increased to
56pF, and a wider tolerance crystal may be
substituted.

The crystal should be a fundamental mode type - not
an overtone. The fundamental mode crystal permits
a simpler oscillator circuit with no additional filter
components and is less likely to generate spurious
responses. The crystal specification is as follows.

Frequency:

20MHz

Tolerance:

As required

Oscillation Mode:

Fundamental

Resonance Mode:

Parallel

Load Capacitance:

32pF

Maximum Series Resistance:

Approximate Drive Level:

1mW

e.g., CTS R1027-2BB-20.0MHZ

(

20ppm absolute,

6ppm 0C to 50C, 32pF, 25

)

Reset Circuit

A simple power up reset circuit with about a 50us
reset low time is shown in Figure 7. Resistor R

is for

protection only and limits current into the RST pin
during power down conditions. The reset low time is
not critical but should be greater than 300ns.

Figure 7 - Power-Up Reset Circuit

Power Supply Decoupling

The MT9041B has two VDD (+5V) pins and two VSS
(GND) pins. Power and decoupling capacitors should
be included as shown in Figure 8.

Figure 8 - Power Supply Decoupling

OSCo

56pF

39pF

3-50pF

20MHz

MT9041B

OSCi

100

1uH

1uH inductor: may improve stability and is optional

+5V

RST

10nF

10k

MT9041B

0.1uF

MT9041B

0.1uF

Advance Information

MT9041B

Multiple E1 Reference Sources with MT9041B

In this example 8 E1 link framers (MT9074) are
connected to a common system backplane clock
using the MT9041B. Each of the extracted clocks
E1.5o go to a mux which selects one of the eight
input clocks as the reference to the MT9041B. The
clock choice is made by a controller using the loss of
signal pin LOS from the MT9074s to qualify potential
references. In the event of loss of signal by one of
the framers, an interrupt signals the controller to
choose a different reference clock. Disturbances in
the generated system backplane clocks C4b and F0b
are minimized by the phase slope limitations of the
MT9041B PLL. This ensures system integrity and
minimizes the effect of clock switchover on
downstream trunks.

Figure 9 - Multiple E1 Reference Sources with MT9041B

10nF

MT9041B

F0o

C4o

FS1
FS2

OSCi

Out

RST

10k

MT9074

F0i

C4b

TTIP

TRING

RTIP

RRING

LOS

E1.5o

20MHz

32ppm

CLOCK

+ 5V

Link 0

MT9074

F0i

C4b

TTIP

TRING

RTIP

RRING

LOS

E1.5o

Links 1-7

REF

OUT

IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7

1 TO 8

MUX

20MHz

To Controller

Interrupt

To Controller

Interrupt

MT9041B

Advance Information

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

Absolute Maximum Ratings*

- Voltages are with respect to ground (V

) unless otherwise stated.

Parameter

Symbol

Min

Max

Units

Supply voltage

-0.3

7.0

Voltage on any pin

-0.3

+0.3

Current on any pin

Storage temperature

-55

125

PLCC package power dissipation

900

Recommended Operating Conditions -

Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Supply voltage

4.5

5.0

5.5

Operating temperature

-40

DC Electrical Characteristics* -

Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Supply current with:OSCi = 0V

DDS

0.5

Outputs unloaded

OSCi = Clock

Outputs unloaded

TTL high-level input voltage

2.0

TTL low-level input voltage

0.8

CMOS high-level input voltage

CIH

0.7V

OSCi

CMOS low-level input voltage

CIL

0.3V

OSCi

Schmitt high-level input voltage

SIH

2.3

RST

Schmitt low-level input voltage

SIL

0.8

RST

Schmitt hysteresis voltage

HYS

0.4

RST

Input leakage current

-50

+50

or 0V

High-level output voltage

0.8V

=4mA

Low-level output voltage

0.2V

=4mA

Advance Information

MT9041B

See "Notes" following AC Electrical Characteristics tables.

* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Timing for input and output signals is based on the worst Chislehurst of the combination of TTL and CMOS thresholds.
* See Figure 10.

Figure 10 - Timing Parameter Measurement Voltage Levels

AC Electrical Characteristics - Performance

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Freerun Mode accuracy with OSCi at: 0ppm

-0

ppm

2-5

32ppm

-32

+32

ppm

2-5

100ppm

-100

+100

ppm

2-5

Capture range with OSCi at: 0ppm

-230

+230

ppm

1,3-5,37

32ppm

-198

+198

ppm

1,3-5, 37

100ppm

-130

+130

ppm

1,3-5,37

Phase lock time

1, 3-11

Output phase continuity with:

mode switch to Normal

200

1-11

mode switch to Freerun

200

1, 3-11

Output phase slope

us/s

1-11, 24

AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* -

Voltages are

with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Schmitt

TTL

CMOS

Units

Threshold Voltage

1.5

0.5V

Rise and Fall Threshold Voltage High

2.3

2.0

0.7V

Rise and Fall Threshold Voltage Low

0.8

0.3V

IRF,

ORF

Timing Reference Points

ALL SIGNALS

IRF,

ORF

MT9041B

Advance Information

See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - Input/Output Timing

Characteristics

Sym

Min

Max

Units

Reference input pulse width high or low

100

Reference input rise or fall time

IRF

8kHz reference input to F8o delay

R8D

-21

1.544MHz reference input to F8o delay

R15D

337

363

2.048MHz reference input to F8o delay

R2D

222

238

F8o to F0o delay

F0D

110

134

F16o setup to C16o falling

F16S

F16o hold from C16o rising

F16H

F8o to C1.5o delay

C15D

-51

-37

F8o to C3o delay

C3D

-51

-37

F8o to C2o delay

C2D

-13

F8o to C4o delay

C4D

-13

F8o to C8o delay

C8D

-13

F8o to C16o delay

C16D

-13

C1.5o pulse width high or low

C15W

309

339

C3o pulse width high or low

C3W

149

175

C2o pulse width high or low

C2W

230

258

C4o pulse width high or low

C4W

111

133

C8o pulse width high or low

C8W

C16o pulse width high or low

C16WL

F0o pulse width low

F0WL

230

258

F8o pulse width high

F8WH

111

133

F16o pulse width low

F16WL

Output clock and frame pulse rise or fall time

ORF

Input Controls Setup Time

100

Input Controls Hold Time

100

MT9041B

Advance Information

Figure 13 - Input Controls Setup and Hold Timing

See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - Intrinsic Jitter Unfiltered

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Intrinsic jitter at F8o (8kHz)

0.0002

UIpp

1-11,18-21,25

Intrinsic jitter at F0o (8kHz)

0.0002

UIpp

1-11,18-21,25

Intrinsic jitter at F16o (8kHz)

0.0002

UIpp

1-11,18-21,25

Intrinsic jitter at C1.5o (1.544MHz)

0.030

UIpp

1-11,18-21,26

Intrinsic jitter at C2o (2.048MHz)

0.040

UIpp

1-11,18-21,27

Intrinsic jitter at C3o (3.088MHz)

0.060

UIpp

1-11,18-21,28

Intrinsic jitter at C4o (4.096MHz)

0.080

UIpp

1-11,18-21,29

Intrinsic jitter at C8o (8.192MHz)

0.160

UIpp

1-11,18-21,30

Intrinsic jitter at C16o (16.384MHz)

0.320

UIpp

1-11,18-21,33

AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Intrinsic jitter (4Hz to 100kHz filter)

0.015

UIpp

1-11,18-21,26

Intrinsic jitter (10Hz to 40kHz filter)

0.010

UIpp

1-11,18-21,26

Intrinsic jitter (8kHz to 40kHz filter)

0.010

UIpp

1-11,18-21,26

Intrinsic jitter (10Hz to 8kHz filter)

0.005

UIpp

1-11,18-21,26

AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Intrinsic jitter (4Hz to 100kHz filter)

0.015

UIpp

1-11, 18-21, 27

Intrinsic jitter (10Hz to 40kHz filter)

0.010

UIpp

1-11, 18-21, 27

Intrinsic jitter (8kHz to 40kHz filter)

0.010

UIpp

1-11, 18-21, 27

Intrinsic jitter (10Hz to 8kHz filter)

0.005

UIpp

1-11, 18-21, 27

F8o

Advance Information

MT9041B

See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Jitter attenuation for 1Hz@0.01UIpp input

1,3,6-11,18-19,21,25,32

Jitter attenuation for 1Hz@0.54UIpp input

1,3,6-11,18-19,21,25,32

Jitter attenuation for 10Hz@0.10UIpp
input

1,3,6-11,18-19,21,25,32

Jitter attenuation for 60Hz@0.10UIpp
input

1,3,6-11,18-19,21,25,32

Jitter attenuation for 300Hz@0.10UIpp
input

1,3,6-11,18-19,21,25,32

Jitter attenuation for 3600Hz@0.005UIpp
input

1,3,6-11,18-19,21,25,32

AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Jitter attenuation for 1Hz@20UIpp input

1,4,6-11,18-19,21,26,32

Jitter attenuation for 1Hz@104UIpp input

1,4,6-11,18-19,21,26,32

Jitter attenuation for 10Hz@20UIpp input

1,4,6-11,18-19,21,26,32

Jitter attenuation for 60Hz@20UIpp input

1,4,6-11,18-19,21,26,32

Jitter attenuation for 300Hz@20UIpp input

1,4,6-11,18-19,21,26,32

Jitter attenuation for 10kHz@0.3UIpp input

1,4,6-11,18-19,21,26,32

Jitter attenuation for 100kHz@0.3UIpp
input

1,4,6-11,18-19,21,26,32

MT9041B

Advance Information

See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 2.048MHz Input to 2.048MHz Output Jitter Transfer

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Jitter at output for 1Hz@3.00UIpp input

2.9

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.09

UIpp

1-5,6-11,18-19, 21,27,33

Jitter at output for 3Hz@2.33UIpp input

1.3

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.10

UIpp

1-5,6-11,18-19,21,2733

Jitter at output for 5Hz@2.07UIpp input

0.80

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.10

UIpp

1-5,6-11,18-19, 21,27,33

Jitter at output for 10Hz@1.76UIpp input

0.40

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.10

UIpp

1-5,6-11,18-19, 21,27,33

Jitter at output for 100Hz@1.50UIpp input

0.06

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.05

UIpp

1-5,6-11,18-19, 21,27,33

Jitter at output for 2400Hz@1.50UIpp input

0.04

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.03

UIpp

1-5,6-11,18-19,21,27,33

Jitter at output for 100kHz@0.20UIpp input

0.04

UIpp

1,5,6-11,18-19,21,27,32

with 40Hz to 100kHz filter

0.02

UIpp

1-5,6-11,18-19,21,27,33

AC Electrical Characteristics - 8kHz Input Jitter Tolerance

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Jitter tolerance for 1Hz input

0.80

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 5Hz input

0.70

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 20Hz input

0.60

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 300Hz input

0.20

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 400Hz input

0.15

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 700Hz input

0.08

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 2400Hz input

0.02

UIpp

1,3,6-11,18-19,21-23,25

Jitter tolerance for 3600Hz input

0.01

UIpp

1,3,6-11,18-19,21-23,25

Advance Information

MT9041B

See "Notes" following AC Electrical Characteristics tables.

AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Jitter tolerance for 1Hz input

150

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 5Hz input

140

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 20Hz input

130

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 300Hz input

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 400Hz input

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 700Hz input

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 2400Hz input

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 10kHz input

UIpp

1,4,6-11,18-19,21-23,26

Jitter tolerance for 100kHz input

0.5

UIpp

1,4,6-11,18-19,21-23,26

AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance

Characteristics

Sym

Min

Max

Units

Conditions/Notes

Jitter tolerance for 1Hz input

150

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 5Hz input

140

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 20Hz input

130

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 300Hz input

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 400Hz input

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 700Hz input

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 2400Hz input

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 10kHz input

UIpp

1,5,6-11,18-19,21-23,27

Jitter tolerance for 100kHz input

UIpp

1,5,6-11,18-19,21-23,27

AC Electrical Characteristics - OSCi 20MHz Master Clock Input

Characteristics

Sym

Min

Typ

Max

Units

Conditions/Notes

Frequency accuracy
(20 MHz nominal)

-0

ppm

15,18

-32

+32

ppm

16,19

-100

+100

ppm

17,20

Duty cycle

Rise time

Fall time

MT9041B

Advance Information

Notes:

Voltages are with respect to ground (V

) unless otherwise stated.

Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels

1. Normal Mode selected.
2. Freerun Mode selected.
3. 8kHz Frequency Mode selected.
4. 1.544MHz Frequency Mode selected.
5. 2.048MHz Frequency Mode selected.
6. Master clock input OSCi at 20MHz

0ppm.

7. Master clock input OSCi at 20MHz

32ppm.

8. Master clock input OSCi at 20MHz

100ppm.

9. Selected reference input at

0ppm.

10. Selected reference input at

32ppm.

11. Selected reference input at

100ppm.

12. For Freerun Mode of

0ppm.

13. For Freerun Mode of

32ppm.

14. For Freerun Mode of

100ppm.

15. For capture range of

230ppm.

16. For capture range of

198ppm.

17. For capture range of

130ppm.

18. 25pF capacitive load.
19. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp
where1UIpp=1/20MHz.
20. Jitter on reference input is less than 7nspp.
21. Applied jitter is sinusoidal.
22. Minimum applied input jitter magnitude to regain synchronization.
23. Loss of synchronization is obtained at slightly higher input
jitter amplitudes.
24. Within 10ms of the state, reference or input change.
25. 1UIpp = 125us for 8kHz signals.
26. 1UIpp = 648ns for 1.544MHz signals.
27. 1UIpp = 488ns for 2.048MHz signals.
28. 1UIpp = 323ns for 3.088MHz signals.
29. 1UIpp = 244ns for 4.096MHz signals.
30. 1UIpp = 122ns for 8.192MHz signals.
31. 1UIpp = 61ns for 16.384MHz signals.
32. No filter.
33. 40Hz to 100kHz bandpass filter.
34. With respect to reference input signal frequency.
35. After a RST or TRST.
36. Master clock duty cycle 40% to 60%.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT9041B