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Электронный компонент: MT8809

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3-21
3-21
MT8809
8 x 8 Analog Switch Array
Features
Internal control latches and address decoder
Short setup and hold times
Wide operating voltage: 4.5V to 13.2V
12Vpp analog signal capability
R
ON
65
max. @ V
DD
=12V, 25C
R
ON
10
@ V
DD
=12V, 25C
Full CMOS switch for low distortion
Minimum feedthrough and crosstalk
Low power consumption ISO-CMOS technology
Internal pull-up resistor for RESET pin
Applications
Key systems
PBX systems
Mobile radio
Test equipment /instrumentation
Analog/digital multiplexers
Audio/Video switching
Description
The Mitel MT8809 is fabricated in MITEL's ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 8 array
of crosspoint switches along with a 6 to 64 line
decoder and latch circuits. Any one of the 64
switches can be addressed by selecting the
appropriate six address bits. The selected switch can
be turned on or off by applying a logical one or
zero to the DATA input. Chip Select (CS) allows the
crosspoint array to be cascaded for matrix
expansion.
Ordering Information
MT8809AC
28 Pin Ceramic DIP
MT8809AE
28 Pin Plastic DIP
MT8809AP
28 Pin PLCC
-
40 to 85C
Figure 1 - Functional Block Diagram
6 to 64
Decoder
Latches
8 x 8
Switch
Array
AX0
AX1
AY0
AY1
AY2
STROBE
DATA RESET
VDD
VSS
Xi I/O
(i=0-7)
Yi I/O (i=0-7)
1
1
64
64






AX2
CS
ISSUE 2
November 1988
ISO-CMOS
MT8809
ISO-CMOS
3-22
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
AY2
AY2 Address Line (Input).
2
STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes low and DATA must be stable on the rising edge of STROBE.
Active Low.
3
CS
Chip Select (Input): this is used to select the device. Active Low.
4
DATA
DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
5
V
SS
Ground Reference.
6-9
X0, X2,
X4, X6
X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and
X6 rows of the switch array.
10
RESET
Master RESET (Input): this is used to turn off all switches regardless of the condition of
CS. A 100k
internal pull-up resistor is also provided. This can be used in conjunction
with a 0.1F capacitor (connected to the RESET pin) to perform power-on reset of the
device. Active Low.
11-18
Y7 - Y0
Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the
switch array.
19
V
DD
Positive Power Supply.
20-23
X7, X5,
X3, X1
X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and
X1 rows of the switch array.
24-26
AX0-AX2 AX0 - AX2 Address Lines (Inputs).
27, 28
AY0, AY1 AY0 and AY1 Address Lines (Inputs).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
AY2
STROBE
CS
DATA
VSS
X0
X2
X4
X6
RESET
Y7
Y6
Y5
Y4
AY1
AY0
AX2
AX1
AX0
X1
X3
X5
X7
VDD
Y0
Y1
Y2
Y3
28 PIN CERDIP/PLASTIC DIP
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
D
A
T
A
AX1
AX0
X1
X3
X5
X7
VDD
VSS
X0
X2
X4
X6
RESET
Y7
Y
1
3
2
1
2
8
2
7
2
6
1
2
1
3
1
4
1
5
1
6
1
7
1
8
C
S
S
T
R
O
B
E
A
Y
2
A
Y
1
A
Y
0
A
X
2
Y
6
Y
5
Y
4
Y
3
Y
2
Y
0
28 PIN PLCC
ISO-CMOS
MT8809
3-23
Functional Description
The MT8809 is an analog switch matrix with an array
size of 8 x 8. The switch array is arranged such that
there are 8 columns by 8 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will interconnect any X I/O with any Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 64
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0-AX2). Data is
presented to the memory on the DATA input. Data is
asynchronously written into memory whenever both
the CS (Chip Select) and STROBE inputs are low
and are latched on the rising edge of STROBE. A
logical "1" written into a memory cell turns the
corresponding crosspoint switch on and a logical "0"
turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are
altered when data is written into memory. The
remaining switches retain their previous states. Any
combination of X and Y inputs/outputs can be
interconnected by establishing appropriate patterns
in the control memory. A logical "0" on the RESET
input will asynchronously return all memory
locations to logical "0" turning off all crosspoint
switches regardless of whether CS is high or low.
Address Decode
The six address inputs along with the STROBE and
CS (Chip Select) are logically ANDed to form an
enable signal for the resettable transparent latches.
The DATA input is buffered and is used as the input
to all latches. To write to a location, RESET must be
high and CS must go low while the address and data
are set up. Then the STROBE input is set low and
then high causing the data to be latched. The data
can be changed while STROBE is low, however, the
corresponding switch will turn on and off in
accordance with the DATA input. DATA must be
stable on the rising edge of STROBE in order for
correct data to be written to the latch.
MT8809
ISO-CMOS
3-24
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
DC Electrical Characteristics are over recommended temperature range.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings
*
- Voltages are with respect to V
SS
unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
Supply Voltage
V
DD
V
SS
-0.3
-0.3
15.0
V
DD
+0.3
V
V
2
Analog Input Voltage
V
INA
-0.3
V
DD
+0.3
V
3
Digital Input Voltage
V
IN
V
SS
-0.3
V
DD
+0.3
V
4
Current on any I/O Pin
I
15
mA
5
Storage Temperature
T
S
-65
+150
C
6
Package Power Dissipation
PLASTIC DIP
CERDIP
P
D
P
D
0.6
1.0
W
W
Recommended Operating Conditions
- Voltages are with respect to V
SS
unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Operating Temperature
T
O
-40
25
85
C
2
Supply Voltage
V
DD
4.5
13.2
V
3
Analog Input Voltage
V
INA
V
SS
V
DD
V
4
Digital Input Voltage
V
IN
V
SS
V
DD
V
DC Electrical Characteristics
-
Voltages are with respect to V
SS
=0V, V
DD
=12V unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Quiescent Supply Current
I
DD
1
100
A
All digital inputs at V
IN
=V
SS
V
DD
except RESET = V
DD.
120
400
A
All digital inputs at V
IN
=V
SS
or
V
DD
except RESET = V
SS.
0.5
1.6
mA
All digital inputs at V
IN
=2.4V,
V
DD
=5.0V
5
15
mA
All digital inputs at V
IN
=3.4V
2
Off-state Leakage Current
(See G.9 in Appendix)
I
OFF
1
500
nA
IV
Xi
- V
Yj
I = V
DD
- V
SS
See Appendix, Fig. A.1
3
Input Logic "0" level
V
IL
0.8
V
4
Input Logic "1" level
V
IH
3.0
V
6
Input Leakage (digital pins)
I
LEAK
0.1
10
A
All digital inputs at V
IN
= V
SS
or V
DD;
RESET = V
DD
DC Electrical Characteristics- Switch Resistance
- V
DC
is the external DC offset applied at the analog I/O pins.
Characteristics
Sym
25C
70C
85C
Units
Test Conditions
Typ
Max
Typ
Max
Typ
Max
1 On-state
V
DD
=12V
Resistance V
DD
=10V
V
DD
= 5V
(See G.1, G.2, G.3 in
Appendix)
R
ON
45
55
120
65
75
185
75
85
215
80
90
225
V
SS
=0V,V
DC
=V
DD
/2,
IV
Xi
-V
Yj
I = 0.4V
See Appendix, Fig. A.2
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
R
ON
5
10
10
10
V
DD
=12V, V
SS
=0,
V
DC
=V
DD
/2,
IV
Xi
-V
Yj
I = 0.4V
See Appendix, Fig. A.2
ISO-CMOS
MT8809
3-25
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Q
Refer to Appendix, Fig. A.7 for test circuit.
AC Electrical Characteristics
- Crosspoint Performance
- V
DC
is the external DC offset at the analog I/O pins.
Voltages are with respect to V
DD
=5V, V
DC
=0V, V
SS
=-7V, unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Switch I/O Capacitance
C
S
20
pF
f=1 MHz
2
Feedthrough Capacitance
C
F
0.2
pF
f=1 MHz
3
Frequency Response
Channel "ON"
20LOG(V
OUT
/V
Xi
)=-3dB
F
3dB
45
MHz
Switch is "ON"; V
INA
= 2Vpp
sinewave; R
L
= 1k
See Appendix, Fig. A.3
4
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD
0.01
%
Switch is "ON"; V
INA
= 2Vpp
sinewave f= 1kHz
;
R
L
=1k
5
Feedthrough
Channel "OFF"
Feed.=20LOG (V
OUT
/V
Xi
)
(See G.8 in Appendix)
FDT
-95
dB
All Switches "OFF"; V
INA
=
2Vpp sinewave f= 1kHz;
R
L
= 1k
.
See Appendix, Fig. A.4
6
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (V
Yj
/V
Xi
).
(See G.7 in Appendix).
X
talk
-45
dB
V
INA
=2Vpp sinewave
f= 10MHz; R
L
= 75
.
-90
dB
V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 600
.
-85
dB
V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 1k
.
-80
dB
V
INA
=2Vpp sinewave
f= 1kHz; R
L
= 10k
.
Refer to Appendix, Fig. A.5
for test circuit.
7
Propagation delay through
switch
t
PS
30
ns
R
L
=1k
;
C
L
=50pF
AC Electrical Characteristics
- Control and I/O Timings
- V
DC
is the external DC offset applied at the analog
I/O pins. Voltages are with respect to V
DD
=5V, V
DC
=0V , V
SS
=-7V, unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CX
talk
30
mVpp
V
IN
=3V+V
DC
squarewave;
R
IN
=1k
, R
L
=1k
.
See Appendix, Fig. A.6
2
Digital Input Capacitance
C
DI
10
pF
f=1MHz
3
Switching Frequency
F
O
20
MHz
4
Setup Time DATA to STROBE
t
DS
10
ns
R
L
= 1k
,
C
L
=50pF
Q
5
Hold Time DATA to STROBE
t
DH
10
ns
R
L
= 1k
,
C
L
=50pF
Q
6
Setup Time Address to STROBE
t
AS
10
ns
R
L
= 1k
,
C
L
=50pF
Q
7
Hold Time Address to STROBE
t
AH
10
ns
R
L
= 1k
,
C
L
=50pF
Q
8
Setup Time CS to STROBE
t
CSS
10
ns
R
L
= 1k
,
C
L
=50pF
Q
9
Hold Time CS to STROBE
t
CSH
10
ns
R
L
= 1k
,
C
L
=50pF
Q
10
STROBE Pulse Width
t
SPW
20
ns
R
L
= 1k
,
C
L
=50pF
Q
11
RESET Pulse Width
t
RPW
40
ns
R
L
= 1k
,
C
L
=50pF
Q
12
STROBE to Switch Status Delay
t
S
40
100
ns
R
L
= 1k
,
C
L
=50pF
Q
13
DATA to Switch Status Delay
t
D
50
100
ns
R
L
= 1k
,
C
L
=50pF
Q
14
RESET to Switch Status Delay
t
R
35
100
ns
R
L
= 1k
,
C
L
=50pF
Q
MT8809
ISO-CMOS
3-26
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
Table 1. Address Decode Truth Table
AY2
AY1
AY0
AX2
AX1
AX0
Connection
AY2
AY1
AY0
AX2
AX1
AX0
Connection
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y0
X1 Y0
X2 Y0
X3 Y0
X4 Y0
X5 Y0
X6 Y0
X7 Y0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y4
X1 Y4
X2 Y4
X3 Y4
X4 Y4
X5 Y4
X6 Y4
X7 Y4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y1
X1 Y1
X2 Y1
X3 Y1
X4 Y1
X5 Y1
X6 Y1
X7 Y1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y5
X1 Y5
X2 Y5
X3 Y5
X4 Y5
X5 Y5
X6 Y5
X7 Y5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y2
X1 Y2
X2 Y2
X3 Y2
X4 Y2
X5 Y2
X6 Y2
X7 Y2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y6
X1 Y6
X2 Y6
X3 Y6
X4 Y6
X5 Y6
X6 Y6
X7 Y6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y3
X1 Y3
X2 Y3
X3 Y3
X4 Y3
X5 Y3
X6 Y3
X7 Y3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0 Y7
X1 Y7
X2 Y7
X3 Y7
X4 Y7
X5 Y7
X6 Y7
X7 Y7
CS
RESET
STROBE
ADDRESS
DATA
SWITCH*
t
CSS
t
CSH
t
RPW
t
SPW
t
AS
t
AH
t
DS
t
DH
t
D
t
S
t
R
t
R
ON
OFF
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%