Mindspeed TechnologiesTM, A Conexant Business

Information in this document is provided in connection with Mindspeed Technologies ("Mindspeed") products. These materials are provided by
Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or
omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed
makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
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AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
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LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST
REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.

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such improper use or sale.

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names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and
names are the property of their respective owners.
For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at

www.mindspeed.com

which is

incorporated by reference.

29704-DSH-001-B

Mindspeed Technologies

Ordering Information

Model Number

Manufacturing Part

Number

Package

Description

Operating Temperature

CX29704

CX29704-14

× 27, 272-Pin PBGA

4xSTS-3/STM-1

40 to 85

CX29702

CX29702-14

× 27, 272-Pin PBGA

2xSTS-3/STM-1

40 to 85

CX29701

CX29701-14

× 27, 272-Pin PBGA

1xSTS-3/STM-1

40 to 85

Revision History

Revision

Level

Date

Description

500034A

June 2001

Formerly Conexant document number 101344A.

500034B

July 2001

Corrected Figure 12.1.

29704-DSH-001-A

July 2002

Formerly document number 500034C. Data sheet now reflects
CX2970x family of devices. Major reorganization throughout.
Added new features that were added to the CX2970x-13 family,
specifically additional APS support.

29704-DSH-001-B

April 2003

Added Bellcore Jitter Specification information to

Section 2.1.3

;

updated register values.

29704-DSH-001-B

Mindspeed Technologies

iii

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

The CX2970x family of integrated circuits implements SONET/SDH processing and ATM/
Packet-Over-SONET(POS)/SDH at 155.52 Mbps. Each component in the family contains both
PMD and TC sublayers and provides a UTOPIA Level 2 interface to the ATM layer or a POS
Level 2 interface to the link layer. Mindspeed software drivers complete the physical layer
solution.

Major functional blocks of the devices include: LVPECL line interfaces, clock and data recovery
(CDR) circuits, transmit clock synthesizer, SONET/SDH framers, 16-bit UTOPIA/POS Level 2
system interface, and control/status interfaces. The control interface includes a simple 16-bit
microprocessor interface and a serial SONET/SDH Section/Line DCC byte interface. An alarm
and status serial interface (ASSI) provides access to alarm and status information. An industry
standard IEEE 1149.1 JTAG interface is provided for board level testing.

Functional Block Diagram

101344_001

Clock

Synthesis

Data &

Clock

Recovery

Serial to

Parallel

Parallel to

Serial

SONET/

SDH

Framer

SONET/

SDH

Framer

Overhead

Processor

Overhead

Processor

Tx ATM

Cell

Processor

Rx ATM

Cell

Processor

Tx POS

Processor

Rx POS

Processor

PORT 2

PORT 3

PORT 4

UTOPIA
Level 2 /

POS-PHY

Interface

PORT 0

RefCLK

PCAP0

NCAP0

REXT0

REXT1

TSDCC 1-4

TLDCC 1-4

TSDCK 1-4

TLDCK 1-4

RSDCC 1-4

RLDCC 1-4

RSDCK 1-4

RLDCK 1-4

D[15:0]

A[8:0]

CS*

W/*R

*DSTB

*INTR

*READY

ASCLK

*ASSTB

ASDO

TDO

TDI

TCK

TMS

*TRST

RxD0-

RxD0+

TxD0-

TxD0+

Microprocessor

Interface

JTAG

Interface

Sec./Line DCC i/f

ASSI

Rx_EOP

TxData[15:0]

TxAdd[4:0]

TxSOC/P[3:0]

*TxEnb[3:0]

TxClav/PTPAx4

TxPrty

Tx_ERR

RxData[15:0]

RxAdd[4:0]

RxSOC/P[3:0]

*RxEnb[3:0]

RxClav/PRPAx4

RxPrty
RxCLK

Tx_STPA

TxCLK

Tx_EOP

Tx_MOD

Rx_RVAL

Rx_ERR

Rx_MOD

FIFO

RxD3+/-

TxD3+/-

SD3

RxD2+/-

TxD2+/-

SD2

RxD1+/-

TxD1+/-

SD1

SD0

Distinguishing Features

Three devices in the STS-3/
STM-1 ATM/POS family based
on port count:

CX29704--four ports
CX29702--two ports
CX29701--one port

Software for industry leading
complete solution:

CX2970x Telecom

Application Package
(CX2970xTAP)

CX28299 Automatic

Protection Switching
(APS) Software Package

Data Sheet

Mindspeed Technologies

29704-DSH-001-B

-Continued from Front-

The CX2970x LVPECL line interface provides a simple interface to industry standard optical transceiver modules. The integrated
clock and data recovery and transmit synthesis circuits are compliant with Bellcore GR-253 jitter standards. In the transmit
direction ,the SONET/SDH framers generate all section, line, and path overhead bytes in addition to implementing framing,
scrambling and alarm indication functions. On the receive path, all framing, descrambling, alarm detection, and pointer
processing is performed. A serial interface inserts and extracts the section or line DCC bytes. The CX2970x has a complete set of
ATM cell processing functions including: cell encapsulation, HEC calculation, cell delineation, payload scrambling/descrambling,
and idle cell insertion/filtering. The POS processing features of the CX2970x include: HDLC framing, scrambling/descrambling,
interframe fills, FIFO management and stuffing/destuffing operations. For both ATM and POS applications, a combined UTOPIA
Level 2/POS Level 2 16-bit interface operates at 50 MHz to support a maximum throughput of 800 Mbps.

Software for the CX2970x is available on the Mindspeed web site and includes the CX2970x Telecom Application Package (TAP)
and the CX28299 Automatic Protection Switching (APS) software. The CX2970x TAP software is compliant with telecom
standards and includes device initialization code, configuration and diagnostic parameters, and support for failure and
performance monitoring according to applicable telecom standards. A debug monitor can optionally be compiled to assist in
initial hardware debugging. The CX28299 APS software supports linear 1+1, linear 1:n, and Unidirectional Path Switched Rings
(UPSR). The CX28299 APS software utilizes the bridging and switching features of the CX2970x family to implement a complete
physical layer APS solution that is transparent to the ATM/Link layer devices.

An evaluation module (EVM) is available from Mindspeed that demonstrates the features of the CX2970x family of devices. The
CX2904-CN8237 ATM/POS EVM includes the Mindspeed CX29704 ATM/POS PHY and the Mindspeed CN8237 ATM SAR
devices along with four optical transceiver modules in a standard PCI form factor card that can be used with most PC
motherboards. The POS system interface is accessible through two 50-pin connectors. Customers can accelerate their time-to-
market by using the evaluation module as a way to become familiar with the device. For complete EVM details including
schematics, board layout, and bill of material information, see the Mindspeed web site (www.mindspeed.com).

29704-DSH-001-B

Mindspeed Technologies

-Continued Distinguishing Features-

APS bridging and switching functions
built in

Receive clock and data recovery and
transmit clock synthesis compliant with
Telcordia GR-253 jitter standards

Full processing of SONET/SDH section,
line, and path overhead bytes

UTOPIA Level 2 and Packet Over SONET
(POS) Level 2 system interface

ATM cell and POS packet processing

Clock and data activity detectors and
level sensors for UTOPIA/POS system
interface debugging

Line Interface

On-chip clock and data recovery (CDR)
and transmit clock synthesis

Serializer and de-serializer circuits

Industry standard serial LVPECL
interface to external optical transceivers

SONET/SDH Framer Functions

Monitor of A1/A2 framing and recover
byte alignment from incoming serial data

Capture and insertion of all SONET/SDH
overhead bytes

Frame scrambling and descrambling

Byte Interleaved Parity (BIP) processing

Receive Pointer Processing to identify
payload location within the STS-3/STM-
1 frame

Line and Path Alarm indication signal
(AIS) detection and generation

Remote Defect and Remote Error
indication (RDI/REI) processing

Data Communication byte extraction and
insertion for line (D1-D3) and path (D4-
D12) bytes via serial interfaces

Performance and failure monitoring
(PM/FM) via status and error counters

Automatic Protection Switching (APS)
Support

Supports unidirectional and
bi-directional linear 1+1 and linear 1:n
APS architectures

Supports

Unidirectional Path

Switched Ring (UPSR) APS
architectures

Full control and processing of Line K1/
K2 octets

Bit Error Rate (BER) calculations
performed in hardware for SD/SF alarm
triggering

UTOPIA/POS port bridging and
switching functionality allows APS
solution that is transparent to ATM/Link
layer devices

ATM Cell and POS Packet Processing

4-cell FIFO buffers for both receive and
transmit directions in ATM mode

Cell encapsulation/delineation, payload
scrambling/descrambling, and idle cell
insertion/filtering

16-bit UTOPIA Level 2 Interface
according to the ATM Forum UTOPIA
Level 2 Specification

ATM cell UDF2 byte overwrite via control
register for each port

256-byte FIFO buffers for both receive
and transmit directions in POS mode

Packet HDLC scrambling/descrambling,
frame generation/delineation, byte
stuffing/destuffing, and FCS generation/
verification

16-bit POS Level 2 interface to a link
layer device

POS interface supports Normal and Hot
selection

UTOPIA/POS Dual-port mapping in
conjunction with SONET/SDH APS
mechanism facilitates quick recovery at
Failure Protection State

Control and Status

Asynchronous SRAM-like
microprocessor interface with 16-bit
data bus for configuration, control, and
status indications

Open drain interrupt output

Alarm and Status Serial Interface (ASSI)

Transmit and Receive serial interfaces
for Section and Line DCC octets

Test and Debug

Line, SONET, and ATM/POS loopbacks
for system debug

SONET/SDH, cell, and packet error
insertion capability

UTOPIA/POS-PHY interface activity
monitoring for diagnostics and debug

Boundary Scan (JTAG) support in
accordance with IEEE 1149.1 for test
board purposes

Electro-mechanical

272-pin PBGA, 27

× 27 mm

Industrial temperature range (

40 °C to

+85 °C)

3.3 V, 0.35 µm CMOS technology with
5 V input tolerance

TTL and CMOS outputs

Typical power consumption:
CX29704: 2.13W; CX29702: 1.95W;
CX29701: 1.89W

All devices in the CX2970x family
(CX29704/2/1) are pin compatible

Standards Compliance

Telcordia GR-253, ITU-G.707 and ANSI
T1.105

ATM Forum User Network Interface V3.1
Specification and physical layer
specification for B-ISDN according to
ITU-T recommendation I.432

Point-to-Point Protocol (PPP) over
SONET/SDH specification (RFC 2615 of
the IETF)

Applications

Switches

Routers

DSLAMs

Cellular base station infrastructure

Add/Drop Muxes (ADMs)

29704-DSH-001-B

Mindspeed Technologies

SONET/SDH STS-3c/STM-1 Overhead Byte Support

Section Overhead Octets Supported

Line Overhead Octets Supported

Path Overhead Octets Supported

Transmit

Receive

A1/A2

F6/28 hex or invert third A1 and first A2 for
LOF generation

Monitor out of frame state machine

Single byte insertable via register, 01 hex
default

Single byte captured into register

, Z0

02, 03 hex

Not checked

Calculated or invert for error insertion

Checked, errors counted

Insertable via register

Captured into register

Insertable via register

Captured into register

D1, D2, D3

00 hex or external data link

External data link

Transmit

Receive

H1/H2

SONET: 620A/93FF hex pointer
SDH: 6A0A/9BFF hex pointer

Full GR.253 pointer processor

Set to 00

Used in pointer processor

Calculated or invert for error insertion

Checked, errors counted

K1/K2

Insertable via register or automatic response
for K2[6:8] RDI-L

Captured into register, interrupt on change

D4-D12

00 hex or external data link

External data link

Insertable via register

Captured into register, interrupt on change

Insertable via register or automatic response
for

REI-L

Checked, errors counted

Insertable via register

Captured into register

Transmit

Receive

00 hex or 64-byte trace buffer

Monitor Rx trace buffer, interrupt on change

Calculated, error insertion

Checked, errors counted

Insertable via register, 13 hex default for ATM
mapping

Captured into register; PLM-P and UNEQ-P
interrupts generated if defect is present

Path

REI

, RDI inserted

Checked, errors counted, status

Insertable via register

Captured into register

Z3/F3

Insertable via register

Captured into register

Z4/K3

Insertable via register

Captured into register

Z5/N1

Insertable via register

Captured into register

29704-DSH-001-B

Mindspeed Technologies

vii

Table of Contents

List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

1.0

Product Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1

Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2

Application Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3

Pin Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4

Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2.0

Functional Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1

Line Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.1

Low Voltage PECL Interface (LVPECL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.2

Clock Synthesis

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.3

Clock and Data Recovery

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.4

Required External Components

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.5

LOCK Condition

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.6

Serial-to-Parallel

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.7

Parallel-to-Serial

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.8

Data Transmission

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2

SONET/SDH Framer and Overhead Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.1

Loss of Signal

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2

Section Overhead

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2.1

A1,A2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2.2

Loss of Frame

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2.3

J0/Z0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.2.4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.2.5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.2.6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.2.7

D1D3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.2.8

Frame Scrambler/Descrambler

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.3

Line Overhead

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.3.1

H1, H2, and H3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.3.2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table of Contents

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

viii

Mindspeed Technologies

29704-DSH-001-B

2.2.3.3

B2 Enhanced Line BER--Signal Degrade/Signal Fail Status

. . . . . . . . . . . . . . 2-11

2.2.3.4

K1 and K2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.2.3.5

Alarm Indication Signal-Line (AIS-L) Detection

. . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.3.6

Remote Defect Indication-Line (RDI-L) Detection

. . . . . . . . . . . . . . . . . . . . . 2-13

2.2.3.7

Remote Defect Indication-Line (RDI-L) Generation

. . . . . . . . . . . . . . . . . . . . 2-13

2.2.3.8

D4D12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.3.9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.3.10

M1 (REI-L)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.3.11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.4

STS SPE Pointer Processing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.4.1

LOP and AIS-P

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.5

Path Overhead

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.2.5.1

J1 Rx Path Trace Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.2.5.2

J1 Tx Path Trace Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.2.5.3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.2.5.4

B3 Enhanced Path BER--Signal Degrade/Signal Fail Status

. . . . . . . . . . . . . 2-18

2.2.5.5

C2 STS Path Signal Label

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.2.5.6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.2.5.7

Remote Error Indication-Path (REI-P) Accumulation

. . . . . . . . . . . . . . . . . . . 2-19

2.2.5.8

Remote Defect Indication-Path (RDI-P) Detection

. . . . . . . . . . . . . . . . . . . . . 2-20

2.2.5.9

Remote Defect Indication-Path (RDI-P) Generation

. . . . . . . . . . . . . . . . . . . 2-21

2.2.5.10

Remote Error Indication-Path (REI-P) Insertion

. . . . . . . . . . . . . . . . . . . . . . 2-22

2.2.5.11

F2 Path User Channel Byte

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.2.5.12

Z3/F3 Path Growth Byte

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.2.5.13

Z4/K3Z5/N1 Path Growth Bytes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.3

ATM Cell Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.3.1

Receive ATM Cell Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.3.1.1

Cell Delineation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.3.1.2

Out of Cell Delineation (OCD)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.1.3

Loss of Cell Delineation (LCD)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.1.4

HEC Verification

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.1.5

Cell Descrambling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.1.6

Cell Filtering

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.1.7

Performance Counters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.3.1.8

UDF2 Overwrite

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.3.2

Transmit ATM Cell Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.3.2.1

Header Error Check (HEC) Insertion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.3.2.2

Cell Scrambling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.3.2.3

Cell Rate Decoupling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.4

Packet Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.1

Receive Packet Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.1.1

Descrambling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.1.2

Frame Delineation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.1.3

Byte Destuffing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.1.4

Frame Check Sequence (FCS) Verification

. . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.1.5

Performance Counters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

CX2970x

Table of Contents

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

2.4.2

Transmit Packet Processor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.4.2.1

Flag Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.4.2.2

FCS Insertion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.4.2.3

Byte Stuffing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.4.2.4

Scrambling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.5

UTOPIA/POS System Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.5.1

UTOPIA Level 2 Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.5.1.1

Direct Status Indication

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.5.1.2

Multiplexed Status Polling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.5.1.3

One Rx/Tx CLAV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.5.1.4

16-bit ATM Cell Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.5.2

UTOPIA Transmit and Receive FIFOs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.5.2.1

Rx ATM Interface Cell FIFO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.5.2.2

Tx ATM Interface Cell FIFO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.5.3

POS Level 2 Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.5.3.1

16-bit POS Packet Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.5.3.2

POS Signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2.5.4

POS Transmit and Receive FIFOs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.5.4.1

Rx POS Interface FIFO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.5.4.2

Tx POS Interface FIFO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.5.5

POS Transmit Flow Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.5.6

POS Receive Flow Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.5.6.1

Normal Selection and Hot Selection Rx Modes of Operation

. . . . . . . . . . . . . 2-39

2.5.7

APS Support

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

2.5.8

1+1 APS Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

2.5.8.1

Unidirectional 1+1 APS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.5.8.2

Bi-directional 1+1 APS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.5.8.3

1:n APS Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.6

Microprocessor Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.6.1

Interface Signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.6.2

Mode Dependent Register Accesses

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.6.3

Programming Model

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

2.7

Interrupt Mechanism

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

2.8

Alarms Status Serial Interface (ASSI)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

2.9

Diagnostics/Testing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

2.9.1

Loopback Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

2.9.2

Error Insertion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.9.2.1

Overhead Bytes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.9.2.2

Loss Of Signal (LOS) Condition

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.9.2.3

Disabling Scramblers/ Descramblers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.9.3

UTOPIA/POS Activity Detector

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.9.3.1

Transition Detection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.9.3.2

Level Sensor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.9.4

JTAG

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.9.5

Full Scan

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Table of Contents

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

Mindspeed Technologies

29704-DSH-001-B

2.9.6

Block Bypass

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

3.0

Applications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1

ATM Layer Applications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2

POS Layer Applications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

4.0

Register Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

0x000--Global Reset and Revision Number Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4

0x001--Global Configuration Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5

Port Configuration Register A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-6

Port Configuration Register B

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7

Port Diagnostic Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-9

Port Status Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-10

Rx FIFO Control/Status Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-11

Tx FIFO Control/Status Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-12

Rx FIFO Status Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13

Tx FIFO Status Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-13

Tx FIFO Threshold; Tx-Inter-Frame-Fill (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-14

0x010--Global Interrupt Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-15

0x011--Global Mask Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-16

Framer Interrupt Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-17

Framer Mask Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-17

Overhead Byte Processor Interrupt Register A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-18

Overhead Byte Processor Mask Register A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-19

Overhead Byte Processor Interrupt Register B

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-20

Overhead Byte Processor Mask Register B

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-21

Cell, FIFO, and UTOPIA/POS Interrupt Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-21

Cell, FIFO, and UTOPIA/POS Mask Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-23

Rx Minimum Packet Length Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-24

Rx Maximum Packet Length Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-25

Rx FIFO High-Limit (Rx FHL) Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-25

Rx FIFO Low-Limit (Rx FLL) Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-26

Tx FIFO High-Limit (Tx FHL) Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-27

Tx FIFO Low Limit (Tx FLL) Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-27

Section BIP Error Counter Register (B1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-28

Line BIP Error Counter Register (B2), Lower Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-28

Line BIP Error Counter Register (B2), Upper Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-29

Line REI Error Counter Register, Lower Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-29

Line REI Error Counter Register, Upper Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-29

Path BIP Error Counter Register (B3)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-30

Path REI Error Counter Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-30

Uncorrectable Bad Header Counter Register (ATM mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-31

Correctable Bad Header Counter Register (ATM mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-31

CX2970x

Table of Contents

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

Rx Cell Counter Register, Lower Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-32

Rx Cell Counter Register, Upper Word (Add: 0x02A, 0x06A, 0x0AA, 0x0EA)

. . . . . . . . . . . . . . . . .

4-32

Tx Cell Counter Register, Lower Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-33

Tx Cell Counter Register, Upper Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-33

Rx Frame Counter Register (Add: 0x02D, 0x06D, 0x0AD, 0x0ED)

. . . . . . . . . . . . . . . . . . . . . . . .

4-33

Tx Frame Counter Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-34

Port Configuration Register C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-34

Rx APS Channel Register (K1, K2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-34

Tx APS Channel Register (K1, K2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-35

Rx Synchronization Status Message Register (S1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-35

Tx Synchronization Status Message Register (S1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-35

Rx Path Signal Label Register (C2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-36

Tx Path Signal Label Register (C2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-36

Rx Path User Channel Register (F2, Z3/F3)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-36

Tx Path User Channel Register (F2, Z3/F3)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-37

Path Trace Address Register (J1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-37

Path Trace Data Register (J1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-38

Rx RDI-P Register (G1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-38

Tx RDI-P and REI-P Register (G1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-38

Rx UDF2 Byte Register (ATM mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-39

Tx REI-L (M1) Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-39

0x040--Engineering Test Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-39

0x050--UTOPIA/POS Rx Transition Detection Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-40

0x051--UTOPIA/POS Tx Transition Detection Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-41

0x090--UTOPIA/POS Rx Level Sensor Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-42

0x091--UTOPIA/POS Tx Level Sensor Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-43

Rx Order Wire Byte Register (E1, E2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-43

Tx Order Wire Byte Register (E1, E2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-44

Rx Section User Channel Register (F1) and Rx Section Trace (J0)

. . . . . . . . . . . . . . . . . . . . . . . .

4-44

Tx Section User Channel Register (F1) and Tx Section Trace (J0)

. . . . . . . . . . . . . . . . . . . . . . . .

4-44

Rx Path Growth Byte Register (Z4/K3, Z5/N1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-45

Tx Path Growth Byte Register (Z4/K3, Z5/N1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-45

Rx Bad FCS Counter Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-45

Rx Maximum Length Violating Packet Counter Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . .

4-46

Rx Minimum Length Violating Packet Counter Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . .

4-46

Rx Packet Counter Register, Lower Word (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-47

Rx Packet Counter Register, Upper Word (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-47

Rx Aborted Packet Counter Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-47

Tx Aborted Packet Counter Register (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-48

Tx Packet Counter Register, Lower Word (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-48

Tx Packet Counter Register, Upper Word (POS mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-48

BER Status Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-49

BER Threshold Register - Line Error Monitoring (B2) and Path Error Monitoring (B3)

. . . . . . . . . .

4-49

Table of Contents

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

xii

Mindspeed Technologies

29704-DSH-001-B

5.0

Functional Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1

ATM Layer Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1

One Rx/Tx CLAV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1.1

Receive

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1.2

Transmit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.1.2

Direct Status Indication

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.1.2.1

Receive

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.1.2.2

Transmit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.1.3

Multiplexed Status Polling

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.1.3.1

Receive

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.1.3.2

Transmit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.1.4

Receive Link Layer Interface (POS Mode)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.1.5

Multiport, Hot Selection Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.1.6

Rx Multiport, Normal Selection Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.1.7

RVAL and RPA Functionality

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.1.8

Transmit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.1.9

Tx Multiport, Normal Mode Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.2

Alarms Status Serial Interface (ASSI)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.3

Data Communication Channel Port (DCC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

6.0

Electrical and Mechanical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1

AC Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1

Microprocessor Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.2

UTOPIA Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.1.3

POS Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.1.3.1

Rx AC Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.1.3.2

Tx AC Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.1.4

DCC Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.1.5

JTAG Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.1.6

Power-Up Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.1.7

Line Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.1.7.1

Transmit Line Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.1.7.2

Receive Line Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.2

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.3

DC Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.4

Mechanical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Appendix A CX29704

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1

General

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2

Pin Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2.1

UTOPIA/POS Level 2 Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2.2

POS Level 2 Interface Specific

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

A.2.3

Line Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

A.2.4

Data Communication Channel Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

CX2970x

Table of Contents

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

xiii

A.2.5

Microprocessor Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

A.2.6

Alarms Status Serial Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

A.2.7

JTAG Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

A.2.8

Scan Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

A.2.9

General Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11

A.2.10

Power and Ground

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11

A.3

Current and Power Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13

A.4

Package Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14

Appendix B CX29702

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1

General

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.2

Pin Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.2.1

UTOPIA/POS Level 2 Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.2.2

POS Level 2 Interface Specific

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.2.3

Line Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

B.2.4

Data Communication Channel Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

B.2.5

Microprocessor Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

B.2.6

Alarm Status Serial Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

B.2.7

JTAG Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

B.2.8

Scan Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

B.2.9

General Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

B.2.10

Power and Ground Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

B.3

Current and Power Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11

B.4

Package Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12

Appendix C CX29701

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.1

General

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.2

Pin Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

C.2.1

UTOPIA/POS Level 2 Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

C.2.2

POS Level 2 Interface Specific

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3

C.2.3

Line Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4

C.2.4

Data Communication Channel Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5

C.2.5

Microprocessor Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6

C.2.6

Alarm Status Serial Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7

C.2.7

JTAG Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7

C.2.8

Scan Interface Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7

C.2.9

General Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8

C.2.10

Power and Ground Pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9

C.3

Current and Power Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12

C.4

Package Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13

Appendix D Application Examples

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

D.1

Alarms Status Serial Interface (ASSI)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

CX2970x

List of Tables

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

List of Tables

Table 2-1.

SONET/SDH STS-3c/STM-1 Overhead Byte Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-2.

Line Error Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-3.

SF/SD Threshold Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-4.

Line Error Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Table 2-5.

ERDI-P Receive Defect Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Table 2-6.

ERDI-P Transmit Defect Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

Table 2-7.

RDI-P Transmit Defect Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

Table 2-8.

Rx ATM Cell Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Table 2-9.

The Rx Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Table 2-10.

Character Escape Map--Byte Destuffing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Table 2-11.

The Tx Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

Table 2-12.

Character Escape Map--Byte Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Table 2-13.

Recommended Mode of Operation Based on the Number of Ports Supported by
the ATM Layer Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

Table 2-14.

Three-stated Receive Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

Table 2-15.

Three-stated Transmit Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

Table 2-16.

Transition Detection Input Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Table 4-1.

Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 5-1.

ASSI AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Table 6-1.

Microprocessor Write/Read Cycle AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-2.

UTOPIA Transmit/Receive AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Table 6-3.

POS Interface Receive AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Table 6-4.

POS Interface Transmit AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

Table 6-5.

Section DCC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

Table 6-6.

Line DCC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

Table 6-7.

JTAG AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

Table 6-8.

Power-Up Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Table 6-9.

Soft Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Table 6-10.

Transmit Line Interface Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Table 6-11.

Receive Line Interface Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Table 6-12.

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Table 6-13.

DC Characteristics of the CX2070x UTOPIA/POS_Phy Pins . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Table 6-14.

DC Characteristics of the CX2970x Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

Table A-1.

UTOPIA/POS Level 2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Table A-2.

POS Level 2 Interface Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

Table A-3.

Line Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

Table A-4.

Data Communication Channel Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

Table A-5.

Microprocessor Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

Table A-6.

Alarms Status Serial Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

List of Tables

CX2970x

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Mindspeed Technologies

29704-DSH-001-B

Table A-7.

JTAG Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

Table A-8.

Scan Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

Table A-9.

General Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11

Table A-10.

Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11

Table A-11.

Current and Power Characteristics of the CX29704 Device . . . . . . . . . . . . . . . . . . . . . . . . . A-13

Table B-1.

UTOPIA/POS Level 2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

Table B-2.

POS Level 2 Interface Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Table B-3.

Line Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

Table B-4.

Data Communication Channel Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

Table B-5.

Microprocessor Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

Table B-6.

Alarms Status Serial Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

Table B-7.

JTAG Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

Table B-8.

Scan Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

Table B-9.

General Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

Table B-10.

Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

Table B-11.

Current and Power Characteristics of the CX29702 Device . . . . . . . . . . . . . . . . . . . . . . . . . B-11

Table C-1.

UTOPIA/POS Level 2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

Table C-2.

POS Level 2 Interface Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3

Table C-3.

Line Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4

Table C-4.

Data Communication Channel Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5

Table C-5.

Microprocessor Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6

Table C-6.

Alarms Status Serial Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7

Table C-7.

JTAG Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7

Table C-8.

Scan Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7

Table C-9.

General Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8

Table C-10.

Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9

Table C-11.

Current and Power Characteristics of the CX29701 Device . . . . . . . . . . . . . . . . . . . . . . . . . C-12

CX2970x

List of Figures

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

xvii

List of Figures

Figure 1-1.

CX2970x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 2-1.

CX2970x Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2.

Bellcore GR-253-CORE Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-3.

External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4.

STS-3c/STM-1 Frame Format and Overhead Byte Default Values . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-5.

Port Interpretation State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Figure 2-6.

Cell Delineation State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Figure 2-7.

Correction Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

Figure 2-8.

16-Bit Cell Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Figure 2-9.

Packet Over SONET/SDH--Data Format (64-byte packet). . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Figure 2-10.

UTOPIA Based 1+1 APS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

Figure 2-11.

UTOPIA Based 1:n APS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

Figure 2-12.

CX29704 Interrupt Mechanism Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

Figure 2-13.

Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

Figure 2-14.

SONET Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

Figure 2-15.

ATM Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52

Figure 3-1.

Interfacing Two CX29704 to One Multiport ATM Layer Device . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-2.

Using Direct Status Indication to Interface One CX29704 to One 4-port ATM Layer Device 3-3

Figure 3-3.

Interfacing Two CX29704 to One Multiport POS Layer Device . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 3-4.

Using Direct Status Indication to Interface One CX29704 to One 4-port POS Layer Device 3-5

Figure 5-1.

Receive One Rx/Tx CLAV Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Figure 5-2.

Receive One Rx/Tx CLAV Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Figure 5-3.

Transmit One Rx/Tx CLAV Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Figure 5-4.

Receive Direct Status Indication Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Figure 5-5.

Transmit Direct Status Indication Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Figure 5-6.

Receive Multiplexed Status Polling Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Figure 5-7.

Transmit Multiplexed Status Polling Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Figure 5-8.

Rx Single PHY Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Figure 5-9.

Multiport, Hot Selection Mode, Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Figure 5-10.

Rx Multiport, Normal Selection Mode, Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Figure 5-11.

RVAL and RPA Functionality in Hot Selection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Figure 5-12.

Tx Single Port, Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Figure 5-13.

Tx Multiport, Normal Mode Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Figure 5-14.

ASSI Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Figure 5-15.

Rx Section Data Communication Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Figure 5-16.

Tx Section Data Communication Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Figure 5-17.

Rx Line Data Communication Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Figure 5-18.

Tx Line Data Communication Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Figure 6-1.

Microprocessor Write Cycle AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

List of Figures

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

xviii

Mindspeed Technologies

29704-DSH-001-B

Figure 6-2.

Microprocessor Read Cycle AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Figure 6-3.

UTOPIA Transmit Direction AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Figure 6-4.

UTOPIA Receive Direction AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Figure 6-5.

POS Interface, AC Characteristics (Receive Path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Figure 6-6.

POS Interface, AC Characteristics (Transmit Path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Figure 6-7.

JTAG AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

Figure 6-8.

Power-Up Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Figure 6-9.

272-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Figure A-1.

CX29704 Package Layout (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14

Figure B-1.

CX29702 Package Layout (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12

Figure C-1.

CX29701 Package Layout (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13

Figure D-1.

ASSI Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

Figure D-2.

LVPECL Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

Figure D-3.

PECL to LVPECL Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

29704-DSH-001-B

Mindspeed Technologies

1-1

1.0 Product Description

The CX2970x family of STS-3/STM-1 ATM/POS SONET/SDH framers are
integrated circuits that implement one, two, or four channel mapping functions
for SONET/SDH processing and ATM/POS applications at 155.52 Mbps.

This chapter provides an overview of the CX2970x devices, including the

primary features and applications. A logic diagram, pin descriptions and a block
diagram are also included.

1.1 Features

The CX2970x family of integrated circuits implements SONET/SDH

processing and ATM/Packet-Over-SONET(POS)/SDH at 155.52 Mbps. Each
component in the family contains both the PMD and the TC sublayers and
provides an UTOPIA Level 2 interface to the ATM layer or a POS Level 2
interface to the link layer. Mindspeed software drivers complete the physical layer
solution.

Major functional blocks of the devices include: LVPECL line interfaces, clock

and data recovery (CDR) circuits, transmit clock synthesizer, SONET/SDH
framers, 16-bit UTOPIA/POS level 2 system interface, and control/status
interfaces. The control interface includes a simple 16-bit microprocessor interface
and a serial SONET/SDH Section/Line DCC byte interface. An alarm and status
serial interface (ASSI) provides access to alarm and status information. An
industry standard IEEE 1149.1 JTAG interface is provided for board level testing.

The CX2970x LVPECL line interface provides a simple interface to industry

standard optical transceiver modules. The integrated clock and data recovery and
transmit synthesis circuits are compliant with Bellcore GR-253 jitter standards. In
the transmit direction the SONET/SDH framers generate all section, line, and
path overhead bytes in addition to implementing framing, scrambling and alarm
indication functions. On the receive path, all framing, descrambling, alarm
detection, and pointer processing is performed. A serial interface inserts and
extracts the section or line DCC bytes. The CX2970x has complete set of ATM
cell processing functions including: cell encapsulation, HEC calculation, cell
delination, payload scrambling/descrambling and idle cell insertion/filtering. The
POS processing features of the CX2970x include: HDLC framing,
scrambling/descrambling, interframe fills, FIFO management and
stuffing/destuffing operations. For both ATM and POS applications a combined
UTOPIA Level 2/POS Level 2 16-bit interface operates at 50 MHz to support
maximum throughput of 800 Mb/s.

1.0 Product Description

CX2970x

1.2 Application Overview

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

1-2

Mindspeed Technologies

29704-DSH-001-B

Software for the CX2970x is available on the Mindspeed web site and

includes the CX2970x Telecom Application Package (TAP) and the CX28299
Automatic Protection Switching (APS) software. The CX2970x TAP software is
compliant with telecom standards and includes device initialization code,
configuration and diagnostic parameters, and support for failure and performance
monitoring according to applicable telecom standards. A debug monitor can
optionally be compiled to assist in initial hardware debugging. The CX28299
APS software supports linear 1+1, linear 1:n, and Unidirectional Path Switched
Rings (UPSR). The CX28299 APS software utilizes the bridging and switching
features of the CX2970x family to implement a complete physical layer APS
solution that is transparent to the ATM/Link layer devices.

An evaluation module (EVM) is available from Mindspeed that demonstrates

the features of the CX2970x family of devices. The CX2904-CN8237 ATM/POS
EVM includes the Mindspeed CX29704 ATM/POS PHY and the Mindspeed
CN8237 ATM SAR devices along with four optical transceiver modules in a
standard PCI form factor card that can be used with most PC motherboards. The
POS system interface is accessible through two 50-pin connectors. Customers can
accelerate their time-to-market by using the evaluation module as a way to
become familiar with the device. For complete EVM details including
schematics, board layout, and bill of material information, see the Mindspeed web
site.

1.2 Application Overview

The CX2970x family of devices can be used in a number of applications:

Switches

Routers

Digital Subscriber Line Access Muxes (DSLAMs)

Cellular base station infrastructure equipment

Add/Drop Muxes

The device is typically used in combination with a ATM layer Segmentation

and Reassembly (SAR) device or with a packet link layer device to implement
ATM over SONET/SDH or Packet over SONET/SDH architectures. For ATM
applications the Mindspeed CN8237 ATM SAR device can be used as a low cost
user network interface or network to network interface for OC-12 rates.
Mindspeed's CN8236 ATM SAR provides SARing functionality at the OC-3 rates
for integration with the CX2970x family of devices.

Packet and ATM cell based architectures can use Mindspeed's CX27470

Traffic Stream Processor (TSP) to build sophisticated traffic management
applications including: AAL5 SARing; ATM traffic shaping, policing and OAM
cell processing; AAL2 and Multi-Protocol Label Switching (MPLS) and other
Quality of Service (QoS) applications.

For more information on CX2970x applications, please see Chapter 3.0.

CX2970x

1.0 Product Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

1.3 Pin Description

29704-DSH-001-B

Mindspeed Technologies

1-3

1.3 Pin Description

Please refer to

Appendix A

Appendix B

, and

Appendix C

for pin descriptions

for the CX2970x family of devices.

1.4 Block Diagram

Figure 1-1

is a detailed block diagram of the CX2970x family of devices.

Figure 1-1. CX2970x Block Diagram

101344_001

Clock

Synthesis

Data &

Clock

Recovery

Serial to

Parallel

Parallel to

Serial

SONET/

SDH

Framer

SONET/

SDH

Framer

Overhead

Processor

Overhead

Processor

Tx ATM

Cell

Processor

Rx ATM

Cell

Processor

Tx POS

Processor

Rx POS

Processor

PORT 2

PORT 3

PORT 4

UTOPIA
Level 2 /

POS-PHY

Interface

PORT 0

RefCLK

PCAP0

NCAP0

REXT0

REXT1

TSDCC 1-4

TLDCC 1-4

TSDCK 1-4

TLDCK 1-4

RSDCC 1-4

RLDCC 1-4

RSDCK 1-4

RLDCK 1-4

D[15:0]

A[8:0]

CS*

W/*R

*DSTB

*INTR

*READY

ASCLK

*ASSTB

ASDO

TDO

TDI

TCK

TMS

*TRST

RxD0-

RxD0+

TxD0-

TxD0+

Microprocessor

Interface

JTAG

Interface

Sec./Line DCC i/f

ASSI

Rx_EOP

TxData[15:0]

TxAdd[4:0]

TxSOC/P[3:0]

*TxEnb[3:0]

TxClav/PTPAx4

TxPrty

Tx_ERR

RxData[15:0]

RxAdd[4:0]

RxSOC/P[3:0]

*RxEnb[3:0]

RxClav/PRPAx4

RxPrty
RxCLK

Tx_STPA

TxCLK

Tx_EOP

Tx_MOD

Rx_RVAL

Rx_ERR

Rx_MOD

FIFO

RxD3+/-

TxD3+/-

SD3

RxD2+/-

TxD2+/-

SD2

RxD1+/-

TxD1+/-

SD1

SD0

2.0 Functional Description

CX2970x

2.1 Line Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-2

Mindspeed Technologies

29704-DSH-001-B

Figure 2-1. CX2970x Line Interface

2.1.1 Low Voltage PECL Interface (LVPECL)

The lvpecl interface provides NRZ data to industry standard optical transceivers
or other physical layer interfaces. Examples on how to interface both 3.3 V and
5.0 V optical transceivers are provided in

Figure D-2

and

Figure D-3

2.1.2 Clock Synthesis

The Clock Synthesis block is responsible for generating a 155.52 MHz clock
signal using a 19.44 MHz reference clock multiplied by 8. This 155.52 MHz
synthesized clock output feeds into the Clock and Data Recovery block. The
synthesized clock is also used to drive the transmit parallel to serial block.

500034_046

Clock

Synthesis

Data &

Clock

Recovery

Serial to

Parallel

Parallel to

Serial

RefCLK

PCAP0

NCAP0

REXT0

REXT1

RxD0-

RxD0+

TxD0-

TxD0+

SONET/

SDH

Framer

SONET/

SDH

Framer

Overhead

Processor

Overhead

Processor

Tx ATM

Cell

Processor

Rx ATM

Cell

Processor

Tx POS

Processor

Rx POS

Processor

PORT 2

PORT 3

PORT 4

UTOPIA
Level 2 /

POS-PHY

Interface

PORT 0

1-4

K 1-4

1-4

K 1-4

15:0

]

8:0

]

*
D

*INTR

*READY

ASC

TDI

*
TR

Microprocessor

Interface

JTAG

Interface

Sec./Line DCC i/f

ASSI

Rx_EOP

TxData[15:0]

TxAdd[4:0]

TxSOC/P[3:0]

*TxEnb[3:0]

TxClav/PTPAx4

TxPrty

Tx_ERR

RxData[15:0]

RxAdd[4:0]

RxSOC/P[3:0]

*RxEnb[3:0]

RxClav/PRPAx4

RxCLK

Tx_STPA

TxCLK

Tx_EOP

Tx_MOD

Rx_RVAL

Rx_MOD

FIFO

RxD3+/-

TxD3+/-

SD3

RxD2+/-

TxD2+/-

SD2

RxD1+/-

TxD1+/-

SD1

SD0

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.1 Line Interface

29704-DSH-001-B

Mindspeed Technologies

2-3

2.1.3 Clock and Data Recovery

This block performs data retiming and clock recovery from the incoming serial
data stream. The 155 MHz clock is synthesized using a 19.44 reference clock.
This synthesized clock is then provided to each port as the reference clock. Each
port phase locks onto the data stream using the 155 MHz synthesized clock as a
reference input and generates the recovered clock and data outputs.

The recovered clock meets jitter tolerance and jitter transfer specifications

according to Bellcore GR-253 (see

Figure 2-2

). Jitter tolerance is defined as how

much jitter the receiver can tolerate and still extract the correct data from the
incoming signal. Jitter transfer is the maximum amount of jitter that any device is
allowed to add to the data stream.

Figure 2-2. Bellcore GR-253-CORE Jitter Specifications

The Jitter Generation shall be less than 0.01 UI

rms

and shall also be less than 0.10 UI

Slope = -20 dB/decade

15UI

1.5UI

0.15UI

Jitter Tolerance

Jitter Generation:

Slope = -20 dB/decade

0.1dB

130 kHz

Jitter Transfer

10 Hz 30 Hz 300 Hz

6.5 kHz

65 kHz

500035_009

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.1 Line Interface

29704-DSH-001-B

Mindspeed Technologies

2-5

2.1.5 LOCK Condition

The CX29704 constantly monitors for a LOCK state between the synthesized
clock and the recovered clock. A LOCK state occurs when there is less than
±1000 PPM shift between the clocks. An Out-of-LOCK state is indicated as a
Loss Of Signal (LOS) alarm (see

Section 2.2.1

) and Loss of Lock (LOL) alarm.

2.1.6 Serial-to-Parallel

The Serial-to-Parallel block converts the incoming serial bit data into 8-bit (octet)
parallel data.

2.1.7 Parallel-to-Serial

The Parallel-to-Serial block serializes and transmits the data from the framer
block.

2.1.8 Data Transmission

There are two modes of operation. By default, transmitted data is driven to the
transceiver by the Clock and Data Recovery Block using the synthesized clock.

The user can also choose to drive data with the recovered clock by setting the

Tx Timing Bit in Configuration Register A (

See "Port Configuration Register A"

on page 4-6.

) to a value of 1.

If no data is present at the input data stream (LOS indication), or the signal

detect input (SD pin) is low, the transmission clock automatically switches to the
synthesized lock. Once the cause for the clock switch (LOS or SD) is terminated,
the transmit clock source returns to its configured source.

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-6

Mindspeed Technologies

29704-DSH-001-B

2.2 SONET/SDH Framer and Overhead Processor

Mindspeed's CX2970x SONET/SDH framer family has an extensive SONET
overhead processing section with external access for D1-D3 and D4-D12 Data
Link message processing. The framer provides data transmission at a standard bit
rate, frequency justification, pointer processing, and SONET frame delineation.
The SONET Overhead processor provides frame synchronization, byte
scrambling and descrambling, and byte multiplexing and demultiplexing.

The frame structure for STS-3c/STM-1 can be envisioned as a 270-column by

nine-row rectangle of bytes (octets) shown in

Figure 2-4

. The section, line, and

path overhead bytes supported by the CX2970x devices are shaded in figure 2-3
and listed in

Table 2-1

. The transmission of the block starts with the first row,

working from left to right, then moves to the second row, left to right, and so on
down to the byte in the bottom right corner. Thus, the transport overhead octets
are actually transmitted in nine groups of nine octets, equally spaced throughout
the frame. Since there are 270 x 9 bytes, the data rate is 270 x 9 x 8 (bits/bytes) x
8,000 fps. (the frame period is 125 micro-seconds) = 155.52 Mbps.

Overhead bytes marked with the value * are variables and are calculated

according to the frame contents.

Figure 2-4. STS-3c/STM-1 Frame Format and Overhead Byte Default Values

101344_009

STS SPE

ATM Cells

125 S

Frame
Boundary

0x00

0x13

0x00

Z3/F3

0x00

Z4/K3

0x00

Z5/N1

0x00

PATH

SECTION

LINE

261 bytes

0x02

0x03

0x00

0x28

0x00

0x01

0x00

0xFF

0x00

D12

0x00

0xF6

0x00

0x28

0x00

0x62

0x93

0x00

0x0A

0x00

D10

0x00

D11

0x00

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-7

Table 2-1. SONET/SDH STS-3c/STM-1 Overhead Byte Support

Layer

Byte

Transmit

Receive

Section

A1/A2

F6/28 hex or invert third A1 and first A2 for
LOF generation

Monitor out of frame state machine

Single byte insertable via register, 01 hex
default

Single byte captured into register

, Z0

02, 03 hex

Not checked

Calculated or invert for error insertion

Checked, errors counted

Insertable via register

Captured into register

Insertable via register

Captured into register

D1, D2, D3

00 hex or external data link

External data link

Line

H1/H2

SONET: 620A/93FF hex pointer
SDH: 6A0A/9BFF hex pointer

Full GR.253 pointer processor

Set to 00

Used in pointer processor

Calculated or invert for error insertion

Checked, errors counted

K1/K2

Insertable via register or automatic
response for K2[6:8] RDI-L

Captured into register, interrupt on change

D4-D12

00 hex or external data link

External data link

Insertable via register

Captured into register, interrupt on change

Insertable via register or automatic
response for REI-L

Checked, errors counted

Insertable via register

Captured into register

Path

00 hex or 64-byte trace buffer

Monitor Rx trace buffer, interrupt on change

Calculated, error insertion

Checked, errors counted

Insertable via register, 13 hex default for
ATM mapping

Captured into register; PLM-P and UNEQ-P
interrupts generated if defect is present

Path REI, RDI inserted

Checked, errors counted, status

Insertable via register

Captured into register

Z3/F3

Insertable via register

Captured into register

Z4/K3

Insertable via register

Captured into register

Z5/N1

Insertable via register

Captured into register

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-8

Mindspeed Technologies

29704-DSH-001-B

2.2.1 Loss of Signal

An LOS defect is declared when the incoming data stream (before descrambling)
contains an all-0s pattern for 20

µs or the Signal Detect (SD) signal indicates

non-valid signal from the optical transceiver for 20

µs or an Out-of-LOCK

condition was detected for 20

µs. The LOS defect is terminated when the

incoming data stream contains two consecutive valid framing patterns and no
LOS defect is detected in the intervening time and the Signal Detect (SD) signal
indicates a valid signal from the optical transceiver and the device is in LOCK
condition. While the port is in LOS state, no values are captured into the device
overhead bytes, and the last value before the LOS occurred remains in the
overhead bytes.

An LOS Defect status bit is provided (Bit 0 in

Framer Interrupt Register on

page 4-17

2.2.2 Section Overhead

The Section Overhead handles the transport of the STS-3c/STM-1 frame across
the physical medium and section-level communications. Its functions are framing
and scrambling on the transmit side, and section error monitoring on the receive
side.

2.2.2.1 A1,A2

On each frame, the framer compares the expected framing pattern (A1=0xF6,
A2=0x28) with the framing bytes received on incoming data in order to ensure
frame alignment. A Severely Errored Frame (SEF) defect is declared when four
consecutive framing patterns contain errors. When an SEF defect is detected, the
SONET/SDH framer begins searching for a framing pattern. When the framer
recognizes two successive error-free framing patterns, the SEF defect is
terminated.

An SEF Defect Generation/Termination status bit, with Interrupt, is provided

(Bit 1) in the

Framer Interrupt Register on page 4-17

2.2.2.2 Loss of Frame

The in-frame timer is activated if there is no SEF defect. The timer stops and is
reset to zero when an SEF defect is detected. The SEF timer is activated when an
SEF defect is present. The timer stops when the SEF defect is terminated. It is
reset to zero when the SEF defect is absent continuously for 3 ms (the in-frame
counter reaches 3 ms).

An LOF defect is detected when the SEF timer reaches the 3 ms threshold.

The LOF defect is terminated when the in-frame counter reaches 3 ms. While the
port is in LOF state, no values are captured in the device overhead bytes, and the
last value before the LOF occurred remains in the overhead bytes. An LOF Defect
Generation/Termination status bit, with Interrupt, is provided (Bit 2 in

Framer

Interrupt Register on page 4-17

An LOF defect may be inserted into the transmit frame by setting the LOF

insertion bit in the

Port Diagnostic Register on page 4-9

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-9

2.2.2.3 J0/Z0

The Section Trace bytes are extracted from the incoming receive frame and
accessible through the microprocessor interface. The data is not kept in the
message format as the J1; however, the data is available in general purpose
registers (

See "Rx Section User Channel Register (F1) and Rx Section Trace (J0)"

on page 4-44.

The transmitted J0 Section Trace value can be modified by writing to the

Section User Channel Register (F1) and Tx Section Trace (J0) on page 4-44

2.2.2.4 B1

The Section Error Monitor performs error monitoring on the entire frame by
calculating the BIP-8 error code of the incoming frame before descrambling. The
result is compared with the B1 overhead byte of the next frame. Any difference
between matching bits indicates that a section bit interleaved parity error has
occurred. The first bit of the B1 byte should reflect the even parity over the first
bit of every byte in the entire frame. These parity bit errors are accumulated in a
16-bit saturating counter that can be read through the microprocessor interface.
To avoid the possibility of loss of events, the counter should be polled at least
once per second. An interrupt is generated upon detection of an error.

B1 Insertion

The BIP-8 error code of the outgoing scrambled frame is calculated and inserted
into the B1 overhead byte of the next frame before scrambling. The first bit of B1
reflects the even parity over the first bit of every byte in the entire frame. The B1
byte may optionally be inserted inverted for diagnostic purposes by setting the B1
inversion bit in the

Port Diagnostic Register on page 4-9

2.2.2.5 E1

The Order Wire Byte, formerly used to facilitate a voice channel, is captured from
the receive frame and can be read via the

Rx Order Wire Byte Register (E1, E2)

on page 4-43

A default value of 0x00 is transmitted on the transmit path for this overhead

byte. A different value may be transmitted by writing to the

Tx Order Wire Byte

2.2.2.6 F1

The Section User Channel byte is captured from the receive frame and can be read
via the through the

Rx Section User Channel Register (F1) and Rx Section Trace

(J0) on page 4-44

A default value of 0x00 is transmitted on the transmit path for this overhead

byte. A different value may be transmitted by writing to the

Tx Section User

Channel Register (F1) and Tx Section Trace (J0) on page 4-44

2.2.2.7 D1D3

The three Section DCC overhead bytes (D1D3) are captured and serially output
on RSDCD1

4 output pins using a 216 kHz clock (with effective rate of 192 kHz)

provided on the RSDCC1

4 output pins. Certain systems require a serial port to

extract the Section DCC bytes and implement management functions. This port
can optionally be disabled via the

Port Configuration Register B on page 4-7

The Section DCC overhead bytes can be inserted on the transmit interface by

suppling data via TSDCC1-4 input pins. The transmit section DCC clock
provided on TSDCC1-4 samples the data on the serial data inputs using the rising
edge of the clock. This port can optionally be disabled via the

Port Configuration

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-10

Mindspeed Technologies

29704-DSH-001-B

2.2.2.8 Frame

Scrambler/Descrambler

Scrambling and descrambling is performed using a 127-sequence-long,
self-synchronous scrambler/descrambler circuit. The generating polynomial is
1+X

. The framing bytes (A1, A2), the section trace byte (J0), and the section

growth bytes (Z0) are not scrambled/descrambled.

The receive frame descrambler may optionally be disabled by setting the FDD

bit in the

Port Diagnostic Register on page 4-9

. The transmit frame scrambler can

be disabled by setting the FSD bit in the

Port Diagnostic Register on page 4-9

2.2.3 Line Overhead

The Line Overhead handles the transport of path-level payloads across the
physical medium. This layer of the overhead provides synchronization and
multiplexing functions for the Line layer. These functions include maintenance
and line protection. The Section Overhead must be terminated before the Line
Overhead can be accessed.

2.2.3.1 H1, H2, and H3

The H1, H2, and H3 in the STS-3c/STM-1 frame are fixed on the transmit side to
locate the path overhead J1 byte immediately after the second Z0 byte of the
Section Overhead. On the receive side the H1, H2, and H3 bytes are used by the
pointer processor (refer to STS SPE Pointer Processing section below) to locate
the floating payload (SPE) as defined by SONET (i.e. Telcordia GR-253) and
ITU standards.

The SS bits within the H1 overhead bytes are undefined by the SONET

Standard and are transmitted with a default value of 00. In SDH applications,
these bits are set to the 10 value. Thus, in SDH mode the default value of the first
H1 byte is 0x6A and the default value of the other two H1 overhead bytes is 0x9B.

2.2.3.2 B2

The Line Error Monitor performs error searching on the entire frame (excluding
the section overhead bytes) by calculating the BIP-24 error code of the incoming
frame after descrambling. The result is compared with the B2 overhead bytes of
the next frame. Any difference between matching bits indicates a line bit
interleaved parity error has occurred. The first bit of the first B2 byte should
reflect the even parity over the first bit of every three bytes in the entire frame.
These parity errors are accumulated in a 32-bit saturating counter that can be read
through the microprocessor interface. Interrupt generation upon detection of an
error is optional.

The user can program a threshold of errors (number of line BIP-24 errors

found) and the period during which this counting is done. The Period register is a
32-bit counter that counts the 19.44 MHz clock. For instance, a period of one
second should be programmed to the Period register as a 0x128A180 value. The
user should also program the threshold of errors (16-bit register), above which an
interrupt is generated. When the period counter reaches the zero value (end of
period), the error counter is reset to zero and the counting begins again. If the
number of BIP-24 errors found in this period is greater than the threshold, an
interrupt is generated to reflect this condition. The number of errors is counted
based on the individual/frame counting mode, as specified in the Port
Configuration register.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-11

2.2.3.3 B2 Enhanced

Line BER--Signal

Degrade/Signal Fail

Status

A dedicated mechanism for enhanced Bit Error Rate (BER) monitoring is
provided. BER monitoring is accomplished by observing the B2 BIP error count.
If the incoming error rate exceeds the thresholds programmed in the APS
Threshold Control register, the signal degrade or signal fail status is reported
using a maskable interrupt. Two thresholds are supported: Signal Degrade (SD)
and Signal Fail (SF). Each threshold is programmable for BER levels from 10

-3

-9

BER Threshold Register - Line Error Monitoring (B2) and Path Error

Monitoring (B3) on page 4-49

Table 2-3

shows the programming range for the

thresholds in the register. The alarm clearing threshold and observation time are
automatically set to 1/10 of the programmed alarm detection threshold.

Table 2-2. Line Error Monitor

BER

Detect Time

(ms)

B2 BER Period

Register

B2 BER Threshold

Register

0x4BF0

0x9A

0x97E0

0x1F

0x4BF00

0x18

128

0x25F800

0x13

2,048

0x25F8000

0x1F

16,384

0x12FC0000

0x18

131,072

0x97E00000

0x13

Table 2-3. SF/SD Threshold Table

L-SF Thresholds (Bits 74)

L-SD Thresholds (Bits 30)

Detect

Threshold

Clearing

Threshold

95%

Confidence

Interval

Actual

Observation

Time

Required

Switch

Initiation

Time

0h3h

64.5 uSec

1 mSec

8 mSec

645 uSec

2 mSec

13 mSec

6.45 mSec

16 mSec

100 mSec

64.5 mSec

128 mSec

1 Sec

645 mSec

2.048 mSec

10 Sec

6.45 Sec

16.384 mSec

83 Sec

9hFh

64.5 Sec

131 Sec

667 Sec

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-12

Mindspeed Technologies

29704-DSH-001-B

The user can program a threshold of errors (number of line BIP-24 errors

B2 Insertion

The BIP-24 error code of the non-scrambled outgoing frame (excluding the
section overhead bytes) is calculated and inserted into the B2 overhead byte of the
next frame before scrambling. The first bit of the first B2 byte reflects the even
parity over the first bit of every three bytes in the entire frame, and so on. The B2
bytes can be inserted inverted for diagnostic purposes by setting the B2 inversion
bit in the

Port Diagnostic Register on page 4-9

2.2.3.4 K1 and K2

The K1 and K2 overhead bytes are used for handshaking between network
elements that support Automatic Protection Switching (APS) when transmission
failure occurs to determine whether or not to switch from the failed working
channel to the protection channel.

Bits 68 of the K2 overhead byte are used for Alarm Indication Signal-Line

(AIS-L) and Remote Defect Indication-Line (RDI-L) alarms which are described
later in this chapter.

These bytes are available through the microprocessor interface for receive and

transmit. In the receive path, the K1 and K2 bytes are captured when three
consecutive identical new-frame values are received. APS Inconsistent State is
entered when in 12 frames, no three consecutive frames are received with
identical K1 byte. The APS state machine exits the Inconsistent State when three
consecutive frames contain an identical K1 byte.

An interrupt is generated upon capture of new values of K1 and K2 bytes. An

APS Inconsistent State status bit (

See "Port Status Register" on page 4-10.

) is

provided and an interrupt is generated when entering or exiting this state.

Table 2-4. Line Error Monitor

BER

Detect Time

(ms)

B2 BER Period

Register

B2 BER Threshold

Register

0x4BF0

0x9A

0x97E0

0x1F

0x4BF00

0x18

128

0x25F800

0x13

2,048

0x25F8000

0x1F

16,384

0x12FC0000

0x18

131,072

0x97E00000

0x13

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-13

The value transmitted for the K2 byte can be controlled by two methods, total

software control, or mixed hardware/software control. Writing the Tx K2 Select
bit in the

Port Configuration Register B on page 4-7

to a logic 0 selects mixed

hardware/software control. In this mode bits 6-8 of the K2 byte are inserted
automatically to generate RDI-L codes and bits 1-5 are controlled by the value in
the

Tx APS Channel Register (K1, K2) on page 4-35

. Setting the Tx K2 Select bit

to a logic 1 selects complete software control. In this mode the entire transmitted
K2 byte is sourced from the Tx APS Channel Register.

2.2.3.5 Alarm Indication

Signal-Line (AIS-L)

Detection

An AIS-L defect is detected on the incoming signal when bits 6, 7, and 8 of the
K2 byte contain the 111 pattern in five consecutive frames. The AIS-L defect is
terminated when bits 6, 7, and 8 of the K2 byte contain any pattern other than 111
in five consecutive frames. AIS-L Defect status bit is provided and Interrupt upon
generation and termination is optional.

2.2.3.6 Remote Defect

Indication-Line (RDI-L)

Detection

RDI-L defect is detected on the incoming signal when bits 6, 7, and 8 of the K2
byte in five consecutive frames contain the 110 pattern. RDI-L defect is
terminated when bits 6, 7, and 8 of the K2 byte contain any pattern other than
110 in five consecutive frames. RDI-L Defect Status Generation/Termination bit
is provided. Generation of an interrupt is optional.

2.2.3.7 Remote Defect

Indication-Line (RDI-L)

Generation

RDI-L is generated within 125

µs of LOS, LOF, or AIS-L defect detection on the

incoming signal. The RDI-L is generated by inserting the pattern 110 in bits 6, 7,
and 8 of the K2 overhead byte.

RDI-L is terminated within 125

µs of termination of the defect that caused it

to be generated by inserting the pattern 000 in bits 6, 7, and 8 of the K2 overhead
byte.

2.2.3.8 D4D12

The nine line DCC overhead bytes (D4D12) are captured and serially output on
the RLDCD1

4 output pins using a 648 kHz clock (with an effective rate of 576

kHz) provided on the RLDCC1

4 output pins. This port can optionally be

disabled via the

Port Configuration Register B on page 4-7

The line DCC overhead bytes can be inserted on the transmit interface by

suppling data via the TLDCC1-4 input pins. The transmit line DCC clock
provided on the TLDCC1-4 samples the data on serial data inputs using the rising
edge of the clock. This port can optionally be disabled via the

Port Configuration

2.2.3.9 S1

Bits 58 of the Synchronization Status byte, S1, are used to convey the
synchronization status of the network elements. Bits 14 are currently undefined.
These status messages provide an indication of the quality of the synchronization
source of the SONET signal. This allows the network elements to determine the
best synchronization reference available and reconfigure their synchronization
references autonomously without creating timing loops. The S1 byte can be read
from the

Rx Synchronization Status Message Register (S1) on page 4-35

A default value of 0x00 is inserted into the transmitted frame. The transmitted

value may be modified by writing to the

Tx Synchronization Status Message

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-14

Mindspeed Technologies

29704-DSH-001-B

2.2.3.10 M1 (REI-L)

The number of REI-L BIP-24 errors detected in the last received frame is
accumulated in a 32-bit counter that can be read through the microprocessor port.
Interrupt generation upon detection of an error is optional.

The transmitted M1 byte can be controlled by either hardware or software.

The Tx M1 Select bit in the

Port Configuration Register B on page 4-7

determines how the byte is generated. Writing the Tx M1 Select bit to a logic 0
selects hardware control. In this mode the REI-L is transmitted by inserting the
number of line BIP-24 errors detected over the last frame into the transmitted M1
overhead byte. Writing the Tx M1 Select bit to a logic 1 selects software control
and the M1 byte value is sourced from the

Tx REI-L (M1) Register on page 4-39

2.2.3.11 E2

The E2 Order Wire byte, formerly used to facilitate a voice channel, is captured
from the receive frame and can be read from the

Rx Order Wire Byte Register

(E1, E2) on page 4-43

A default value of 0x00 is inserted into the transmitted frame. The transmitted

value may be modified by writing to the

Tx Order Wire Byte Register (E1, E2) on

page 4-44

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-15

2.2.4 STS SPE Pointer Processing

During normal operation, the pointer value (H1, H2) represents the offset from
the H3 byte to the first byte of the STS SPE (J1). Any consistent new value
received three successive times replaces the current value. If an increment is
detected, the byte following the H3 is considered a positive stuff byte, and the
pointer value is incremented by one. If a decrement is detected, then H3 is
considered a negative stuff byte, and the pointer value is decremented by one. If a
set New Data Flag (NDF) is detected, the new pointer value replaces the old
pointer value.

2.2.4.1 LOP and AIS-P

The pointer interpretation can be modeled as a finite state-machine, holding
three-states: NORM, AIS, LOP. The transition between the states occurs after
detecting three consecutive events of the same type (with the exception of
transition from AIS_state to NORM_state by Norm_NDF). The following events
drive the transition:

NORM_point--Normal NDF and offset value in range with valid
concatenation values.

NDF_enable/Set_NDF--NDF enabled AND offset value in range.

AIS_ind--11111111 11111111 (in H1 and H2 bytes).

Incr_ind--Normal NDF AND majority of I bits inverted AND no majority
of D bits inverted AND previous NDF_enable, incr_ind or decr_ind.

Decr_ind--Normal NDF AND majority of D bits inverted AND no
majority of I bits inverted AND previous NDF_enable, incr_ind or
decr_ind.

Inv_point--Any other OR norm_point with an offset value not equal to the
active offset is defined as Invalid-Pointer.

The transitions indicated in the state diagram are defined as follows:

Inc_ind/dec_ind--Offset adjustment (increment or decrement indication).

3 x norm_point--Three consecutive equal norm_point indications.

NDF_enable--Single NDF_enable indication.

3 x AIS_ind--Three consecutive frames with AIS indications.

8 x inv_point--Eight consecutive inv_point (SDH mode only).

8 x NDF_enable--Eight consecutive NDF_enable.

NOTE(S):

Active offset is defined as the accepted current phase of the VC in the
NORM_state and is undefined in the other states.

NDF enabled is equal to 1001, 0001, 1101, 1011, 1000.

Normal NDF is equal to 0110, 1110, 0010, 0100, 0111.

The transitions from NORM to NORM do not represent changes of state
but imply offset changes.

3 x norm_point takes precedence over 8 x inv_point.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-17

2.2.5 Path Overhead

The Path Overhead checks for end-to-end communication integrity. The Section
and Line Overhead must be terminated before the Path Overhead can be accessed.

2.2.5.1 J1 Rx Path

Trace Buffer

A 16-byte (SDH mode) or 64-byte (SONET mode) trace buffer is available for
receiving the path identifier byte J1. Data to the buffer is written or read via the
Path Trace Address register and the Path Trace Data register.

An interrupt is generated whenever a new message is received for two

successive frames. The Rx Path Trace buffer can be read by reading the 16 or
64 bytes from the registers that compose this buffer. The selection of which part
(i.e., register) of the buffer will be read is determined by the Rx Path Trace
address. To begin reading the buffer, an address is loaded to the Rx Path Trace
address. Generally, this is the first address of the buffer. The R/W bit should be
set to 1 (Read mode) and the Rx/Tx bit of the register set to 1 (reading the receive
buffer).

A 16-bit microprocessor read cycle should be performed from the address

mapped to the Rx Path Trace array. After this reading cycle, the Path Trace
address is auto-incremented to point to the next 16 bits of the buffer. The next
reading cycle is from the same address of the microprocessor port but with an
auto-incremented pointer (Rx Path Trace address). After 8 read cycles (SDH
mode) or 31 read cycles (SONET mode), the reading is completed and the Rx
Path Trace address is loaded with its initial value. The identifier is received using
the J1 overhead byte on each frame. The first byte of the identifier (one in MSB
for SDH mode or the first byte after CR (0x0D) and LF(0x0A) for SONET mode)
is located in the LSB of the word in address 0x0 and the second byte on the MSB.
Each byte received is compared with the appropriate byte in the previous
identifier. When two new identical consecutive identifiers are received, an
interrupt is generated.

To summarize the process of reading the Path Trace message, the following

steps are required:

Receive an interrupt that points to a new message.

Load the Path Trace address with the first address in the buffer.

Read the first 16-bit word of the buffer (after which the address register is
auto-incremented).

Repeat step 3, if required.

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-18

Mindspeed Technologies

29704-DSH-001-B

2.2.5.2 J1 Tx Path

Trace Buffer

A 16-byte (SDH mode) or 64-byte (SONET mode) trace buffer is available for
transmission through the path identifier byte (J1). Data to the buffer is written or
read via the Tx Path Trace Address register and the Tx Path Trace Data register.

To load the buffer with the transmitted value, the user must first disable the J1

transmission logic by setting the appropriate bit in the Path Trace Address register
to logic 0. While in that state, the default value is transmitted. The transmit J1 is
loaded with new data by writing the 16 or 64 bytes that make up this buffer to the
registers. The selection of which part of the buffer data will be written is done by
the Tx Path Trace address. Once the transmission is disabled, and an address is
loaded to the Tx Path Trace address, the R/W and Rx/Tx bits should be set to 0
(writing data to the transmit buffer). A 16-bit write should then be performed on
the microprocessor bus to the address mapped to the Tx Trace buffer. After this
writing cycle, the Tx Path Trace address is auto-incremented to point to the next
16 bits of the buffer. After 8 (SDH) writing cycles or 32 (SONET) writing cycles,
the Enable/Disable bit should be set to 1. This allows transmission of the buffer
data by the J1 overhead byte.

To summarize, the process of loading the buffer with values requires the

following steps:

Disable the transmission.

Load the Path Trace address with the first address in the buffer.

Write a 16-bit word to the address of the Tx Path Trace buffer, after which
the address register is auto-incremented.

Repeat Step 3 if required.

Enable the transmission.

2.2.5.3 B3

The path error monitor block performs error monitoring on the entire STS SPE by
calculating the BIP-8 error code of the incoming SPE after descrambling. The
result is compared with the B3 overhead byte of the next frame. Any difference
between matching bits indicates that a path bit interleaved parity error has
occurred. The first bit of the B3 byte should reflect the even parity over the first
bit of every byte in the entire SPE. These parity bit errors are accumulated in a
16-bit saturating counter that can be read through the microprocessor interface.
Bits 47 of the transmitted G1 overhead byte are allocated to the REI-P count
transmitted on the last frame. To avoid losing events, the counter should be polled
at least once per second. Interrupt generation upon detection of an error is
optional.

B3 Insertion

The Bit Interleaved Parity (BIP)-8 error code of the outgoing STS SPE before
scrambling is calculated and inserted into the B3 overhead byte of the next frame.
The first bit of B3 reflects the even parity over the first bit of every byte in the
entire STS SPE. The B3 byte can be inserted inverted for diagnostic purposes by
setting the B3 inversion bit in the

Port Diagnostic Register on page 4-9

2.2.5.4 B3 Enhanced

Path BER--Signal

Degrade/Signal Fail

Status

A dedicated mechanism for enhanced BER monitoring is provided. BER
monitoring is accomplished by observing the B3 BIP error count. If the incoming
error rate exceeds the thresholds programmed in the APS Threshold Control
register, the signal degrade or signal fail status is reported using a maskable
interrupt. Two thresholds are supported: Signal Degrade (SD) and Signal Fail
(SF). Each threshold is programmable for BER levels from 10

-3

to 10

-9

via the

BER Threshold Register - Line Error Monitoring (B2) and Path Error Monitoring
(B3) on page 4-49

Table 2-3

shows the programming range for the threshold in

the register. The alarm clearing threshold and observation time are automatically
set to 1/10 of the programmed alarm detection threshold.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-19

2.2.5.5 C2 STS Path

Signal Label

The Path Signal label indicates the type of content being carried to the network by
the SPE. A value of 0x13 indicates ATM transport, a value of 0xCF indicates
non-scrambled POS/SDH data, and a value of 0x16 indicates a scrambled
POS/SDH data.

Path Label Mismatch (PLM)--PLM defect sets when C2, different than 0x13

for ATM mode, (In the range of 02FE except FC) is received for five
consecutive frames. A PLM defect is cleared when C2 is found with a matched
value in five consecutive frames (five consecutive frames with any value that does
not create a PLM error). A PLM defect is set when C2 is different than 0xCF (for
unscrambled POS mode) or different than 0x16 (or scrambled POS) is received
during five consecutive frames. A PLM defect is cleared when during five
consecutive frames C2 is found with a matched value.

UNEQ (UNEQuipped)--UNEQ defect is set when C2 = 00, during five

consecutive frames. A UNEQ defect is cleared when C2 does not equal 00 during
five consecutive frames. Receiving an FF value in C2 does not cause the detection
of a new UNEQ or PLM defect, nor does it cause an existing UNEQ or PLM
defect to be terminated.

The default value transmitted by the CX2970x is 13 hex for an ATM mapping.

This value can be changed to any other value via the

Tx Path Signal Label

. A value of 0x16 indicates scrambled POS/SDH data.

2.2.5.6 G1

The G1 byte of the STS Path Overhead is used to convey the Path terminating
status and performance back to the originating STS Path Terminating Element
(PTE). This allows the status and performance of the complete duplex path to be
monitored at either end, or any point along the path. Bits 1-4 are allocated for an
STS Path Remote Error Indication (REI) function and bits 5-7 are used for an
STS Path Remote Defect Indication (RDI) signal.

2.2.5.7 Remote Error

Indication-Path (REI-P)

Accumulation

REI-P (SPE BIP-8 errors detected by B3 by the far end) values are accumulated
in a 16-bit saturating counter. The number of errors detected over the last received
frame is transmitted to the far end via the G1 overhead byte. The legal values of
the 4-bit field are 08. Any other value is considered as zero. Interrupt generation
upon detection of an indication is optional.

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-20

Mindspeed Technologies

29704-DSH-001-B

2.2.5.8 Remote Defect
Indication-Path (RDI-P)

Detection

For enhanced RDI-P (ERDI-P), a defect is detected on the incoming signal when
a defect sequence is received in bits 57 of the G1 overhead byte for ten
consecutive frames. The RDI-P defect is terminated when a no-defect sequence is
received in bits 57 of G1 for ten consecutive frames. ERDI-P defect declaration
is terminated when a 000 or 001 (SONET mode); or 011, 001, or 000 (SDH
mode) is received in bits 57 of G1 for ten consecutive frames.

An RDI-P Defect Status Generation/Termination bit is provided, and Interrupt

generation is optional.

Table 2-5. ERDI-P Receive Defect Coding

G1 bits

5-7

Priority of ERDI-P codes

(for SONET)

Interpretation

SONET

SDH

000

No defects

100

AIS-P, LOP-P,
LOS, LOF, AIS-L
(1-bit RDI-P)

AIS-P, LOP, UNEQ,
LOS, LOF, AIS-L

010

PLM-P, LCD-P

LCD

110

UNEQ-P

UNEQ

001

No defects

101

AIS-P, LOP-P,
LOS, LOF, AIS-L

AIS-P, LOP,
LOS, LOF, AIS-L

011

No defect

111

AIS-P, LOP, UNEQ,
LOS, LOF, AIS-L

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.2 SONET/SDH Framer and Overhead Processor

29704-DSH-001-B

Mindspeed Technologies

2-21

2.2.5.9 Remote Defect
Indication-Path (RDI-P)

Generation

Enhanced RDI-P (ERDI-P) is supported on the transmit path (transmitted via
bites 5-7of G1 overhead byte). Transmitting a single-bit RDI (i.e. non-enhanced
RDI) or totally disabling the transmission of RDI-P is controlled via the

Port

Configuration Register B on page 4-7

. By default, RDI-P transmission is

disabled. Generation of RDI-P defects can be controlled in two different ways; by
total software control or by mixed hardware/software control. Total software
control is enabled by setting the Tx RDI-P Select bit in the

Port Configuration

and programming the

Tx RDI-P and REI-P Register (G1)

on page 4-38

with the value to be transmitted. Mixed hardware/software control is

selected by clearing the Tx RDI-P Select bit in the Port Configuration Register B
register. In this mode the RDI-P value contained in the Tx RDI-P and REI-P
register will be transmitted when no receive defects are present as described in
Table 2-5 and Table 2-6. Enhanced RDI-P defect coding is generated per

Table 2-6

ERDI-P is generated for at least 10 frames. It is deactivated by inserting the

no-defect sequence into the G1 overhead byte for at least 10 frames. In SONET
mode, the value of G1 bits 57 are transmitted as programmed by the Tx RDI-P
and REI-P register according to a trigger event with higher priority. In SDH
mode, the Tx RDI-P and REI-P register value is sent as is. When a defect occurs
while another event is being transmitted, the first event transmission (using
overhead byte G1) terminates first, and then the next defect transmission begins.

A single-bit RDI-P is generated per

Table 2-7

if enhanced RDI-P is disabled

via the

Port Configuration Register B on page 4-7

Table 2-6. ERDI-P Transmit Defect Coding

G1 bits

5-7

Priority of ERDI-P codes

(for SONET)

Trigger

SONET

SDH

000

No defects

010

PLM-P, LCD-P

LCD

110

UNEQ-P

UNEQ

001

No defects

101

AIS-P, LOP-P,
LOS, LOF, AIS-L

AIS-P, LOP,
LOS, LOF, AIS-L

Table 2-7. RDI-P Transmit Defect Coding

G1 bits 5-7

Interpretation

SONET

SDH

000

No defects

100

AIS-P, LOP-P,
LOS, LOF, AIS-L

AIS-P, LOP, UNEQ,
LOS, LOF, AIS-L

2.0 Functional Description

CX2970x

2.2 SONET/SDH Framer and Overhead Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-22

Mindspeed Technologies

29704-DSH-001-B

2.2.5.10 Remote Error
Indication-Path (REI-P)

Insertion

Remote Error Indication on Path (REI-P) is transmitted by inserting the number
of path BIP-8 errors detected over the last frame into bits 14 of the G1 overhead
byte. REI-P can be generated automatically by the transmit overhead processor or
manually controlled via the

Tx RDI-P and REI-P Register (G1) on page 4-38

. The

Tx REI-P Select bit in the

Port Configuration Register B on page 4-7

selects the

source of the transmitted REI-P value.

2.2.5.11 F2 Path User

Channel Byte

The receive overhead processor captures the Path User Channel Byte (F2) from
the incoming receive data stream. The received value can be read via the

Rx Path

User Channel Register (F2, Z3/F3) on page 4-36

A default value of 0x00 is transmitted on the transmit path for the F2 Path

User Channel Overhead byte. The transmitted value may be changed by writing to
the

Tx Path User Channel Register (F2, Z3/F3) on page 4-37

2.2.5.12 Z3/F3 Path

Growth Byte

The receive overhead processor captures the Path Growth Byte (F3) from the
incoming receive data stream. The received value can be read via the

Rx Path

User Channel Register (F2, Z3/F3) on page 4-36

A default value of 0x00 is transmitted on the transmit path for the Z3/F3 Path

Growth Overhead byte. The transmitted value may be changed by writing to the

Tx Path User Channel Register (F2, Z3/F3) on page 4-37

2.2.5.13 Z4/K3Z5/N1

Path Growth Bytes

The receive overhead processor captures the Path Growth Bytes (Z4Z5) from the
incoming receive data stream. The received value can be read via the

Rx Path

Growth Byte Register (Z4/K3, Z5/N1) on page 4-45

A default value of 0x00 is transmitted on the transmit path for the Z4/K3 and

Z5/N1 Path Growth Overhead bytes. The transmitted values may be changed by
writing to the

Tx Path Growth Byte Register (Z4/K3, Z5/N1) on page 4-45

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.3 ATM Cell Processor

29704-DSH-001-B

Mindspeed Technologies

2-23

2.3 ATM Cell Processor

2.3.1 Receive ATM Cell Processor

The receive ATM cell processor performs cell delineation, cell descrambling,
idle/unassigned cell filtering and header error detection or correction.

2.3.1.1 Cell Delineation

The Cell Delineation function enables the identification of cell boundaries. This
process is achieved with the following three states:

HUNT State--Processes the incoming data byte by byte to find a match
between the calculation of HEC for an assumed header field and the
assumed HEC field. Once this match is found, the system enters the
PRESYNC state.

PRESYNC State--Searches for six consecutive correct HECs on a cell by
cell basis. If an incorrect HEC is found, the process returns to the HUNT
state.

SYNC State--The only state that enables transmission of cells to the ATM
layer. If an incorrect HEC is found seven consecutive times, the cell
delineation is assumed to be lost and the process returns to the HUNT
state.

Figure 2-6. Cell Delineation State Machine

Byte by byte

Cell by cell

Correct HEC

Incorrect HEC

6 consecutive

Correct HEC

7 consecutive
Incorrect HEC

101344_007

PRESYNC

SYNC

HUNT

2.0 Functional Description

CX2970x

2.3 ATM Cell Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-24

Mindspeed Technologies

29704-DSH-001-B

2.3.1.2 Out of Cell

Delineation (OCD)

An OCD is declared when the cell delineation state machine is found in the
HUNT or PRESYNC state. OCD is terminated when the cell delineation state
machine is in the SYNC state or when LCD defect is declared.

An OCD Defect Status (upon generation and termination) bit is provided (

See

"Cell, FIFO, and UTOPIA/POS Interrupt Register" on page 4-21.

) along with an

Interrupt.

2.3.1.3 Loss of Cell

Delineation (LCD)

An LCD defect is declared when an OCD anomaly persists for 4 ms. An LCD
defect is terminated when the cell delineation state machine enters the SYNC
state for at least 4 ms.

An LCD Defect Status bit is provided (

See "Cell, FIFO, and UTOPIA/POS

Interrupt Register" on page 4-21.

and an Interrupt upon generation and

termination is optional.

2.3.1.4 HEC Verification

There are two states of operation for HEC verification:

Detection State--The HEC is calculated and the result is compared with
the polynomial found on the HEC octet after subtracting the polynomial
X

+ X

+ 1. If these polynomials are not the same, the cell is

discarded.

Correction State--This procedure is similar to the Detection state except
that when a single bit error is detected in the Correction state, correction is
performed. The cell is then passed and the state machine enters the
Detection state.

When in the SYNC state, the Correction state is entered. If an error is

detected, the state machine enters the Detection state. As long as errors exist, the
state machine remains in the Detection state. If no errors are detected, the state
machine returns to the Correction state. Disabling the Correction state (i.e.,
working in the Detection state only) is optional.

2.3.1.5 Cell

Descrambling

Cell level descrambling is performed by using the self-synchronous descrambler
polynomial X

+ 1.

The descrambler operates only on the information field and is suspended

during the five octets of the header and when in HUNT state. The descrambling
operation can be optionally bypassed.

2.3.1.6 Cell Filtering

Idle and bad header cells are filtered by not being passed to the Rx FIFO.

Figure 2-7. Correction Mode State Machine

101344_008

Detection

State

Correction

State

No error

detected

(cell passed)

Error detected
(cell discarded)

Single bit error detected

(correction and cell passed)

Multibit error detected

(cell discarded)

No error detected

(cell passed)

From PRESYNC state

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.3 ATM Cell Processor

29704-DSH-001-B

Mindspeed Technologies

2-25

2.3.1.7 Performance

Counters

To provide the system with specific knowledge on the quality of the physical
connections, four dedicated counters are available to be read through the
microprocessor port. Each counter is reset to zero value upon reading its content.

16-bit counter--accumulates the number of uncorrectable HEC errors
found

16-bit counter--accumulates the number the cells with correctable HEC
errors

32-bit counter--accumulates the number of error-free cells put in the Rx
FIFO

32-bit counter--accumulates the number of transmitted cells (excluding
idle/unassigned cells)

2.3.1.8 UDF2 Overwrite

The User Defined Field 2 or UDF2 field is available on the UTOPIA interface on
cell transactions. The 16-bit cell transfer format is shown in

Table 2-8

A host processor controlled register (

See "Rx UDF2 Byte Register (ATM

mode)" on page 4-39.

) is used for the UDF2 byte. The register can be considered

a port identifier. The value from the matching port register is placed in the UDF2
field for every cell received. The direction of the transfer across the UTOPIA bus
is from the PHY layer to the ATM layer.

Table 2-8. Rx ATM Cell Structure

Header 1

Header 2

Header 3

Header 4

UDF1 (HEC)

UDF2

Payload 1

Payload 2

Payload 47

Payload 48

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.4 Packet Processor

29704-DSH-001-B

Mindspeed Technologies

2-27

2.4 Packet Processor

2.4.1 Receive Packet Processor

The receive packet processor performs frame delineation, packet extraction, FCS
error detection and payload descrambling. After processing the frame, only the
information part passes to the POS interface.

2.4.1.1 Descrambling

The self-synchronous descrambler, using the polynomial X

+ 1, operates on the

POS data stream. Descrambling is done directly on the data stream coming from
SONET/SDH SPE (before any preprocessing). By default, the descrambler is
enabled.

2.4.1.2 Frame

Delineation

Frame delineation is achieved by searching for the flag character (0x7E) in the
descrambled data stream. The flags are removed upon detection.

2.4.1.3 Byte Destuffing

Byte destuffing is performed by searching for a Control Escape character (0x7D)
in the data stream. When such a character is detected, it is removed, and the
following byte is Exclusive-ORed with the value 0x20.

Table 2-10

lists the

Character Escape Map.

2.4.1.4 Frame Check

Sequence (FCS)

Verification

The FCS value is verified on the entire information field after descrambling and
byte destuffing. The FCS value is generated by a CRC-CCITT (two-byte) or
CRC-32 (four-byte) calculation. If an error is found, the packet is marked as a
defective packet that should be discarded. FCS calculation and insertion can
optionally be disabled.

The CRC-CCITT is two-bytes long and is calculated by the polynomial 1+ X

+ X

. The CRC-32 is four-bytes long and is calculated by the polynomial

1+ X + X

+ X

Table 2-9. The Rx Frame Format

Flag

Information

FCS

Flag

Interframe Fill Or Next Information

0x7E

Variable Length

16/32 bits

0x7E

Table 2-10. Character Escape Map--Byte Destuffing

Sequence

Escaped

7DE5

7D5E

Abort

7D7E

2.0 Functional Description

CX2970x

2.4 Packet Processor

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-28

Mindspeed Technologies

29704-DSH-001-B

2.4.1.5 Performance

Counters

To provide the system with specific knowledge on the quality of the physical
connections, the following five dedicated counters can be read through the
microprocessor port:

16-bit counter--accumulates the number of FCS errors found.

16-bit counter--accumulates the number the packets violating the
minimum length-limit of a packet.

16-bit counter--accumulates the number the packets violating the
maximum length-limit of a packet.

16-bit counter--accumulates the number of aborted packets.

32-bit counter--accumulates the number of error-free packets.

Each counter is reset to a zero value upon reading its content.
When a packet violates the minimum-length criteria, it is marked as defective

and passed to the FIFO. When a packet violates the maximum length criteria, it is
marked as a defective packet and the following bytes are discarded. The packet
that violates the maximum length criteria is marked with the assertion of the POS
Interface Error pin while being read from the FIFO by the link layer. The
maximum and minimum packet length is defined in the Rx-Max_Pack_Length
and Rx-Min_Pack_length registers. A packet is also considered defective if it
does not include at least one data byte in addition to the FCS field (when the FCS
verification option is enabled).

2.4.2 Transmit Packet Processor

The transmit packet processor performs frame generation, frame encapsulation,
FCS error-code calculation, byte-stuffing, and payload scrambling. The FCS,
byte-stuffing, and scrambler can be either disabled or enabled independently.

2.4.2.1 Flag Generator

The frame generator inserts the "Flag-Sequence" whenever an end of packet is
encountered, the transmit FIFO is empty or an error has occurred, and no new
"Start-Of-Packet" is detected.

2.4.2.2 FCS Insertion

The FCS value is calculated over the entire frame before byte-stuffing and
scrambling. The CRC-CCITT is two bytes long, calculated by the polynomial
1 + X

+ X

. The CRC-32 is four bytes long, calculated by the polynomial

1+ X + X

+ X

The FCS bytes are merged into the frame before the closing flag.

2.4.2.3 Byte Stuffing

For enabling transparency, two characters need to be escaped: the Flag Sequence
and the Escape character. When an escape operation is performed on a character,
it is exclusively ORed (XOR operation) with the value of 0x20 and an Escape
character (0x7D) precedes it. This operation is performed only after the FCS
calculation.

Table 2-11. The Tx Frame Format

Flag

Information

FCS

Flag

Interframe Fill Or Next Information

0x7E

Variable Length

16/32 bits

0x7E

2.0 Functional Description

CX2970x

2.5 UTOPIA/POS System Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-30

Mindspeed Technologies

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2.5 UTOPIA/POS System Interface

The interface to the higher layer is a mixed-mode interface that supports UTOPIA
Level 2 for ATM cell applications or Packet Over SONET (POS) Level 2 for
packet based applications. The interface is 16-bits wide and runs at a maximum
frequency of 50 Mhz to support a maximum throughput of 800 Mb/s. The system
interface mode is selected by writing to the ATM/POS bit in the

Port

Configuration Register A on page 4-6

. This bit also selects ATM cell processing or

POS packet processing. Mixed port mode operation is not supported, therefore all
ports of the device should be configured the same.

2.5.1 UTOPIA Level 2 Interface

The interface to the ATM layer is a standard UTOPIA Level 2 interface. Variable
modes of operation are available for both single and multiport ATM Layer device
connections.

The UTOPIA Level 2 bus is a standard bus in which the PHY device functions

as a slave. When one Rx FIFO is filled with a complete cell, the Cell Available
(CLAV) indication is asserted by the FIFO. Depending on the mode of operation
(Direct Status, Multiplexed Status, or One CLAV), the indication is driven out. As
a result, the ATM Layer starts to read or write data to the port. For a detailed
description of the UTOPIA Level 2 Interface, see the ATM Forum Standard
(7/95).

NOTE:

The UTOPIA Level 2 specification defines the Direct Status Indication
and Multiplexed Status Polling as optional. Therefore many ATM layer
devices may not support these types of fifo status indication mechanisms.

2.5.1.1 Direct Status

Indication

In this mode, each port has a dedicated pin for obtaining the fill status of its FIFO.
Regardless of the address driven on the Rx/Tx address bus, the status of all Rx/Tx
FIFOs is reported through corresponding pins. This mode of operation is
recommended when using a single PHY device.

Table 2-13. Recommended Mode of Operation Based on the Number of Ports Supported by the ATM Layer Device

No. of Ports Supported by the ATM Layer Device

14 Ports

531 Ports

Recommended Mode of Operation

Direct Status Indication
One Rx/Tx CLAV

Multiplexed Status Polling
One Rx/Tx CLAV

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-31

2.5.1.2 Multiplexed

Status Polling

In this mode, each port has a dedicated pin for reporting FIFO status. This status
is driven out even if the Rx/Tx address bus only one of the ports within the same
PHY-IC. Thus, if one Rx port is selected by the RxADD bus, all four ports drive
their Status CLAV pins. The same is true for the transmit port of the UTOPIA
interface.

NOTE:

In this mode of operation, all ports within the same PHY device must be
mapped to addresses that have three identical MSBits. Practically, when
performing selection in this mode, the two LSBits of the address bus are
discarded. This mode is recommended when using multiple PHY devices
functioning with the same ATM Layer device.

2.5.1.3 One Rx/Tx CLAV

In One Rx/Tx CLAV mode, all four ports within the same PHY device share the
same pin for reporting their status. After selecting a specific port (by the Tx/Rx
address bus), the associated port drives its FIFO status on the shared CLAV pin
(Clav[0]). This mode of operation is suited for both single- and multi-PHY
devices functioning with a single ATM Layer device.

2.5.1.4 16-bit ATM Cell

Format

The UTOPIA Level 2 Interface supports a 16-bit cell format mode of operation.

Figure 2-8

illustrates the 16-bit ATM cell format.

In the 16-bit mode of operation, the cell is constructed from 54 bytes--five

header bytes, a UDF2 byte, and 48 payload bytes. The HEC byte is considered to
be the fifth byte of the header. The cell bytes are transferred or taken from the
ATM layer as words. Each word contains two bytes. The UDF2 byte is transmitted
with a value of 0x0 and can be overwritten on the receive interface via the

UDF2 Byte Register (ATM mode) on page 4-39

. The UTOPIA port number that

received the cell can be inserted into the UDF2 byte to indicate to the ATM layer
which physical line port the cell was transferred over.

Figure 2-8. 16-Bit Cell Format

Header 1

Header 2

Header 3

Header 4

HEC

Payload 47

Payload 1

UDF2 (User Definable, see

Rx UDF2 Byte Register)

Payload 2

Payload 48

Bit 0

Bit 15

101344_015

2.0 Functional Description

CX2970x

2.5 UTOPIA/POS System Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-32

Mindspeed Technologies

29704-DSH-001-B

2.5.2 UTOPIA Transmit and Receive FIFOs

2.5.2.1 Rx ATM

Interface Cell FIFO

The Rx ATM Interface Cell FIFO compensates for temporary timing differences
between the physical and ATM layer. The ATM cells are inserted into the Rx
FIFO using the recovered clock divided by eight. The ATM cells are drawn from
the Rx FIFO using the UTOPIA Level 2 Interface Rx clock. The FIFO has a
four-cell capacity and provides FIFO management used by the UTOPIA interface.
The FIFO can be reset by software via the port FIFO Control/Status register.

2.5.2.2 Tx ATM Interface

Cell FIFO

This block compensates for temporary timing differences between the physical
layer and the ATM layer. The ATM cells are inserted into the Tx FIFO using the
UTOPIA Level 2 Interface Tx clock. The ATM cells are drawn from the Tx FIFO
using the recovered clock (divided by eight) or the reference clock. The Tx ATM
Interface FIFO has a four-cell capacity and provides the FIFO management used
by the UTOPIA interface.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-33

2.5.3 POS Level 2 Interface

To support packet transfer over SONET/SDH, the CX2970x family provides an
extension to the UTOPIA Level 2 interface. This extension includes additional
pins and dual modes of interfacing to a link layer. Both Selected Status and Polling
Status modes are available for the link layer to obtain Tx/Rx FIFO status of the
chip.
The Start Of Packet (SOP) and End Of Packet (EOP) signals are used to
determine packet boundaries. The Rx/TxMOD pins determine the number of
valid bits (8 or 16) in the last word of the packet being transferred. The
Rx/TxERR pins are used in case any type of error occurs during the current
transfer. Such an error may be of a parity or CRC type. If an error occurs in the
transmit path, an Abort sequence is transmitted, followed by Flag Sequences until
a new SOP is available. On the receive path, when any CRC, RUNT (less than one
byte of an information packet), or Abort Sequence error is detected, the Rx ERR
pin is asserted to flag the link layer to discard the current packet.

NOTE:

For correct POS mode functionality the default values of the following
POS registers should be changed and programmed with the values below:

Rx Max. packet length register (0xFFFF) (

page 4-25

)

Rx FHL register (0x0A) (

page 4-25

)

Rx FLLregister (0x05) (

page 4-26

)

Tx FHL register (0x35) (

page 4-27

)

Tx FLL register (0x30) (

page 4-27

)

Tx FIFO Threshold register (0x20) (

page 4-14

)

2.5.3.1 16-bit POS

Packet Format

The Packet Over SONET/SDH data format is shown in

Figure 2-9

. The POS data

is transmitted/received on a 16-bit basis. The MSB of the data bus are the bits to
be transmitted first. Octets are written to and received from the SONET/SDH
interface Most Significant Bit (MSB) first.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-35

2.5.3.2 POS Signals

The POS level 2 interface includes the following pins:

RxSOP/TxSOP--Rx/Tx Start of Packet indicates the first word of the a
packet.

RxEOP/TxEOP--Rx/Tx End of Packet indicates the last word of a packet.

RxMOD/TxMOD--Rx/Tx Modulo indicates the length of the last data
word in a packet (8/16 bits).

RxERR/TxERR--Rx/Tx error indicates an error was detected during the
transfer of the packet and the packet should be discarded due to abort
sequence, FCS error, etc. (RERR/TERR is asserted only during the
transfer of the last word of a packet).

PTPA--Tx Packet Available indicates that a predefined minimum number
of words (two bytes) is available in the polled Tx FIFO. Logic 1 indicates
that the FIFO is not full. The number of words in the FIFO is less than the
value held by the Tx FLL. Logic 0 indicates that the Tx FIFO is full or
almost full (user programmable by the Tx FHL) and data may not be
transmitted. The PTPA is driven by the chip when the address on the
TADR bus matches the address of one of its ports. When using the PTPA
pin (polling the FIFO's status through a single pin), the DTPA[0] pin is
used. This means that the same physical pin is used for both DTPA[0] and
PTPA functions, depending on the port configuration. The use of the PTPA
pin (for multiplexed status polling) is not available in the Hot Selection
mode of the interface.

STPA--Tx Selected Packet Available. Logic 1 indicates that a minimum
(predefined) number of words are available in the selected FIFO (FIFO to
which data is currently being sent). This means that the number of words
in the FIFO is less than the value held by the Tx FLL. Logic 0 indicates
that the FIFO is full or almost full (user programmable by the Tx FHL).

2.0 Functional Description

CX2970x

2.5 UTOPIA/POS System Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-36

Mindspeed Technologies

29704-DSH-001-B

DTPA[3:0]--Direct Transmit Packet Available indicates the FIFO
associated with each bit of this bus. Logic 1 indicates that the
corresponding FIFO is not full (holds less than minimum predefined
words held in the Tx FLL). The POS processor does not initiate
transmission until the number of words in the FIFO reaches the predefined
number (i.e., DTPA [x] equals zero). Logic 0 indicates that the FIFO is full
or nearly full (determined by the value held in the Tx FHL register).

PRPA--Received Polled Packet Available indicates that data is available in
the polled Rx FIFO. Logic 1 indicates that the polled FIFO has at least one
EOP or holds a predefined number of double words (held in the Rx FHL)
to be read. Logic 0 indicates that the Rx FIFO holds less than the
predefined number of words and no EOP is held. The PRPA is driven by
the chip when the address on the RADR bus matches the address of one of
its ports. When using the PRPA (polling the status of the four ports through
a single pin), the DRPA[0] pin is used. This means that the PRPA and
DRPA[0] are physically the same pin with functionality according to the
programming of the POS interface port.

RVAL--Receive Data Valid. Logic 1 indicates that receive signals are valid
(RxDAT, RxSOP, RxEOP, RxMOD, RxPRTY, RxERR). RVAL is asserted
when data transfer is initiated (conditional on DRPA also being asserted).
RVAL changes to logic 0 on FIFO empty condition (no valid data in the
FIFO) or on EOP Read condition from the FIFO. No data is read from the
FIFO while RVAL is deasserted. RVAL is reasserted after the current FIFO
is deselected. RVAL allows monitoring of the selected FIFO. Other FIFOs
are polled by the DRPA bus.

DRPA[3:0]--Direct Receive Packet Available indicates the FIFO status
associated with each bit of this bus. Logic 1 indicates that the
corresponding FIFO holds at least one EOP or a predefined number of
words to be read. Logic 0 indicates that the FIFO holds no EOP and less
than the predefined number of words.

TxDAT/RxDAT[15:0]--Tx/Rx data bus. Valid only when TxENB/RxENB
are asserted.

TxADR/RxADR[4:0]--Tx/Rx address bus. Used to select which port data
is being written or read and which port is being polled.

TxPRTY/RxPRTY--Tx/Rx data bus parity information indicates that a
parity error should be reported but that data transfer should not be
interrupted.

TxENB/RxENB--Enables the Write/Read transfer operation. In Normal
Selection mode, while TxENB/RxENB are asserted, TxADR/RxADR are
used to poll other FIFOs (using the PRPA and PTPA pins) while data is
transferred from/to the selected port. In Hot Selection mode, when
TxENB/RxENB are asserted, data is being transferred; however, polling is
not available.

TxClk/RxClk--UTOPIA/POS Tx/Rx clock, is used to write/read data
to/from the FIFOs. These clocks should cycle at no higher than 50 MHz,
but not less than the rate that would cause overflows in the FIFOs.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-37

2.5.4 POS Transmit and Receive FIFOs

2.5.4.1 Rx POS

Interface FIFO

The Rx POS Interface FIFO can store up to 256 bytes of data, plus additional
management information. The FIFO logic functionality includes flagging the
availability status of the data in the FIFO, as well as flagging FIFO overrun and
underrun. When an overrun is encountered, the writing of data to the FIFO is
disabled. Writing to the FIFO resumes after the existing FIFO data is read and a
"Start-of-Packet" is detected in the receive path. Thus, the first data word to be
written after an overrun state is the start of a packet. When the POS-interface tries
to read data from an empty FIFO an underrun occurs and invalid data is read;
however, data is written to the FIFO as soon as it becomes available. An interrupt
upon overrun/underrun detection is optional.

The FIFO threshold is the number of bytes available in the FIFO. The FIFO

flags the link layer that free bytes are available, and that the number of available
bytes in the FIFO is more than the value held by the Rx_FHL Register. The
available data indication terminates when the number of available bytes in the
FIFO is less than value held by the Rx_FLL Register. (The FHL and FLL
registers specify the number of bytes in 32-bit granularity.) When a Packet-Abort
command is detected on the receive path, the packet is marked with an error flag,
and no more data is written to the FIFO until a "Start-Of-Packet" is detected.

2.5.4.2 Tx POS Interface

FIFO

The Tx POS Interface FIFO can store up to 256 bytes plus additional
management information. The FIFO logic functionality includes flagging the
availability status of the data in the FIFO, and flagging FIFO overrun and
underrun. When an overrun is detected, the current packet continues to be
transmitted. To avoid redundant packet abortion, an "Abort-Sequence" is
transmitted only when the overran word is transmitted. After transmission of an
"Abort-Sequence," no new data is transmitted until a "Start-Of-Packet" is
detected in the FIFO. The detection of the overrun state does not force the
transmission of an automatic "Abort-Sequence". In a case where the current (or
any other) packet is completely transmitted, no packet abort is transmitted. In case
of underrun (an empty FIFO state during which a packet is transmitted), an abort
sequence is transmitted and all the bytes associated with this packet are replaced
by a Flag sequence. Data transmission resumes after a "Start-of-Packet" is
detected. Generation of an interrupt upon overrun/underrun detection is optional.

The Threshold registers (Tx-FHL and Tx-FLL) determine the

minimum/maximum number of double (four-byte) words in the FIFO. The
Threshold registers also determine under what conditions the FIFO flags the
link-layer as available/unavailable for writing. When the number of words in the
FIFO is greater than Tx-FHL (in four-byte granularity), the FIFO flags the link
layer to stop sending data. When the number of words in the FIFO is less than
Tx-FLL, the FIFO flags the link layer that it is ready for data to be written. The
transmission of packets starts whenever the number of words in the FIFO is
greater than the number held by the Tx-thresh. This register is used to avoid
underrun of the FIFO and allows the user to determine the FIFO characteristics.
The Tx-IFF (Inter-Fill Flag) determines the number of flags that separate each
two packets on the transmission side. Although the value held in the FHL and
FLL registers is in double (four-byte) word boundaries, the packet can also be in
byte boundaries.

2.0 Functional Description

CX2970x

2.5 UTOPIA/POS System Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-38

Mindspeed Technologies

29704-DSH-001-B

2.5.5 POS Transmit Flow Control

The Direct Transmit Packet Available (DTPA)[3:0] provides per-port indication
of the fill status of each corresponding FIFO. When working in single PTA pin
mode, the Polled Transmit Packet Available (PTPA) and Selected Transmit Packet
Available (STPA) pins give an indication of FIFO availability to the link layer.
The PTPA polls the non-selected Tx-FIFO port. The STPA obtains the status of
the currently selected Tx-FIFO port (FIFO to which the data is currently being
sent).

NOTE:

The PTPA pin is physically the same pin as the DTPA[0], which functions
according to the POS interface configuration.

By programming the Tx FHL (FIFO High Limit) and Tx FLL (FIFO Low

Limit), the user can designate the number of double (four-byte) words in the
Tx FIFO on which the available Transmit Packet Available (TPA) indications are
given. TPA indications (STPA, PTPA, DTPA) are determined by the selected
mode of operation. When the number of (double) words in the Tx-FIFO is less
than the Tx FLL, one of the TPA pins is asserted depending on the selected mode
of operation. When the number of (double) words in the Tx FIFO is greater than
the Tx FHL, one of the TPA pins is deasserted.

2.5.6 POS Receive Flow Control

The Direct Receive Packet Available (DRPA)[3:0] provides per-port indication of
the fill status of each corresponding Rx FIFO. The Received Polled Packet
Available (PRPA) pin is used to poll the Rx port selected by the address-bus of the
interface, and indicates that data is valid in the polled Rx FIFO. The Receive
Signal Validity (RVAL) indicates the validity of the receive signal pins. For each
Rx FIFO, low and high limit values are programmable.

For each Rx FIFO, a Rx FHL register allows the user to program the number

of (double) words on which one of the RPA signals is asserted. The RPA signal
asserted depends upon the selected mode of operation. When the number of
(double) words in the Rx FIFO is greater than the value held in the Rx FIFO High
Limit (FHL) (in (double) word granularity), one of the RPA pins is asserted
depending on the selected mode of operation. An RPA pin is also asserted
whenever there is at least one EOP in the Rx FIFO. It is deasserted when the
number of (double) words is less than the value held by the Rx FLL register.

For proper operation of the FIFO, the definition of the FHL value must be

greater than the FLL value. Although the values held in the FHL and FLL
registers are in word boundaries, this does not limit the packet itself to word
boundaries. It can also be in byte boundaries.

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-39

2.5.6.1 Normal

Selection and Hot

Selection Rx Modes of

Operation

The receive path supports both Normal Selection and Hot Selection of the ports.
In Normal Selection mode, the selection of a port is established by driving the
port's address and setting the RxENB pin high for one cycle. Data is available on
the data bus one clock cycle after the assertion of RxENB. This is similar to the
timing of the UTOPIA Level 2 bus.

In Hot Selection mode, port selection is established by changing the address

on the RxADR bus without toggling the RxENB pin. This provides better
performance on the POS interface by saving an idle-cycle. System designers can
determine the proper mode depending upon the system design.

NOTE:

In Hot Selection mode, no polling is performed and the use of four Direct
Status pins (DRPA[3:0]) is required. Also, for reliable operation of the
system when reading data from one PHY-IC to another PHY-IC, it is highly
recommended to use Normal Selection mode, using the idle cycle to avoid
conflicts on the shared bus caused by different varying timing behavior of
different ICs. In Normal Selection mode, several pins can be saved by
using the polling mode, which allows status to be given through a shared
pin (PRPA). An idle-cycle is required, however, when switching between
different ports.

2.0 Functional Description

CX2970x

2.5 UTOPIA/POS System Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-40

Mindspeed Technologies

29704-DSH-001-B

2.5.7 APS Support

The CX2970x family of devices supports unidirectional and bi-directional 1+1
APS and 1:n APS that is transparent to the Layer 2 device.

2.5.8 1+1 APS Operation

In the 1+1 APS operation, the backup link runs in lockstep with an active link.

Table 2-14

lists the output signals on the CX2970x UTOPIA/POS interface

related to the receive direction which are three-stated when the respective
Rx Enable bit is turned off. The Rx Enable bit is located in

Rx FIFO

Control/Status Register on page 4-11

. These signals operate normally when the

enables are turned on.

During normal operation, the protection channel's handshaking signals are

disabled and the receive FIFO is allowed to fill and overflow. When a protection
switch is required, the output signals of the working channel are disabled and the
output signals of the protection channel are enabled. The two links should be
programmed with the same receive addresses by writing Port Rx Addr[4:0] in the
Port Configuration Register A.

Table 2-15

lists the output signals on the CX2970x UTOPIA/POS interface

related to the transmit direction are three-stated when the respective Tx Enable bit
is turned off. The Tx Enable bit is located in

Tx FIFO Control/Status Register on

page 4-12

. These signals operate normally when the enables are turned on.

During normal operation, the protection channel's handshaking signals are

disabled and the transmit FIFO is written to at the same rate as the working
channel's FIFO. When a protection switch is required, the output signals of the
working channel are disabled and the output signals of the protection channel are
enabled. The two links should be programmed with the same Tx Address.

Refer to

Figure 2-9

for the UTOPIA 2 based operation for 1+1 APS. The

figure illustrates both connectivity and operation. The UTOPIA case is shown,
but the same principle applies to the POS option. Consider the direction from A to
B.

Table 2-14. Three-stated Receive Output Signals

Mode

Three-stated Receive Output Signals

ATM

RxClav, RxSOC, RxData[15:0], RxPrty

POS

Rval, RxMod, RxEOP, RxErr, RxData[15:0], RxSOP, RxPrty, DRPA, PRPA

Table 2-15. Three-stated Transmit Output Pins

Mode

Three-stated Receive Output Pins

ATM

TxClav

POS

DTPA, STPA

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-41

2.5.8.1 Unidirectional

1+1 APS

The following steps show how the unidirectional 1+1 switching is performed.

Working TxAddr = Working RxAddr = Protection TxAddr = Protection
RxAddr

Protection channel signals are disabled: TxCLAV, RxCLAV, and RxData.
This includes all signals with a drive direction from the PHY layer to the
ATM layer.

TxData is written into the protection and working channels on side A. The
working channel controls TxCLAV while the protection channel TxCLAV
is disabled.

The protection channel on side A transmits data in lockstep with the
working channel. Both links are hot and synchronized.

The receiver end on side B can pick either stream.

The RxData is driven onto the side A UTOPIA bus by the working
channel. The protection channel RxData does not drive the bus, so this
information is discarded.

A signal fail or other error condition is detected at B on the working
channel and an interrupt is sent to the host processor.

The working channel RxEnable is turned off at B by the host processor.

The protection channel Rx FIFO is reset at B by the host processor.

10.

The protection channel RxEnable is turned on at B by the host processor.

11.

The protection channel is now the active channel on the receiver at B and
controls the RxUTOPIA bus.

12.

The working channel TxEnable is turned off at A by the host processor.

13.

The protection channel TxEnable is turned on at A by the host processor.

NOTE:

The K1/K2 byte signaling follows the standards during this process.
During the switching period, data may be lost.

Figure 2-10. UTOPIA Based 1+1 APS

Hot

Working

Link

Hot

Protection

Link

RxCLAV & RxData

Hot

TxCLAV

TxData

RxAddr

RxCLAV/RxData

TxCLAV

RxEnable = OFF

TxData

RxAddr

RxEnable = ON

TxAddr

TxEnable = OFF

TxEnable = ON

TxCLAV

TxData

RxAddr

RxCLAV/RxData

TxCLAV

RxEnable = OFF

TxData

RxAddr

RxEnable = ON

TxAddr

TxEnable = OFF

TxEnable = ON

RxCLAV & RxData

500034_001

2.0 Functional Description

CX2970x

2.5 UTOPIA/POS System Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-42

Mindspeed Technologies

29704-DSH-001-B

2.5.8.2 Bi-directional

1+1 APS

In addition to the steps used for the unidirectional 1+1 APS, the bi-directional
1+1 APS contains the following steps:

K1/K2 byte signaling on the protection channel causes an interrupt for the
bi-directional case at A.

The working channel RxEnable is turned off at A by the host processor.

The protection channel Rx FIFO is reset at A by the host processor.

The protection channel RxEnable is turned on at A by the host processor.

The working channel TxEnable is turned off at B by the host processor.

The protection channel TxEnable is turned on at B by the host processor.

NOTE:

During the switching period, data may be lost.

2.5.8.3 1:n APS

Operation

The CX2970x supports 1:n APS operation by giving the backup link the ability to
be used as a backup link for the receive link and transmit link independently. This
feature is supported by separate programmable port address for the receive
direction (

See "Port Configuration Register A" on page 4-6.

) and transmit

direction (

See "Port Configuration Register C" on page 4-34.

). The port address

is host processor configurable.

For the unidirectional 1:n APS operation, each port requires a unique receive

and transmit address, while for the bi-directional 1:n APS operation, the receive
and transmit addresses should be configured to the same address.

Refer to

Figure 2-11

for the UTOPIA level 2 based operation for 1:n APS. The

figure illustrates both connectivity and operation. The UTOPIA case is shown but
the same principal applies to POS level 2. In this example, only unidirectional
APS is discussed.

All output signals on the CX2970x UTOPIA/POS interface that drive from the

PHY layer to the ATM/Link layer are three-stated when the enable signal is turned
off. These signals operate normally when enable is turned on.

Figure 2-11. UTOPIA Based 1:n APS

Backup

RxEnable = OFF

RxClav & RxData

RxEnable = ON

Link 1

Link N

TxEnable = OFF

RxCLAV & RxData

TxClav

TxData

RxAddr

TxClav

RxAddr 1

TxData

Utopia 2

Bus

TxAddr

TxAddr 1

TxClav

RxEnable = ON

RxAddr N

TxData

TxAddr N

TxEnable = ON

RxClav & RxData

RxCLAV & RxData

TxClav

TxData

RxAddr

TxClav

RxAddr 1

TxData

Utopia 2

Bus

TxAddr

TxAddr 1

TxClav

RxEnable = ON

RxAddr N

TxData

TxAddr N

TxEnable = ON

RxClav & RxData

RxEnable = ON

RxEnable = OFF

TxEnable = OFF

RxEnable = OFF

TxEnable = OFF

500034_002

Link

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.5 UTOPIA/POS System Interface

29704-DSH-001-B

Mindspeed Technologies

2-43

The steps below show how 1:n unidirectional switching is performed.

The protection channel can be configured to carry traffic with its enable
turned on; in this case, the channel has a unique UTOPIA address. The
channel could also be configured to a working channel UTOPIA address
with the enable turned off.

The 'N' working channels are enabled and each has a unique UTOPIA
address.

The protection channel is active and framed at least with idle traffic or the
traffic that matches its UTOPIA address.

Working channel 1 degrades or fails in the direction from A to B.

K1/K2 byte signaling is sent over the protection channel to indicate the
switch request from B to A. Working channel 1 is requested to bridge to
the protection link.

The protection channel UTOPIA TxAddr is set to the working channel 1
UTOPIA address through the microprocessor interface.

The host turns off the working channel 1 TxEnable and turns on the
protection channel TxEnable.

K1/K2 byte signaling from A to B indicates the bridged channel.

The protection channel RxUTOPIA address is set to the working channel 1
UTOPIA address by the host.

10.

The host turns off the working channel 1 RxEnable and turns on the
protection channel RxEnable.

The protection channel from B to A is still available. A SD/SF detected on

channel 'N' at A could cause the protection channel to backup channel 'N' in the B
to A direction.

NOTE:

During the switching period data may be lost.

2.0 Functional Description

CX2970x

2.6 Microprocessor Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

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Mindspeed Technologies

29704-DSH-001-B

2.6 Microprocessor Interface

2.6.1 Interface Signals

A microprocessor port is provided for management and status purposes. This port
allows the system to read or write to the different registers, and to obtain status
information, i.e., an event causing an interrupt or a port error status. It is also used
for programming the device mode of operation and to define the data to be
transmitted (loading the registers with data of the overhead words, other than the
default defined by the standards).

The CX29704 supports a general microprocessor (

µP) interface.

The following signals are supported:

9-bit address bus

16-bit bidirectional data bus

*CS (Chip Select)

*DSTB (Output Enable)

W/*R (Defines transaction direction)

*READY (Synchronizes between processor and chip frequencies and
indicates when valid data is present on the bus)

*INTR (Signals the

µP that an Interrupt event has occurred)

For details about wave forms and timing, see AC characteristics in

Chapter 9.0

2.6.2 Mode Dependent Register Accesses

Bit 13 of the Port Configuration Register A (address 0x02, 0x42, 0x82, 0xC2)
selects between ATM and POS device operation. When operating in ATM mode,
the POS registers are not accessible.

When a POS register is read from or written to while the device is configured

for ATM mode, the *READY interface signal is not asserted. If the host
microprocessor is waiting for this signal to be asserted, a bus timeout/bus error
results. This also applies if an ATM register is read from or written to while the
device is configured for POS mode.

If the host microprocessor is not using the *READY signal and instead is

using wait states (i.e., waiting the minimum data out delay and then sampling the
data out), the data returned is 0x0.

To avoid the bus time out issues with applications that use the *READY

interface signal, control software should only read and write registers that are
associated with the current mode of the device.

2.0 Functional Description

CX2970x

2.7 Interrupt Mechanism

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-46

Mindspeed Technologies

29704-DSH-001-B

2.7 Interrupt Mechanism

The CX29704 supports interrupt generation upon the occurrence of various
events. Every port can generate an interrupt according to its individual event. It is
the user's responsibility to define the events that are the source of the interrupts.
These events can be masked individually to disable interrupt generation. Interrupt
registers continue to be updated by new events, even if the associated interrupt is
disabled. Upon reading these registers, all bits are cleared. To reset pending
interrupts by software, a dedicated bit is assigned (

See "0x000--Global Reset and

Revision Number Register" on page 4-4.

). For additional details about mask and

status registers, please see the register descriptions in

Chapter 4.0

When unmasking interrupt events, the appropriate interrupt registers should

be read to clear these registers and avoid interrupt generation based on older
events. Upon receiving an interrupt, the Global Interrupt register should be read
to determine the source block of the interrupt. On each port there are four
interrupt source options: Framer Block, Overhead Byte Processor Block (A & B),
and FIFO/UTOPIA Block. Based upon the source block indicated by the Global
Interrupt register, the specific block features a register indicating which event
caused the interrupt.

Following is a list of events that generate interrupts:
·

Framer Block
Change in LOS defect status
Change in SEF defect status
Change in LOF defect status
Rx Frame counter is half-full
Tx Frame counter is half-full

Figure 2-12. CX29704 Interrupt Mechanism Structure

101344_010

Global Mask

i = 0 . . . 2

Global Interrupt

Port 0 Block i Mask

Port 0 Block i Interrupt

Port 1 Block i Mask

Port 1 Block i Interrupt

Port 2 Block i Mask

Port 2 Block i Interrupt

Port 3 Block i Mask

Port 3 Block i Interrupt

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.7 Interrupt Mechanism

29704-DSH-001-B

Mindspeed Technologies

2-47

Overhead Byte Processor Block
BIP8-S error was detected
Change in AIS-L defect status
Change in RDI-L defect status
BIP24-L error was detected
REI-L was detected
New value of K1, K2 overhead bytes was captured
APS state machine enters or exits the inconsistent state
New value of S1 overhead byte was captured
New value of C2 overhead byte was captured
New value of the Path Trace 64-byte (SONET) or 16-byte (SDH)

identifier was captured

Change in LOP-P defect status
Change in AIS-P defect status
Change in ERDI-P bit values
BIP8-P error was detected
Change in REI-P defect status
Line BER (B2) exceeded threshold

Cell/Packet Processor, FIFO and UTOPIA/POS Interface Blocks:
Change in OCD defect status
Change in LCD defect status
Correctable Bad Header (CBH) was detected
Uncorrectable Bad Header (UBH) was detected
Rx FIFO Overrun (RFO) was detected (in POS mode only)
Rx FIFO Underrun (RFU) was detected
Tx FIFO Overrun (TFO) was detected
Tx FIFO Underrun (TFU) was detected
Parity Error (PE) was detected
Start Of Cell Error (SOCE) was detected
Correctable bad header counter is half-full
Uncorrectable bad header counter is half-full
Bad FCS packet was detected
Abort sequence was transmitted
Abort sequence was received
Longer than maximum allowed packet was detected
Smaller than minimum allowed packet was detected
Rx cell/packet counter is half-full

NOTE:

Tx Cell/Packet Counter Is Half-Full Interrupt and Performance Monitor
registers are reset upon read.

2.0 Functional Description

CX2970x

2.8 Alarms Status Serial Interface (ASSI)

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-48

Mindspeed Technologies

29704-DSH-001-B

2.8 Alarms Status Serial Interface (ASSI)

The ASSI provides important permanent status alarm signals for external use. It is
most suitable for driving LEDs (with minimum external logic).

This interface consists of the following three pins:

ASCLK--interface clock

ASDO--drives the data serially

*ASSTB--data strobe

The information stream is constructed from the following status errors:

P-SD

P-SF

L-SD

L-SF

LCD

LOP

AIS-P

AIS-L

LOF

TxC/P

RxC/P

LOS

Tx Cells/Packets (TxC/P) and Rx Cells/Packets (RxC/P) are status bits that

indicate whether valid cells are being transmitted or received (excluding idle
cells). This information is useful for obtaining permanent traffic indications.
Each indication is driven for four clock cycles, one clock cycle for each port,
starting from port 0. The *ASSTB marks the end of the information stream,
which marks the LOS status of Port three.

The external application can be implemented by using shift registers and

latches, or by using PLDs. A maximum application (accessing all signals)
requires only four 8-bit shift registers and latches.

In general, the interface clock (ASCLK) shifts the serial data (ASDO) through

the shift registers. The data strobe (*ASSTB) latches the data (to the appropriate
location) using the latches whose inputs are connected in parallel to the shift
registers' outputs.

For functional timing, see the Alarms Status Serial Interface Functional

Timing in

Chapter 5.0

. For an application example, see

Appendix D

CX2970x

2.0 Functional Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2.9 Diagnostics/Testing

29704-DSH-001-B

Mindspeed Technologies

2-53

2.9.2 Error Insertion

2.9.2.1 Overhead Bytes

An error insertion mechanism is provided for diagnostic purposes. Errors can be
inserted for the following events:

Incorrect header on transmitted cells. This mode enables one-bit header
error insertion by inverting the LSBit of header byte number one, and
multi-bit header error insertion by inverting the two LSBits of header byte
number one.

Incorrect FCS on transmitted packet. This mode allows the transmission of
inverted FCS code of the packet (bit-wise).

Incorrect B3 byte (path BIP-8 overhead byte) on transmitted frame. The
B3 byte is transmitted inverted.

Incorrect B2 bytes (line BIP-24 overhead byte) on transmitted frame.
B2 bytes are transmitted inverted.

Incorrect B1 byte (section BIP-8 overhead byte) on transmitted frame. The
B1 is transmitted inverted.

Incorrect A1, A2 on transmitted frame for emulating an LOF condition.
The third A1 byte and the first A2 byte are transmitted inverted.

2.9.2.2 Loss Of Signal

(LOS) Condition

For emulating an LOS condition, the transmitter can be forced to transmit an
all-0s pattern.

2.9.2.3 Disabling

Scramblers/

Descramblers

Frame/Cell/Payload Scramblers (on the transmit path) and Frame/Cell/Payload
Descramblers (on the receive path) can be disabled for diagnostic purposes.

2.9.3 UTOPIA/POS Activity Detector

UTOPIA/POS activity detector is a debug feature to simplify board development
debug and customer support. The activity detector feature is composed of a
transition detection circuit and a level sensor.

The activity detection circuit indicates if the UTOPIA/POS input signals are

handshaking with the upper layer. The signal direction detected is from the layer 2
device to the CX29704.

The input signals monitored are listed in

Table 2-16

Table 2-16. Transition Detection Input Signals

Mode

Three-stated Receive Output Signals

ATM

TxSOC, TxEnb, TxCLK, RxEnb, RxCLK, TxAdd[4:0], TxPrty, RxAdd[4:0]

POS

TxSOP, TxEnb, TxCLAV, TxCLK, TxMOD, TxEOP, RxEnb, TxErr, RxCLK,
TxAdd[4:0], TxPrty, RxAdd[4:0]

2.0 Functional Description

CX2970x

2.9 Diagnostics/Testing

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

2-54

Mindspeed Technologies

29704-DSH-001-B

2.9.3.1 Transition

Detection

The transition detection circuit indicates if the UTOPIA/POS input signals are
transitioning. The transition detector circuit records the transitions detected in the
transition detection registers (

See "0x050--UTOPIA/POS Rx Transition

Detection Register" on page 4-40.

See "0x051--UTOPIA/POS Tx Transition

Detection Register" on page 4-41.

). As long as there is no transition on the signal,

the transition value of this signal is 0, otherwise the value is 1. The registers are
reset upon read.

2.9.3.2 Level Sensor

The level sensor indicates the level of the transitioned signals detected. The host
processor can read the current values on those input signals. The exceptions
would be TxCLK and RxCLK. TxCLK captures Tx input signals and RxCLK
captures input Rx signals.

The value of those signals is latched by the activity edge signal and is

represented at level sensor registers (

See "0x090--UTOPIA/POS Rx Level

Sensor Register" on page 4-42.

See "0x091--UTOPIA/POS Tx Level Sensor

NOTE:

The level sensor registers must be read first and then the activity registers;
otherwise, the activity registers reset the data that was latched in the level
sensor registers.

2.9.4 JTAG

The CX2970x family supports boundary scan according to IEEE Standard
1149.1.

Support includes the following five pins:

TDO

TDI

TCK (Up to 5 MHz)

TMs

*TRST

Mandatory function support includes the following:

Extent

Bypass

Sample

JTAG ID number

The JTAG chain connects all except the following pins: RxD[0,1,2,3]+,

RxD[0,1,2,3], TxD[0,1,2,3]+, TxD[0,1,2,3], SD[0,1,2,3], PCAP[0,1,2,3],
NCAP[0,1,2,3], REXT[0,1], TMS, TCK, TDI, TDO, TRTS, RefCLK.

2.9.5 Full Scan

The CX2970x family supports full scan. Logic is connected in 50 scan chains.

2.9.6 Block Bypass

This mode enables bypass of the block by connecting the line interface pins
directly to the Serial-to-Parallel/Parallel-to-Serial blocks.

This mode is for manufacturing testing only.

29704-DSH-001-B

Mindspeed Technologies

3-1

3.0 Applications

3.1 ATM Layer Applications

Figure 3-1

illustrates a multiport ATM Layer Device interfacing two CX29704

ICs according to UTOPIA Level 2 specifications. This configuration enables
connection of up to eight CX29704 ICs to one multiport ATM Layer Device. The
modes of operation shown in

Figure 3-1

are Multiplexed Status mode and One

Rx/Tx CLAV mode. Both modes receive and transmit cells from and to one PHY
port at a time. In Multiplexed Status mode, the ATM layer device polls the
Receive and Transmit FIFO status of four PHY ports simultaneously. In this
mode, several multiport devices share the same UTOPIA bus. When any specific
device port is polled for status, all ports within this PHY device provide their
status by the Clav[3:0] pins.

In One Rx/Tx CLAV mode, the ATM Layer device polls the Receive or

Transmit FIFO status of a single PHY port at a time by using the address pins to
select the port. The polled port provides its status on the Rx/TxClav[0] pin. One
Rx/Tx CLAV mode uses the Rx/TxClav[0] pin to obtain the status of any port.
This mode does not use the signals TxClav[3:1] and RxClav[3:1].

CX2970x

3.0 Applications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

3.2 POS Layer Applications

29704-DSH-001-B

Mindspeed Technologies

3-3

Figure 3-2

demonstrates the connection of one CX29704 to one 4-port ATM

Layer device according to the UTOPIA Level 2 Specification. The connection is
performed using Direct Status Indication mode, where there is a direct per port
indication of the FIFO status by dedicated RxClav and TxClav signals. Cell
transmission is made to or from one PHY port at a time. Receive and transmit
channels function simultaneously and independently. This mode supports a 16-bit
data bus.

3.2 POS Layer Applications

Figure 3-3

illustrates a multiport POS Layer Device interfacing two CX29704 ICs

according to the POS interface. This configuration enables the connection of up
to eight CX29704 ICs to one multiport POS Layer Device. The modes of
operation shown in

Figure 3-3

are Selected Status mode and Polling Status mode.

Both modes receive and transmit packets from and to one PHY port at a time. In
the Selected Status mode, the POS Link Layer device polls the Receive and
Transmit FIFO status of four different PHY ports per poll. Polling is performed
using signals DTPA/DRPA[3:0]. DTPA/DRPA[i] indicates the FIFO associated
with port i. In the Selected Status mode, the POS Layer Device polls the Receive
or Transmit FIFO status of a single PHY port at a time, using the PTPA/STPA or
PRPA/RVAL signals and the address pin to select the desired port.

Figure 3-2. Using Direct Status Indication to Interface One CX29704 to One 4-port ATM Layer Device

TxData[15:0]

TxAdd[4:0]

TxSOC
*TxEnb

TxClav[3:0]

TxPrty

TxCLK

RxData[15:0]

RxAdd[4:0]

RxSOC

*RxEnb

RxClav[3:0]

RxPrty

RxCLK

CX29704

4-PORT

ATM LAYER

DEVICE

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

TxD0+/-

RxD0+/-

SD0

TxD1+/-

RxD1+/-

SD1

TxD2+/-

RxD2+/-

SD2

TxD3+/-

RxD3+/-

SD3

101344_003

29704-DSH-001-B

Mindspeed Technologies

4-1

4.0 Register Descriptions

The following memory map provides addresses and descriptions for the registers in the CX2970x family of
devices. Register addresses for the dual port CX29702 device correspond to addresses for ports 0 and 1 listed in
this section. Register addresses for the single port CX29701 device correspond to addresses for port 0.

NOTE:

The convention used in this section is that bit 0 represents the least
significant bit while bit 7 represents the most significant bit. This
convention may contradict the order used in the SONET/SDH standards,
therefore special attention should be paid.

The POS mode registers cannot be accessed in ATM mode and vice versa.
See

Section 2.6.2

for mode dependent register accesses.

Table 4-1. Register Address Mapping (1 of 3)

Address

Register

Page

Number

Port 0

Port 1

Port 2

Port 3

0x000

Global Reset and Revision Number

page 4-4

0x001

Global Configuration

page 4-5

0x002

0x042

0x082

0x0C2

Port Configuration A

page 4-6

0x003

0x043

0x083

0x0C3

Port Configuration B

page 4-7

0x004

0x044

0x084

0x0C4

Port Diagnostic

page 4-9

0x005 0x045

0x085

0x0C5

Port Status

page 4-10

0x006

0x046

0x086

0x0C6

Rx FIFO Control/Status

page 4-11

0x007

0x047

0x087

0x0C7

Tx FIFOs Control/Status

page 4-12

0x008

0x048

0x088

0x0C8

Rx FIFO Status (POS mode)

page 4-13

0x009

0x049

0x089

0x0C9

Tx FIFO Status (POS mode)

page 4-13

0x00A

0x04A

0x08A

0x0CA

Tx FIFO threshold; Tx Inter-Frame-Fill (POS mode)

page 4-14

0x010 Global

Interrupt

page 4-15

0x011 Global

Mask

page 4-16

0x012

0x052

0x092

0x0D2

Framer Interrupt

page 4-17

0x013

0x053

0x093

0x0D3

Framer Mask

page 4-17

0x014

0x054

0x094

0x0D4

Overhead Bytes Processor Interrupt A

page 4-18

0x015

0x055

0x095

0x0D5

Overhead Bytes Processor Mask A

page 4-19

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-2

Mindspeed Technologies

29704-DSH-001-B

0x016

0x056

0x096

0x0D6

Overhead Bytes Processor Interrupt B

page 4-20

0X017

0x057

0x097

0x0D7

Overhead Bytes Processor Mask B

page 4-21

0x018

0x058

0x098

0x0D8

Cell, FIFO and UTOPIA/POS Interrupt

page 4-21

0x019

0x059

0x099

0x0D9

Cell, FIFO and UTOPIA/POS Mask

page 4-23

0x01A

0x05A

0x09A

0X0DA

Rx Minimum Packet Length (POS mode)

page 4-24

0x01B

0x05B

0x09B

0x0DB

Rx Maximum Packet Length (POS mode)

page 4-25

0x01C

0x05C

0x09C

0x0DC

Rx FIFO High Limit (POS mode)

page 4-25

0x01D

0x05D

0x09D

0x0DD

Rx FIFO Low Limit (POS mode)

page 4-26

0x01E

0x05E

0x09E

0x0DE

Tx FIFO High Limit (POS mode)

page 4-27

0x01F

0X05F

0x09F

0x0DF

Tx FIFO Low Limit (POS mode)

page 4-27

0x020

0x060

0x0A0

0x0E0

Section BIP Error Counter (B1)

page 4-28

0x021

0x061

0x0A1

0x0E1

Line BIP Error Counter (B2) (Lower Word)

page 4-28

0x022

0x062

0x0A2

0x0E2

Line BIP Error Counter (B2) (Upper Word)

page 4-29

0x023

0x063

0x0A3

0x0E3

Line REI Error Counter (Lower Word)

page 4-29

0x024

0x064

0x0A4

0x0E4

Line REI Error Counter (Upper Word)

page 4-29

0x025

0x065

0x0A5

0x0E5

Path BIP Error Counter (B3)

page 4-30

0x026

0x066

0x0A6

0x0E6

Path REI Error Counter

page 4-30

0x027

0x067

0x0A7

0x0E7

Uncorrectable Bad Header Counter (ATM mode)

page 4-31

0x028

0x068

0x0A8

0x0E8

Correctable Bad Header Counter (ATM mode)

page 4-31

0x029

0x069

0x0A9

0x0E9

Rx Cell Counter (Lower Word) (ATM mode)

page 4-32

0x02A

0x06A

0x0AA

0x0EA

Rx Cell Counter (Upper Word) (ATM mode)

page 4-32

0x02B

0x06B

0x0AB

0x0EB

Tx Cell Counter (Lower Word) (ATM mode)

page 4-33

0x02C

0x06C

0x0AC

0x0EC

Tx Cell Counter (Upper Word) (ATM mode)

page 4-33

0x02D

0x06D

0x0AD

0x0ED

Rx Frame Counter

page 4-33

0x02E

0x06E

0x0AE

0x0EE

Tx Frame Counter

page 4-34

0x02F

0x06F

0x0AF

0x0EF

Port Configuration C

page 4-34

0x030

0x070

0x0B0

0x0F0

Rx APS Channel (K1, K2)

page 4-34

0x031

0x071

0x0B1

0x0F1

Tx APS Channel (K1, K2)

page 4-35

0x032

0x072

0x0B2

0x0F2

Rx Synchronization Status Message (S1)

page 4-35

0x033

0x073

0x0B3

0x0F3

Tx Synchronization Status Message (S1)

page 4-35

0x034

0x074

0x0B4

0x0F4

Rx Path Signal Label (C2)

page 4-36

0x035

0x075

0x0B5

0x0F5

Tx Path Signal Label (C2)

page 4-36

0x036

0x076

0x0B6

0x0F6

Rx Path User Channel (F2, F3)

page 4-36

Table 4-1. Register Address Mapping (2 of 3)

Address

Register

Page

Number

Port 0

Port 1

Port 2

Port 3

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-3

0x037

0x077

0x0B7

0x0F7

Tx Path User Channel (F2, F3)

page 4-37

0x038

0x078

0x0B8

0x0F8

Path Trace Address (J1)

page 4-37

0x039

0x079

0x0B9

0x0F9

Path Trace Data (J1)

page 4-38

0x03A

0x07A

0x0BA

0x0FA

Rx RDI-P (G1) Register

page 4-38

0x03B

0x07B

0x0BB

0x0FB

Tx RDI-P (G1) Register

page 4-38

0x03C

0x07C

0x0BC

0x0FC

Rx UDF2 Byte Register (ATM mode)

page 4-39

0x03D

0x07D

0x0BD

0x0FD

Tx REI-L Register (M1)

page 4-39

0x040

Engineering Test Register

page 4-39

0x050

UTOPIA/POS Rx Transition Detection

page 4-40

0x051

UTOPIA/POS Tx Transition Detection

page 4-41

0x090

UTOPIA/POS Rx Level Sensor

page 4-42

0x091

UTOPIA/POS Tx Level Sensor

page 4-43

0x101

0x141

0x181

0x1C1

Rx Order Wire Byte (E1, E2)

page 4-43

0x102

0x142

0x182

0x1C2

Tx Order Wire Byte (E1, E2)

page 4-44

0x103

0x143

0x183

0x1C3

Rx Section User Channel (F1) / Rx Section Trace
Path (J0)

page 4-44

0x104

0x144

0x184

0x1C4

Tx Section User Channel (F1) / Tx Section Trace Path
(J0)

page 4-44

0x105

0x145

0x185

0x1C5

Rx Path Growth Bytes (Z4, Z5)

page 4-45

0x106

0x146

0x186

0x1C6

Tx Path Growth Bytes (Z4, Z5)

page 4-45

0x107

0x147

0x187

0x1C7

Rx Bad FCS Counter (POS mode)

page 4-45

0x108

0x148

0x188

0x1C8

Rx Maximum Length Violating Packet Counter
(POS mode)

page 4-46

0x109

0x149

0x189

0x1C9

Rx Minimum Length Violating Packet Counter
(POS mode)

page 4-46

0x10A

0x14A

0x18A

0x1CA

Rx Packet Counter (Lower Word) (POS mode)

page 4-47

0x10B

0x14B

0x18B

0x1CA

Rx Packet Counter (Upper Word) (POS mode)

page 4-47

0x10C

0x14C

0x18C

0x1CB

Rx Aborted Packet Counter (POS mode)

page 4-47

0x10D

0x14D

0x18D

0x1CD

Tx Aborted Packet Counter (POS mode)

page 4-48

0x10E

0x14E

0x18E

0x1CE

Tx Packet Counter (Lower Word) (POS mode)

page 4-48

0x10F

0x14F

0x18F

0x1CF

Tx Packet Counter (Upper Word) (POS mode)

page 4-48

0x110

0x150

0x190

0x1D0

BER Error Counter

page 4-49

0x111

0x151

0x191

0x1D1

BER Threshold

page 4-49

Table 4-1. Register Address Mapping (3 of 3)

Address

Register

Page

Number

Port 0

Port 1

Port 2

Port 3

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-5

0x001--Global Configuration Register

Bit

Type

Name

Default

Description

15:7

Reserved

Reserved for future functionality

R/W

Port 3
Power-down

0 = Port 3 is enabled
1 = Port 3 is in Power-down mode (disabled)

R/W

Port 2
Power-down

0 = Port 2 is enabled
1 = Port 2 is in power-down mode (disabled)

NOTE:

The Power-down mode can only be entered after the FIFO port is

disabled (in the FIFO status and control register)

R/W

Port 1
Power-down

0 = Port 1 is enabled
1 = Port 1 is in Power-down mode (disabled)

NOTE:

The Power-down mode can only be entered after the FIFO port is

disabled (in the FIFO Status and Control register)

R/W

Port 0
Power-down

0 = Port 0 is enabled
1 = Port 0 is in Power-down mode (disabled)

NOTE:

The Power-down mode can only be entered after the FIFO port is

disabled (in the FIFO Status and Control register)

R/W

POS interface
mode

(POS mode only)
0 = Normal selection
1 = Hot selection
(in Hot Selection mode, the ENB pin cannot be deasserted while changing
the address value)

1:0

R/W

UTOPIA/POS flow
control mode

00 = Polling cell/packet indication - 1 RxClav/1 TxClav signal (ATM mode),

or 1 PTPA/1 PRPA signal (POS mode)

01 = Direct Status Indication - 4 TxClav/4 RxClav signals (ATM mode), or 4

DTPA/4 DRPA signals (POS mode)

10 = Multiplexed Status Indication (ATM mode only)

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-6

Mindspeed Technologies

29704-DSH-001-B

Port Configuration Register A

hex address:

Port 0

Port 1

Port 2

Port 3

0x002

0x042

0x082

0x0C2

Bit

Type

Name

Default

Description

Tx Clock Switch

Selects Tx clock switch in case of LOS or SD pin is low
0 = No auto-switch to synthesized clock
1 = Auto-switch to synthesized clock

R/W

19M/8K

0 = The RCLK pin toggles with the 19.44 MHz recovered clock (divided
by 8)
1 = The RCLK pin toggles with the 8 kHz frame sync

R/W

ATM/POS

Selects the mode of operation of the port
0 = ATM
1 = POS

NOTE:

This bit selects ATM cell processing or POS packet processing. It

also selects the mode of the system interface to be UTOPIA or POS.
Mixed port mode operation is not supported, therefore all ports of the
device should be configured the same.

12:8

R/W

Port Rx Add[4:0]

Port 0 = 0
Port 1 = 1
Port 2 = 2
Port 3 = 3

Port receive address. The address assigned to a port to read or poll the
FIFO by the higher link layer through the UTOPIA/POS interface port.
Can be configured differently than the port Tx address for 1:n APS
operation.

R/W

CHEDC

Cell Header Error Detection or Correction mode of operation
0 = Header error detection mode of operation
1 = Header error correction mode of operation

R/W

REI-P Individual
/Frame

0 = Each Path REI is accumulated in the REI-P register
1 = One or more Path REIs are received in the same frame and result in
an accumulated error in the REI-P register

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-7

Port Configuration Register B

hex address:

R/W

PBIP Individual
/Frame

0 = Each Path BIP-8 error is accumulated in the PBIP register
1 = One or more Path BIP-8 errors are detected in a frame and result in
an accumulated error in the PBIP register

R/W

REI-L Individual
/Frame

0 = Each Line REI is accumulated in the REI-L register
1 = One or more Line REIs were received in the same frame and result in
an accumulated error in the REI-L register

R/W

LBIP Individual
/Frame

0 = Each Line BIP-24 error is accumulated in the LBIP register
1 = One or more Line BIP-24 errors are detected in a frame and result in
an accumulated error in the LBIP register

R/W

SBIP Individual
/Frame

0 = Each Section BIP-8 error is accumulated in the SBIP register
1 = One or more Section BIP-8 errors are detected in a frame and result
in an accumulated error in the SBIP register

R/W

Tx Timing

0 = The reference clock is the timing source of the transmit path
1 = The recovered clock (divided by 8) is the timing source of the
transmit path

R/W

SDH/SONET

0 = SDH mode
1 = SONET mode

Bit

Type

Name

Default

Description

Port 0

Port 1

Port 2

Port 3

0x003

0x043

0x083

0x0C3

Bit

Type

Name

Default

Description

R/W

Path BER Enable

0 = The path BER mechanism is disabled
1 = The path (B3) BER mechanism is enabled

R/W

Tx REI-P Select

0 = H/W controlled transmit REI-P

(SONET/SDH bits[1:4] of the G1 byte)

1 = Overwrite REI-P with the value from Tx RDI-P and REI-P register

R/W

Tx RDI-P Select

0 = H/W controlled transmit RDI-P

(SONET/SDH bits[5:7] of the G1 byte)

1 = Overwrite RDI-P with value from Tx RDI-P and REI-P register

NOTE:

When this bit is set to 0 the RDI-P value contained in the Tx RDI-P

and REI-P register will be transmitted when no receive defects are present
as described in

Table 2-6

and

Table 2-7

R/W

Tx M1 Select

0 = H/W controlled transmit M1 byte
1 = Overwrite M1 byte with value from Tx Remote Error Indication register

R/W

Tx K2 Select

0 = H/W controlled transmit K2 RDI-L

(SONET/SDH bits [6:8] of the K2 byte)

1 = Overwrite K2 byte with value from Tx APS Channel Register.

NOTE:

When this bit is set to 0, SONET/SDH bits [1:5] of the K2 byte are

still controlled by the Tx APS Channel Register

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-8

Mindspeed Technologies

29704-DSH-001-B

R/W

Tx Enhanced RDI-P

enable

0 = Enhanced RDI-P is disabled on the transmit side
1 = Enhanced RDI-P is enabled on the transmit side

NOTE:

Both bits (9,10) of this register should be set to logic 1 to enable

ERDI-P

R/W

Tx RDI-P enable

0 = RDI-P is disabled on the transmit side
1 = RDI-P is enabled

R/W

Line BER enable

0 = The line BER mechanism is disabled
1 = The line (B2) BER mechanism is enabled

7:6

R/W

Rx FCS mode

Controlling the FCS Receive mode while in POS mode (FCS is calculated
after descrambling and byte destuffing)
00 = CRC-CCITT (16-bit) is calculated
01 = CRC-32 (32-bit) is calculated
10 = FCS detection is disabled (16 bits are stripped from Information)
11 = FCS detection is disabled (32 bits are stripped from Information)

5:4

R/W

Tx FCS mode

Controlling the FCS Transmit mode while in POS mode (FCS is calculated
before scrambling and byte stuffing)
00 = CRC-CCITT (16-bit) is calculated
01 = CRC-32 (32-bit) is calculated
10 = Reserved for future functionality
11 = Reserved for future functionality

R/W

Tx LDCC

Controlling the Transmit Line DCC port
0 = The port is disabled and no clock or data pins are active.
1 = The port is enabled; data on the TLDCD pin is sampled using the
576 kHz clock pin (TLDCC) and transmitted as part of the SONET/SDH line
overhead bytes

R/W

Rx LDCC

Controlling the Receive Line DCC port
0 = Port is disabled, no clock or data pins are active
1 = Port is enabled; the 576 kHz clock is enabled, and received line DCC
bytes are serially available on the RLDCD pin

R/W

Tx SDCC

Controlling the Transmit Section DCC port
0 = The port is disabled and no clock or data pins are active
1 = The port is enabled; data on the TSDCD pin is sampled using the
192 kHz clock pin (RSDCC) and transmitted as part of the SONET/SDH
section overhead bytes

R/W

Rx SDCC

Controlling the Receive Section DCC port
0 = The port is disabled and no clock or data pins are active
1 = The port and the 192 kHz clock are enabled; Received Section DCC
bytes are serially available on the pin

Bit

Type

Name

Default

Description

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-9

Port Diagnostic Register

hex address:

Port 0

Port 1

Port 2

Port 3

0x004

0x044

0x084

0x0C4

Bit

Type

Name

Default

Description

R/W

Reserved

Reserved for future functionality

R/W

FCS inversion

1 = Inverted insertion of the FCS error code of the packet (bit-wise of the
FCS bits)

13:12

R/W

CHEI[1:0]

Cell Header Error Insertion
00 = No error insertion
01 = One-bit error insertion (second bit of a cell)
11 = Multi-bit error insertion (first two bits of a cell)

R/W

CSD

0 = Cell scrambling enabled or Payload scrambling enabled in POS mode
1 = Cell scrambling disabled or Payload scrambling disabled in POS mode

R/W

CDD

0 = Cell descrambling enabled or Payload descrambling in POS mode
1 = Cell descrambling disabled or Payload descrambling in POS mode

R/W

FSD

0 = Frame scrambling enabled
1 = Frame scrambling disabled

R/W

FDD

0 = Frame descrambling enabled
1 = Frame descrambling disabled

R/W

B3 inversion

1 = Inverted insertion of the B3 overhead byte for diagnostic purposes

R/W

B2 inversion

1 = Inverted insertion of the B2 bytes for diagnostic purposes

R/W

B1 inversion

1 = Inverted insertion of the B1 byte for diagnostic purposes

R/W

LOF insertion

1 = Inversion of the third A1 and the first A2 framing bytes to simulate LOF
defect for diagnostic purposes

R/W

LOS insertion

1 = Insertion of all-0s pattern in the transmit stream to simulate LOS defect
for diagnostic purposes

2:0

R/W

Loopback

Control[2:0]

000 = Loopbacks are disabled
001 = Line Loopback is enabled
010 = SONET Loopback is enabled
011 = ATM/POS Loopback is enabled
101 = Digital Clock Halt--In this mode, all digital clocks are disabled (global
clock from PLL and RxClk/TxClk of each port). This mode can only be
changed by hardware reset.
Disabling the clock of Port 3 also disables the global clock (global PLL clock
divided by 8).
100 = Jitter test mode (Engineering only)

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-10

Mindspeed Technologies

29704-DSH-001-B

Port Status Register

hex address:

Port 0

Port 1

Port 2

Port 3

0x005

0x045

0x085

0x0C5

Bit

Type

Name

Default

Description

15:14

Reserved

Reserved for future functionality

LOL

1 = LOL defect is NOT present

UNEQipped

1 = Unequipped defect is present

PLM status

1 = PLM defect is present

APS Mismatch
status

1 = APS State Machine is in the Inconsistent state

LCD status

1 = LCD defect is present

OCD status

1 = OCD defect is present

RDI-P status

1 = RDI-P defect is present

AIS-P status

1 = AIS-P defect is present

LOP-P status

1 = LOP-P defect is present

RDI-L status

1 = RDI-L defect is present

AIS-L status

1 = AIS-L defect is present

LOF status

1 = LOF defect is present

SEF status

1 = SEF defect is present

LOS status

1 = LOS defect is present

NOTE(S):

* = Upon reset, it is assumed that the receive path is defective. Status bits reflecting the defects are cleared only after valid

data (for the appropriate number of frames) is detected.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-11

Rx FIFO Control/Status Register

hex address:

Port 0

Port 1

Port 2

Port 3

0x006

0x046

0x086

0x0C6

Bit

Type

Name

Default

Description

15:6

Reserved

Reserved for future functionality

R/W

Rx Enable
(APS Control -
ATM and POS)

0 = ATM/POS receive output signals are enabled for this port.
1 = ATM/POS receive output signals are disabled for this port.

For APS applications, the Rx Enable control bit allows the working and
protection link handskaking signals to be enabled or disabled as needed.
Refer to

Section 2.5.7

for a full description.

R/W

Rx UTOPIA reset
(ATM Mode)

1 = Rx UTOPIA reset
This mode is provided for quick recovery on a link fault. By resetting the
FIFO (bit 3) and the UTOPIA (bit 4), the user can configure the port and
disable the data writing to the FIFOs. In this case, the
CLAV/Packet-Available pin is not driven with a value when the port is
selected (because it is usually mapped to another port's address to act as
the hot back-up). As soon as a fault is detected and cleared, the Rx FIFO
can be enabled to begin receiving/transmitting data.

R/W

Rx FIFO reset
(ATM Mode)

1 = Rx FIFO is in Reset mode

2:0

RFS[0:2]
(Engineering Only)

Rx FIFO Status
000 = Rx FIFO does not contain a complete cell
001 = Rx FIFO contains a complete cell
010 = Rx FIFO contains two complete cells
011 = Rx FIFO contains three complete cells
100 = Rx FIFO contains four complete cells

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-15

0x010--Global Interrupt Register

Bit

Type

Name

Default

Description

Port 3 Cell, FIFO and
UTOPIA

1 = Port 3 Cell/Packet Processor, FIFO, or UTOPIA block is the interrupt
source

Port 3 Overhead B

1 = Port 3 Overhead B Byte Processor block is the interrupt source

Port 3 Overhead A

1 = Port 3 Overhead A Byte Processor block is the interrupt source

Port 3 Framer

1 = Port 3 Framer block is the interrupt source

Port 2 Cell, FIFO and
UTOPIA

1 = Port 2 Cell/Packet Processor, FIFO, or UTOPIA block is the interrupt
source

Port 2 Overhead B

1 = Port 2 Overhead B Byte Processor block is the interrupt source

Port 2 Overhead A

1 = Port 2 Overhead A Byte Processor block is the interrupt source

Port 2 Framer

1 = Port 2 Framer block is the interrupt source

Port 1 Cell, FIFO and
UTOPIA

1 = Port 1 Cell/Packet Processor, FIFO, or UTOPIA block is the interrupt
source

Port 1 Overhead B

1 = Port 1 Overhead B Byte Processor block is the interrupt source

Port 1 Overhead A

1 = Port 1 Overhead A Byte Processor block is the interrupt source

Port 1 Framer

1 = Port 1 Framer block is the interrupt source

Port 0 Cell, FIFO and
UTOPIA

1 = Port 0 Cell/Packet Processor, FIFO, or UTOPIA block is the interrupt
source

Port 0 Overhead B

1= Port 0 Overhead B Byte Processor block is the interrupt source

Port 0 Overhead A

1 = Port 0 Overhead A Byte Processor block is the interrupt source

Port 0 Framer

1 = Port 0 Framer block is the interrupt source

NOTE(S):

Interrupt registers are reset upon read.

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-16

Mindspeed Technologies

29704-DSH-001-B

0x011--Global Mask Register

Bit

Type

Name

Default

Description

R/W

Port 3 Cell, FIFO
and UTOPIA

1 = Mask Port 3 Cell/Packet Processor, FIFO, and UTOPIA/POS Interface
Block interrupts

R/W

Port 3 Overhead B

1 = Mask Port 3 Overhead B Byte Processor Block interrupts

R/W

Port 3 Overhead

1 = Mask Port 3 Overhead A Byte Processor Block interrupts

R/W

Port 3 Framer

1 = Mask Port 3 Framer Block interrupts

R/W

Port 2 Cell, FIFO
and UTOPIA

1 = Mask Port 2 Cell/Packet Processor, FIFO, and UTOPIA/POS Interface
Block interrupts

R/W

Port 2 Overhead B

1 = Mask Port 2 Overhead B Byte Processor Block interrupts

R/W

Port 2 Overhead

1 = Mask Port 2 Overhead A Byte Processor Block interrupts

R/W

Port 2 Framer

1 = Mask Port 2 Framer Block interrupts

R/W

Port 1 Cell, FIFO
and UTOPIA

1 = Mask Port 1 Cell/Packet Processor, FIFO, and UTOPIA/POS Interface
Block interrupts

R/W

Port 1 Overhead B

1 = Mask Port 1 Overhead B Byte Processor Block interrupts

R/W

Port 1 Overhead A

1 = Mask Port 1 Overhead A Byte Processor Block interrupts

R/W

Port 1 Framer

1 = Mask Port 1 Framer Block interrupts

R/W

Port 0 Cell, FIFO
and UTOPIA

1 = Mask Port 0 Cell/Packet Processor, FIFO, and UTOPIA/POS Interface
Block interrupts

R/W

Port 0 Overhead B

1 = Mask Port 0 Overhead Bytes Processor

R/W

Port 0 Overhead A

1 = Mask Port 0 Overhead Bytes Processor interrupts

R/W

Port 0 Framer

1 = Mask Port 0 Framer block interrupts

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-18

Mindspeed Technologies

29704-DSH-001-B

Overhead Byte Processor Interrupt Register A

hex address:

Port 0

Port 1

Port 2

Port 3

0x014

0x054

0x094

0x0D4

Bit

Type

Name

Default

Description

R/W

PLM intr

1 = PLM defect was detected or terminated

R/W

PTMIS intr

1 = Path Trace Mismatch occurred

R/W

PSL intr

1 = New value for the C2 Overhead byte was captured. A new value is
captured when five consecutive identical values are received.

R/W

REI-P intr

1 = REI-P error was detected

R/W

PBIP intr

1 = Path BIP-8 error was detected

R/W

RDI-P intr

1 = RDI-P defect was detected or terminated

R/W

AIS-P intr

1 = AIS-P defect was detected or terminated

R/W

LOP-P intr

1 = LOP-P defect was detected or terminated

R/W

S1 intr

1 = New value for bits 47 of the S1 overhead byte was captured

R/W

K1/K2 state intr

1 = APS state machine changed state. This machine changes to the
Inconsistent State if within a 12-frame period; no three consecutive K1
bytes are received with the same value. This machine exits the Inconsistent
State when three consecutive, equal K1 values are received.

R/W

K1/K2 capture intr

1 = New value for the K1 or K2 Overhead bytes was captured. Value is
captured when three consecutive identical frames are received.

R/W

REI-L intr

1 = REI-L error was detected

R/W

LBIP intr

1 = Line BIP-8/24 error was detected

R/W

RDI-L intr

1 = RDI-L defect was detected or terminated

R/W

AIS-L intr

1 = AIS-L defect was detected or terminated

R/W

SBIP intr

1 = Section BIP-8 error was detected

NOTE(S):

Upon reset, it is assumed that the receive path is defective. Status bits reflecting the defects are cleared only after valid

data (for the appropriate number of frames) is detected.

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-20

Mindspeed Technologies

29704-DSH-001-B

Overhead Byte Processor Interrupt Register B

hex address:

Port 0

Port 1

Port 2

Port 3

0x016

0x056

0x096

0x0D6

Bit

Type

Name

Default

Description

15:9

Reserved

Reserved for future functionality

P-SD

1 = Path Signal Degrade. An interrupt is generated when the number of
B3 errors exceeds the threshold set.

P-SF

1 = Path Signal Fail. An interrupt is generated when the number of B3
errors exceeds the threshold set.

L-SD

1 = Line Signal Degrade. An interrupt is generated when the number of
B2 errors exceeds the threshold set.

Rx Runt Packet
error

1 = An illegal (less than one byte of information) packet was found on the
receive path (POS mode).

Rx FCS error

1 = FCS error was found on the receive path (POS mode)

L-SF

1 = Line Signal Fail. An interrupt is generated when the number of B2
errors exceeds the threshold set.

Rx Abort

1 = An abort sequence was received (POS mode).

Tx Abort

1 = An abort sequence was transmitted due to an error (POS mode).

Unequipped intr

1 = Unequipped error was detected.

NOTE(S):

* = Upon reset, it is assumed that the receive path is defective. Status bits reflecting the defects are cleared only after valid

data (for the appropriate number of frames) is detected.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-21

Overhead Byte Processor Mask Register B

hex address:

Cell, FIFO, and UTOPIA/POS Interrupt Register

hex address:

Port 0

Port 1

Port 2

Port 3

0x017

0x057

0x097

0x0D7

Bit

Type

Name

Default

Description

15:9

Reserved

Reserved for future functionality

R/W

P-SD mask

1 = Path signal degrade mask

R/W

P-SF mask

1 = Path signal fail mask

R/W

L-SD mask

1 = Line signal degrade mask

R/W

Runt Packet mask

1 = Runt (less than one byte of information) packet intr mask

R/W

FCS Error mask

1 = FCS error intr mask

R/W

L-SF mask

1 = Line signal fail mask

R/W

Rx Abort mask

1 = Rx abort intr mask

R/W

Tx Abort mask

1 = Tx abort intr mask

R/W

Unquipped mask

1 = Unequipped error mask

NOTE(S):

* = Upon reset, it is assumed that the receive path is defective. Status bits reflecting the defects are cleared only after valid

data (for the appropriate number of frames) is detected.

Port 0

Port 1

Port 2

Port 3

0x018

0x058

0x098

0x0D8

Bit

Type

Name

Default

Description

R/W

PEMAL intr

1 = Packet exceeded maximum length limit

R/W

PEMIL intr

1 = Packet exceeded minimum length limit

R/W

TCCHF intr

1 = Tx Cell/Packet Counter is half-full

R/W

RCCHF intr

1 = Rx Cell/Packet Counter is half-full

R/W

UBHCHF intr

1 = Uncorrectable Bad Header Counter is half-full

R/W

CBHCHF intr

1 = Correctable Bad Header Counter is half-full

R/W

SOCE intr

1 = Start Of Cell Error
Generated when TxSOC is sampled high and a cell is already being
transmitted

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-25

Rx Maximum Packet Length Register (POS mode)

hex address:

NOTE:

The value of these registers should be reprogrammed to 0xFFFF.

Rx FIFO High-Limit (Rx FHL) Register (POS mode)

hex address:

NOTE:

The value of these registers should be reprogrammed to 0x0A.

Port 0

Port 1

Port 2

Port 3

0x01B

0x05B

0x09B

0x0DB

Bit

Type

Name

Default

Description

15:0

R/W

Max_Pack_Length

0x0600

Determines the maximum length of a packet (POS mode). Packets
violating this limit are marked as error packets. An interrupt upon
detection of an error is optional.

Port 0

Port 1

Port 2

Port 3

0x01C

0x05C

0x09C

0x0DC

Bit

Type

Name

Default

Description

15:6

Reserved

Reserved for future functionality.

5:0

R/W

Rx FIFO High Limit

0x2F

Determines the number of double words (32-bit) that is the limit for
Rx FIFO full condition. When the number of double words in the Rx FIFO
exceeds the [predefined] value, the DRPA and PRPA pins are asserted.
When at least one End-Of-Packet resides in the Rx FIFO, the RPA signals
are asserted regardless of the quantity of words in the FIFO. The RPA
pins are not deasserted when the number of double words is less than
the predefined value. Although the value specified in this register allows
setting boundaries to the FIFO in words (two bytes), the POS packet can
end within byte boundaries, as described in the POS interface.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-27

Tx FIFO High-Limit (Tx FHL) Register (POS mode)

hex address:

NOTE:

The value of these registers should be reprogrammed to 0x35.

Tx FIFO Low Limit (Tx FLL) Register (POS mode)

hex address:

NOTE:

The value of those registers should be reprogrammed to 0x30.

Port 0

Port 1

Port 2

Port 3

0x01E

0x05E

0x09E

0x0DE

Bit

Type

Name

Default

Description

15:6

Reserved

Reserved for future functionality.

5:0

R/W

Tx FIFO High Limit

0x2F

Determines the number of double words (32-bit) in the Tx FIFO on which
the DTPA and PTPA pins are deasserted. When the number of double
words in the Tx FIFO exceeds this [predefined] value, the TPA signals are
negated (according to the POS interface functionality) to reflect a Tx FIFO
full condition. When the number of double words is less than this value,
the DTPA and PTPA pins are not asserted. Although the number specified
in this register sets FIFO boundaries in words (two bytes), the POS
packet can end within byte boundaries as described in the POS interface.

Port 0

Port 1

Port 2

Port 3

0x01F

0x05F

0x09F

0x0DF

Bit

Type

Name

Default

Description

15:6

Reserved

Reserved for future functionality.

5:0

R/W

Tx FIFO Low Limit

0x08

Determines the number of double words (32-bit), which is the limit for
Tx FIFO empty condition. When Tx FIFO contain less double words than
the [predefined] value, the DRPA and PRPA pins are asserted. Although
the number specified in this register sets FIFO boundaries in double
words (four bytes), the POS packet can end within byte boundaries as
described in the POS interface.

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-28

Mindspeed Technologies

29704-DSH-001-B

Section BIP Error Counter Register (B1)

hex address:

Line BIP Error Counter Register (B2), Lower Word

hex address:

Port 0

Port 1

Port 2

Port 3

0x020

0x060

0x0A0

0x0E0

Bit

Type

Name

Default

Description

15:0

SBIP[15:0]

Section BIP-8 error 16-bit saturating counter.

This counter reflects the number of Section BIP-8 errors (Individual or
Frame mode) detected since the last time this counter was read. The
counter should be polled at least once per second to avoid saturation.
Counter is reset upon read.

NOTE(S):

* Performance Monitor Registers are reset upon read.

Port 0

Port 1

Port 2

Port 3

0x021

0x061

0x0A1

0x0E1

Bit

Type

Name

Default

Description

15:0

LBIP[15:0]

Line BIP-24 Error, 32-bit saturating counter.

This counter reflects the number of line BIP-8 errors (Individual or Frame
mode) detected since the last time this counter was read. This is the
lower word of the counter and should be read first. The counter is reset
upon read.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-29

Line BIP Error Counter Register (B2), Upper Word

hex address:

Line REI Error Counter Register, Lower Word

hex address:

Line REI Error Counter Register, Upper Word

hex address:

Port 0

Port 1

Port 2

Port 3

0x022

0x062

0x0A2

0x0E2

Bit

Type

Name

Default

Description

15:0

LBIP[31:16]

Line BIP-24 Error, 32-bit saturating counter.

This is the upper word of the counter and should be read immediately
after the lower word to avoid loss of information.

Port 0

Port 1

Port 2

Port 3

0x023

0x063

0x0A3

0x0E3

Bit

Type

Name

Default

Description

15:0

REI-L[15:0]

REI-L 32-bit saturating counter.

This counter reflects the number of REI-Ls (Individual or Frame mode)
detected since the last time this counter was read. This is the lower word
of the counter and should be read first. The counter is reset upon read.

Port 0

Port 1

Port 2

Port 3

0x024

0x064

0x0A4

0x0E4

Bit

Type

Name

Default

Description

15:0

REI-L[31:16]

REI-L 32-bit saturating counter.

This is the upper word of the counter and should be read immediately
after the lower word to avoid loss of information.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-33

Tx Cell Counter Register, Lower Word

hex address:

Tx Cell Counter Register, Upper Word

hex address:

Rx Frame Counter Register (Add: 0x02D, 0x06D, 0x0AD, 0x0ED)

hex address:

Port 0

Port 1

Port 2

Port 3

0x02B

0x06B

0x0AB

0x0EB

Bit

Type

Name

Default

Description

15:0

TxCell[15:0]

Transmit cell 32-bit saturating counter.

This counter reflects the number of cells that were drawn from the Tx FIFO
and transmitted into the line since the last time this counter was read. This
number does not include generated idle/unassigned cells. This is the lower
word of the counter and should be read first. The counter is reset upon
read.

Port 0

Port 1

Port 2

Port 3

0x02C

0x06C

0x0AC

0x0EC

Bit

Type

Name

Default

Description

31:16

TxCell[31:16]

Transmit cell 32-bit saturating counter.

This is the upper word of the counter and should be read immediately after
the lower word to avoid loss of information.

Port 0

Port 1

Port 2

Port 3

0x02D

0x06D

0x0AD

0x0ED

Bit

Type

Name

Default

Description

15:0

RxFrame[15:0]

Receive frame 16-bit saturating counter.

This counter reflects the number of frames received since the last time
this counter was read. The counter is reset upon read.

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-34

Mindspeed Technologies

29704-DSH-001-B

Tx Frame Counter Register

hex address:

Port Configuration Register C

hex address:

Rx APS Channel Register (K1, K2)

hex address:

Port 0

Port 1

Port 2

Port 3

0x02E

0x06E

0x0AE

0x0EE

Bit

Type

Name

Default

Description

15:0

TxFrame[15:0]

Transmit frame 16-bit saturating counter.

This counter reflects the number of frames transmitted since the last time
this counter was read. Counter is reset upon read.

Port 0

Port 1

Port 2

Port 3

0x02F

0x06F

0x0AF

0x0EF

Bit

Type

Name

Default

Description

15:5

Reserved

Reserved for future functionality

4:0

R/W

Port Tx Add[4:0]

Port 0 = 0
Port 1 = 1
Port 2 = 2
Port 3 = 3

Port transmit address. The address assigned to a port to write or poll
the FIFO by the higher link layer through the UTOPIA/POS interface port.
It can be configured differently than the port Rx address for 1:n APS
operation.

Port 0

Port 1

Port 2

Port 3

0x030

0x070

0x0B0

0x0F0

Bit

Type

Name

Default

Description

15:8

K1[7:0]

These bytes are the received K1 and K2 overhead bytes, which are used for
automatic protection switching purposes. A new value is captured if new K1
value is received for three consecutive frames. An interrupt is generated upon
capture.

7:0

K2[7:0]

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-35

Tx APS Channel Register (K1, K2)

hex address:

Rx Synchronization Status Message Register (S1)

hex address:

Tx Synchronization Status Message Register (S1)

hex address:

Port 0

Port 1

Port 2

Port 3

0x031

0x071

0x0B1

0x0F1

Bit

Type

Name

Default

Description

15:8

R/W

K1[7:0]

Transmit K1 overhead byte

7:0

R/W

K2[7:0]

Transmit K2 overhead byte.

NOTE:

SONET/SDH bits [6:8] of the K2 byte are controlled automatically if the

`Tx K2 Select' bit in the Port Configuration Register B register is set to 0.

Port 0

Port 1

Port 2

Port 3

0x032

0x072

0x0B2

0x0F2

Bit

Type

Name

Default

Description

15:8

Unused

7:0

S1[7:0]

This byte is assigned for synchronization status messages. Bits [3:0] are
assigned for sychronization status messages. An interrupt is generated upon
capture of a new S1 value.

NOTE:

These bits correspond to SONET/SDH bits [5:8].

Port 0

Port 1

Port 2

Port 3

0x033

0x073

0x0B3

0x0F3

Bit

Type

Name

Default

Description

15:8

Unused

7:0

R/W

S1[7:0]

This byte is assigned for synchronization status messages.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-39

Rx UDF2 Byte Register (ATM mode)

hex address:

Tx REI-L (M1) Register

hex address:

0x040--Engineering Test Register

Port 0

Port 1

Port 2

Port 3

0x03C

0x07C

0x0BC

0x0FC

Bit

Type

Name

Default

Description

15:8

Unused

7:0

R/W

UDF2[7:0]

Port 0 = 0x00
Port 1 = 0x01
Port 2 = 0x02
Port 3 = 0x03

This value is placed into the User defined UDF2 byte of the ATM cell
that is passed to the ATM layer device via the UTOPIA interface. The
default values implement a port identifier mechanism.

Port 0

Port 1

Port 2

Port 3

0x03D

0x07D

0x0BD

0x0FD

Bit

Type

Name

Default

Description

15:8

Reserved

Reserved for future functionality

7:0

R/W

M1[7:0]

Line Remote Error Indication (REI-L) byte (M1) transmitted value.

NOTE:

The M1 byte is controlled automatically if the `Tx M1 Select' bit in the

Port Configuration Register B register is set to 0.

Bit

Type

Name

Default

Description

15:12

R/W

Port 3 Tx Clock

1000

11:8

R/W

Port 2 Tx Clock

0100

7:4

R/W

Port 1 Tx Clock

0010

3:0

R/W

Port 0 Tx Clock

0001

NOTE:

For proper device operation the values in this register must not be changed.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-41

0x051--UTOPIA/POS Tx Transition Detection Register

Bit

Type

Name

Default

Description

15:12

TxCLK Activity

(ATM/POS)

1 = TxCLK activity detected
0 = No TxCLK activity detected since last read

TxSOC/SOP Activity

(ATM/POS)

1 = TxSOC/SOP activity detected
0 = No TxSOC/SOP activity detected since last read

TxEOP Activity

(POS)

1 = TxEOP activity detected
0 = No TxEOP activity detected since last read

TxErr Activity

(POS)

1 = TxErr activity detected
0 = No TxErr activity detected since last read

TxMod Activity

(POS)

1 = TxMod activity detected
0 = No TxMod activity detected since last read

TxPrty Activity

(ATM/POS)

1 = TxPrty activity detected
0 = No TxPrty activity detected since last read

TxEnb Activity

(ATM/POS)

1 = TxEnb activity detected
0 = No TxEnb activity detected since last read

TxAdd[4] Activity

(ATM/POS)

1 = TxAdd[4] activity detected
0 = No RxAdd[4] activity detected since last read

TxAdd[3] Activity

(ATM/POS)

1 = TxAdd[3] activity detected
0 = No RxAdd[3] activity detected since last read

TxAdd[2] Activity

(ATM/POS)

1 = TxAdd[2] activity detected
0 = No RxAdd[2] activity detected since last read

TxAdd[1] Activity

(ATM/POS)

1 = TxAdd[1] activity detected
0 = No RxAdd[1] activity detected since last read

TxAdd[0] Activity

(ATM/POS)

1 = TxAdd[0] activity detected
0 = No RxAdd[0] activity detected since last read

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-43

0x091--UTOPIA/POS Tx Level Sensor Register

Rx Order Wire Byte Register (E1, E2)

hex address:

Bit

Type

Name

Default

Description

15:11

TxSOC/SOP Level

(ATM/POS)

1 = TxSOC/SOP HIGH activity detected
0 = TxSOC/SOP LOW activity detected

TxEOP Level

(POS)

1 = TxEOP HIGH activity detected
0 = TxEOP LOW activity detected

TxErr Level

(POS)

1 = TxErr HIGH activity detected
0 = TxErr LOW activity detected

TxMod Level

(POS)

1 = TxMod HIGH activity detected
0 = TxMod LOW activity detected

TxPrty Level

(ATM/POS)

1 = TxPrty HIGH activity detected
0 = TxPrty LOW activity detected

TxEnb Level

(ATM/POS)

1 = TxEnb HIGH activity detected
0 = TxEnb LOW activity detected

TxAdd[4] Level

(ATM/POS)

1 = TxAdd[4] HIGH activity detected
0 = TxAdd[4] LOW activity detected

TxAdd[3] Level

(ATM/POS)

1 = TxAdd[3] HIGH activity detected
0 = TxAdd[3] LOW activity detected

TxAdd[2] Level

(ATM/POS)

1 = TxAdd[2] HIGH activity detected
0 = TxAdd[2] LOW activity detected

TxAdd[1] Level

(ATM/POS)

1 = TxAdd[1] HIGH activity detected
0 = TxAdd[1] LOW activity detected

TxAdd[0] Level

(ATM/POS)

1 = TxAdd[0] HIGH activity detected
0 = TxAdd[0] LOW activity detected

NOTE(S):

This register is reset by reading the UTOPIA/POS Activity Detector register.

Port 0

Port 1

Port 2

Port 3

0x101

0x141

0x181

0x1C1

Bit

Type

Name

Default

Description

15:8

R/W

E2[7:0]

Receive Order Wire overhead bytes

7:0

R/W

E1[7:0]

Receive Order Wire overhead bytes

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-44

Mindspeed Technologies

29704-DSH-001-B

Tx Order Wire Byte Register (E1, E2)

hex address:

Rx Section User Channel Register (F1) and Rx Section Trace (J0)

hex address:

Tx Section User Channel Register (F1) and Tx Section Trace (J0)

hex address:

Port 0

Port 1

Port 2

Port 3

0x102

0x142

0x182

0x1C2

Bit

Type

Name

Default

Description

15:8

R/W

E2[7:0]

Transmit Order Wire overhead bytes

7:0

R/W

E1[7:0]

Transmit Order Wire overhead bytes

Port 0

Port 1

Port 2

Port 3

0x103

0x143

0x183

0x1C3

Bit

Type

Name

Default

Description

15:8

J0[7:0]

Received Section Trace byte. This byte is not in the message format like J1,
but rather a single, general-purpose byte.

7:0

R/W

F1[7:0]

Received Order Wire overhead bytes.

Port 0

Port 1

Port 2

Port 3

0x104

0x144

0x184

0x1C4

Bit

Type

Name

Default

Description

15:8

R/W

J0[7:0]

Transmit Section Trace byte. This byte is not in the message format like J1,
but rather a single, general-purpose byte.

7:0

R/W

F1[7:0]

Transmit Order Wire overhead bytes.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-47

Rx Packet Counter Register, Lower Word (POS mode)

hex address:

Rx Packet Counter Register, Upper Word (POS mode)

hex address:

Rx Aborted Packet Counter Register (POS mode)

hex address:

Port 0

Port 1

Port 2

Port 3

0x10A

0x14A

0x18A

0x1CA

Bit

Type

Name

Default

Description

15:0

Rx Pack[15:0]

Receive Packet 32-bit saturating counter.

This counter reflects the number of packets received and transferred into the
Rx FIFO since the last time the counter was read. This is the lower word of
the counter and should be read first. The counter is reset upon read. Each
EOP is counted when entering the FIFO.

Port 0

Port 1

Port 2

Port 3

0x10B

0x14B

0x18B

0x1CB

Bit

Type

Name

Default

Description

15:0

Rx Pack[31:16]

Receive Packet 32-bit saturating counter.

This is the upper word of the counter and should be read immediately
after the lower word to avoid loss of information.

Port 0

Port 1

Port 2

Port 3

0x10C

0x14C

0x18C

0x1CC

Bit

Type

Name

Default

Description

15:0

Rx Ab_Packet[15:0]

This counter holds the number of received aborted packets.
This register is reset to its default value upon reading.

4.0 Register Descriptions

CX2970x

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

4-48

Mindspeed Technologies

29704-DSH-001-B

Tx Aborted Packet Counter Register (POS mode)

hex address:

Tx Packet Counter Register, Lower Word (POS mode)

hex address:

Tx Packet Counter Register, Upper Word (POS mode)

hex address:

Port 0

Port 1

Port 2

Port 3

0x10D

0x14D

0x18D

0x1CD

Bit

Type

Name

Default

Description

15:0

Tx Ab_Packet[15:0]

This counter holds the number of transmitted packets that were aborted.
This register is reset to its default value upon reading.

Port 0

Port 1

Port 2

Port 3

0x10E

0x14E

0x18E

0x1CE

Bit

Type

Name

Default

Description

15:0

TxPack[15:0]

Transmit Packet 32-bit saturating counter.

This counter reflects the number of packets drawn from the Tx FIFO
and transmitted into the line since the last time this counter was read.

This is the lower word of the counter and should be read first. The
counter is reset upon read. Each EOP is counted when read from the
FIFO.

Port 0

Port 1

Port 2

Port 3

0x10F

0x14F

0x18F

0x1CF

Bit

Type

Name

Default

Description

31:16

TxPack[31:16]

Transmit Packet 32-bit saturating counter.

This is the upper word of the counter and should be read immediately
after the lower word to avoid loss of information.

CX2970x

4.0 Register Descriptions

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

29704-DSH-001-B

Mindspeed Technologies

4-49

BER Status Register

hex address:

BER Threshold Register - Line Error Monitoring (B2) and Path Error Monitoring (B3)

hex address:

Port 0

Port 1

Port 2

Port 3

0x110

0x150

0x190

0x1D0

Bit

Type

Name

Default

Description

15:4

P-SF

1 = Path Signal Fail defect detected

P-SD

1 = Path Signal Degrade defect detected

L-SF

1 = Line Signal Fail defect detected

L-SD

1 = Line Signal Degrade defect detected

Port 0

Port 1

Port 2

Port 3

0x111

0x151

0x191

0x1D1

Bit

Type

Name

Default

Description

15:12

R/W

P-SF Threshold

0100

Threshold exponent value for setting path signal fail error status.

11:8

R/W

P-SD Threshold

0110

Threshold exponent value for setting path signal degrade error status.

7:4

R/W

L-SF Threshold

0011

Threshold exponent value for setting line signal fail error status.

3:0

R/W

L-SD Threshold

0110

Threshold exponent value for setting line signal degrade error status.

5.0 Functional Timing

CX2970x

5.1 ATM Layer Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

5-2

Mindspeed Technologies

29704-DSH-001-B

5.1.1.2 Transmit

Figure 5-3

illustrates the functional timing of one TxClav mode of operation.

TxClav indicates whether the PHY port, whose address was on TxAdd in the

previous clock cycle, can accept a complete cell. The ATM layer selects a PHY
port which receives the next cell by placing its address on TxAdd when *TxEnb is
not asserted and asserting *TxEnb on the next cycle.

Figure 5-2. Receive One Rx/Tx CLAV Functional Timing

RxCLK (I)

RxAdd (I)

RxClav (O)

*RxEnb (I)

RxData (O)

RxSOC (O)

P47P48

P45P46

P43P44

H3H4

H1H2

Hi-Z

N-1

PHY M

PHY N

P47P48

Hi-Z

H1H2

Hi-Z

101344_018

Figure 5-3. Transmit One Rx/Tx CLAV Functional Timing

101344_019

TxCLK (I)

TxAdd (I)

TxClav (O)

*TxEnb (I)

TxData (I)

TxSOC (I)

P39P40

P41P42

P43P44

P45P46

H1H2 H3H4

P37P38

P35P36

P47P48

Hi-Z

N+1

N+2

N-2

N-1

PHY M

PHY N

CX2970x

5.0 Functional Timing

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

5.1 ATM Layer Interface

29704-DSH-001-B

Mindspeed Technologies

5-5

5.1.3 Multiplexed Status Polling

5.1.3.1 Receive

Figure 5-6

illustrates functional timing of Multiplexed Status Polling mode.

RxClav0RxClav3 indicate whether the PHY ports, which belong to the

address group of the address that was on RxAdd in the previous clock cycle, have
a complete cell available. The ATM layer selects a PHY port from which to
receive the next cell by placing its address on RxAdd when *RxEnb is not
asserted, and by asserting *RxEnb on the next cycle.

Figure 5-6. Receive Multiplexed Status Polling Functional Timing

101344_022

RxCLK (I)

RxAdd (I)

RxClav0 (O)

RxClav1 (O)

RxClav2 (O)

RxClav3 (O)

*RxEnb (I)

RxData (O)

RxSOC (O)

P43P44

P45P46

P47P48

H6H5

H1H2

H3H4

H1H2

PHY 13

PHY 1

P47P48

P45P46

P43P44

PHY 25

5.0 Functional Timing

CX2970x

5.1 ATM Layer Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

5-8

Mindspeed Technologies

29704-DSH-001-B

5.1.5 Multiport, Hot Selection Mode

Figure 5-9

illustrates the hot selection of a multiport device. Direct Status

indication is obtained by the DRPA pins. This example presents four ports with
each pair packed in the same IC device (Ports 1 and 2 in the same IC and Ports 3
and 4 in the same IC).

NOTE:

The transition between the selection of Port 1 and Port 2 is done without a
dead cycle (no deassertion of the RENB pin is required). A transition
between two ports of different devices, however, requires the deassertion
of the RENB pin and thus causes a dead cycle.

Figure 5-9. Multiport, Hot Selection Mode, Functional Timing

101344_025

Dead

Cycle

Two PHYs in

different ICs

Two PHYs within

the same IC

RFCLK

DRPA[1]

DRPA[2]

DRPA[3]

DRPA[4]

RENB

RADR[4:0]

RVAL

RDAT[15:0]

RPRTY

RMOD

RSOP

REOP

RERR

Selected

PHY

NULL

PA(1)

PA(2)

PA(3)

PA(4)

1Fh

5.0 Functional Timing

CX2970x

5.1 ATM Layer Interface

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

5-10

Mindspeed Technologies

29704-DSH-001-B

5.1.7 RVAL and RPA Functionality

Figure 5-11

illustrates RPA and RVAL functionality while functioning in Hot

Selection mode.

In the first transfer, the DRPA[1] pin is deasserted to reflect the fact that the

amount of data in the Rx FIFO is below the threshold. The RVAL pin remains
asserted, indicating that valid data still exists and is being transferred. When the
RVAL is deasserted, the FIFO is empty. The link layer should then deassert the
RENB pin.

In the lower part of

Figure 5-11

, another read process starts (DRPA[1] is

asserted due the existence of [EOP] in the FIFO). In this case, the FIFO continues
to be filled the data of the next packet after the EOP of the current packet enters
the FIFO.

When reading the FIFO at the EOP, the RVAL pin is deasserted. When this

occurs, no data is transferred from the port. At that point, the link layer may
deselect and reselect the same port, and reinitiate the transfer of a new packet.

Figure 5-11. RVAL and RPA Functionality in Hot Selection Mode

101344_027

FIFO below
threshold,
no EOP

FIFO empty

FIFO contains
an EOP

EOP, FIFO still

above or contains

another EOP

RFCLK

RVAL

DRPA[1]

RENB

RADR[4:0]

RDAT[15:0]

RPRTY

RMOD

RSOP

REOP

RERR

W15

W16 W17 W18 W19 W20

W21

CX2970x

5.0 Functional Timing

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

5.1 ATM Layer Interface

29704-DSH-001-B

Mindspeed Technologies

5-11

5.1.8 Transmit

The previous timing diagrams refer to the receive side of the POS interface;
however, the same timing diagram (with the exception of the RVAL signal) is
valid for the transmit side. The assertion and deassertion of the available free
bytes in the FIFO act in the same manner as the available bytes to be read in the
receive side.

The TPA assertion indicates that the FIFO is ready to have data written to it.

When the number of bytes in the FIFO exceeds the predefined number (by the
register Tx FHL in 32-bit granularity), the TPA pin is deasserted. Then the TENB
pin should be asserted. During the transfer of the first word of the packet, the
TSOP must be asserted. The TEOP must be asserted during the writing to the
FIFO of the last word of a packet. When an SOP is encountered without the
assertion of EOP at the previous transfer, the new packet is handled and the
previous one is marked with an error and aborted.

Figure 5-12. Tx Single Port, Functional Timing

. . .

101344_028

. . .

PKT 1

B1
B2

PKT 1

B1
B2

PKT 1

B3
B4

PKT 1

B5
B6

PKT 1

B7
B8

PKT 1

B37
B38

PKT 1

B39
B40

PKT 1

B41
B42

PKT 1

B43
B44

PKT 1

B45

TFCLK

TSOP

TEOP

TMOD

TERR

TPA

TENB

TDAT[15:0]

TPRTY

CX2970x

6.0 Electrical and Mechanical Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

6.1 AC Characteristics

29704-DSH-001-B

Mindspeed Technologies

6-3

Table 6-1. Microprocessor Write/Read Cycle AC Parameters

Subject

Symbol

Parameter

Min.

Max.

Units

WRITE
CYCLE

Address bus setup time before *DSTB active

W/*R changes to 1 before *DSTB active

*READY valid after *DSTB active

Address bus hold time after *DSTB inactive

W/*R changes to 0 before *DSTB inactive

Data bus hold time after *DSTB inactive

*READY high-Z to after DSTB inactive

*DSTB minimum negative pulse width

350

Data bus valid after *DSTB active

t10

*DSTB recovery time

350

t11

*CS changes to 0 before *DSTB active

t12

*CS changes to 1 after *DSTB inactive

t13

*READY active after *DSTB active

310

READ

CYCLE

t14

Address bus setup time before *DSTB active

t15

W/*R changes to 0 before *DSTB active

t16

*DSTRB minimum negative pulse width

350

t17

*READY valid after *DSTB active

t18

Data bus delay from Hi-Z until invalid data out

t19

Valid data out delay from *READY active

t20

Address bus hold time after *DSTB inactive

t21

W/*R changes to 1 before *DSTB inactive

t22

*DSTB recovery time

350

t23

Data bus hold time after *DSTB inactive

t24

*READY high-Z after DSTB inactive

t25

*CS changes to 0 before *DSTB active

t26

*CS changes to 1 after *DSTB inactive

t27

*READY active after *DSTRB active

310

CX2970x

6.0 Electrical and Mechanical Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

6.1 AC Characteristics

29704-DSH-001-B

Mindspeed Technologies

6-5

6.1.3 POS Interface

6.1.3.1 Rx AC Timing

Figure 6-5

illustrates the AC timing of the Receive POS interface and its

characteristics.

Table 6-2. UTOPIA Transmit/Receive AC Parameters

Subject

Symbol

Parameter

Min.

Max.

Units

Transmit Direction

TxClk

Frequency

MHz

Duty cycle

TxClk rise/fall time

Peak-to-peak jitter

Input setup to TxClk

Input hold from TxClk

Signal going high impedance from TxClk

Signal going low impedance to TxClk

Signal going low impedance from TxClk

Signal going high impedance to TxClk

Output setup to TxClk

Output hold from TxClk

Receive Direction

RxClk

Frequency

MHz

Duty cycle

RxClk rise/fall time

Peak-to-peak jitter

Input setup to RxClk

Input hold from RxClk

Signal going high impedance from RxClk

Signal going low impedance to RxClk

Signal going low impedance from RxClk

Signal going high impedance to RxClk

Output setup to RxClk

Output hold from RxClk

CX2970x

6.0 Electrical and Mechanical Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

6.1 AC Characteristics

29704-DSH-001-B

Mindspeed Technologies

6-7

6.1.3.2 Tx AC Timing

Figure 6-6

illustrates the AC timing and characteristics of the Transmit POS

interface.

RxData

RxClk High to RxData Valid

RxData

RxClk High to RxData High-Z

tZB

RxData

RxClk High to RxData Driven

RxPrty

RxClk High to RxPrty Valid

RxPrty

RxClk High to RxPrty High-Z

tZB

RxPrty

RxClk High to RxPrty Driven

RxSOP

RxClk High to RxSOP Valid

RxSOP

RxClk High to RxSOP High-Z

tZB

RxSOP

RxClk High to RxSOP Driven

RxEOP

RxClk High to RxEOP Valid

RxEOP

RxClk High to RxEOP High-Z

tZB

RxEOP

RxClk High to RxEOP Driven

RxMOD

RxClk High to RxMOD Valid

RxMOD

RxClk High to RxMOD High-Z

tZB

RxMOD

RxClk High to RxMOD Driven

RxERR

RxClk High to RxERR Valid

RxERR

RxClk High to RxERR High-Z

tZB

RxERR

RxClk High to RxERR Driven

RVAL

RxClk High to RVAL Valid

RVAL

RxClk High to RVAL High-Z

tZB

RVAL

RxClk High to RVAL Driven

PRPA

RxClk High to PRPA Valid

PRPA

RxClk High to PRPA High-Z

tzb

PRPA

RxClk High to PRPA Driven

DRPA

RxClk High to DRPA[3:0] Valid

Table 6-3. POS Interface Receive AC Parameters (2 of 2)

Symbol

Description

Min

Max

Units

CX2970x

6.0 Electrical and Mechanical Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

6.1 AC Characteristics

29704-DSH-001-B

Mindspeed Technologies

6-9

Table 6-4. POS Interface Transmit AC Parameters

Symbol

Description

Min

Max

Units

TxClk Frequency

MHz

TxClk Duty Cycle

TxEnb

TxEnb Set-up time to TxClk

TxEnb

TxEnb Hold Time to TxClk

TxData

TxData[15:0] Set-up Time to TxClk

TxData

TxData[15:0] Hold Time to TxClk

TxPrty

TxPrty Set-up Time to TxClk

TxPrty

TxPrty Hold Time to TxClk

TxSOP

TxSOP Set-up Time to TxClk

TxSOP

TxSOP Hold Time to TxClk

TxEOP

TxEOP Set-up Time to TxClk

TxEOP

TxEOP Hold Time to TxClk

TxMOD

TxMOD Set-up Time to TxClk

TxMOD

TxMOD Hold Time to TxClk

TxERR

TxERR Set-up Time to TxClk

TxERR

TxERR Hold Time to TxClk

TxAdd

TxAdd[4:0] Set-up Time to TxClk

TxAdd

TxAdd[4:0] Hold Time to TxClk

0.5

STPA

TxClk High to STPA Valid

STPA

TxClk High to STPA High-Z

tZB

STPA

TxClk High to STPA Driven

PTPA

TxClk High to PTPA High-Z

tZP

PTPA

TxClk High to PTPA Driven

DTPA

TxClk High to DTPA[3:0] Valid

6.0 Electrical and Mechanical Specifications

CX2970x

6.1 AC Characteristics

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

6-12

Mindspeed Technologies

29704-DSH-001-B

6.1.7 Line Interface

The transmit and receive line interfaces are industry standard low voltage PECL
(LPECL) interfaces. See

Figure D-2

and

D-3

for examples of properly interfacing

fiber optics transceivers to the CX29704's PECL interface.

6.1.7.1 Transmit Line

Interface

The PECL Transmit Line Interface is designed as open-drain differential-pair
current switches that steer/sink current through the external loads.

Table 6-10. Transmit Line Interface Parameters

Description

Value

Note

Type

PECL Transmitter

Data Rate

155 Mb/s

Max (worst case p-p) differential amplitude

2,000 mV

Min (opening) differential amplitude

1,100 mV

Max (off) differential amplitude

170 mV

Maximum Rise/Fall time (2080%)

327 ps

Minimum Rise/Fall time (2080%)

85 ps

Differential skew (max)

25 ps

Deterministic jitter

10% UI

Random jitter

12% UI

Output current--Ioh (typ)

TBD mA

Output current--Iol (typ)

TBD mA

Output current--Ioz (leakage)

TBD mA

NOTE(S):

1. An example of an Off Transmitter is no power supplied to the PMD and PMA transmit output being driven to a static state

during loopback.

2. At Vtt = Vdd 2 V for 50

pad.

3. Cl ~ 2 pf.
4. Differential p-p amplitude represents a 2x voltage swing measured at each output pad (Tx + Tx).

CX2970x

6.0 Electrical and Mechanical Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

6.2 Absolute Maximum Ratings

29704-DSH-001-B

Mindspeed Technologies

6-13

6.1.7.2 Receive Line

Interface

The PECL receiver is designed as a self-biased, wide-swing, high-gain amplifier.
The input stage can withstand a wide common mode range at its inputs while
maintaining high gain and wide bandwidth.

6.2 Absolute Maximum Ratings

The absolute maximum ratings listed below are the maximum stresses that the
device can tolerate without risking permanent damage.These ratings are not
typical of normal device operation. Exposure to absolute maximum rating
conditions for extended time periods may affect the device's reliability. This
device should be handled as an ESD-sensitive device. Voltage on any signal pin
that exceeds the power supply voltage by more than +0.5 V can induce destructive
latchup.

Table 6-11. Receive Line Interface Parameters

Description

Value

Type

PECL Receiver

Data rate

155 Mb/s

Minimum differential sensitivity (p-p)

(1)

200 mV

Maximum differential sensitivity (p-p)

(2)

2,000 mV

Input impedance

1 M

NOTE(S):

(1)

D21.5 idle pattern

(2)

AC coupling input

Table 6-12. Absolute Maximum Ratings

Parameter

Value

Supply Voltage

3.3

5% V

Operating Temperature--No Air Flow

40 °C/W

Operating Temperature--200 Linear Feet (1 Meter) per Minute

33 °C/W

Storage Temperature

40 to 125 °C

11 °C/W

Ambient Temperature under Bias

40 to 85 °C

Junction Temperature

150 °C

Static Discharge Voltage

1,500 V

Latchup Current

150 mA

Appendix A CX29704

CX2970x

A.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A-2

Mindspeed Technologies

29704-DSH-001-B

TxData[15:0]
(POS mode)

R3
P4

R2
R1
P2
P1
N3
N1

M4
M3
M2

L4
L3
L2
L1

POS Interface Transmit Data. Packet/data is transmitted from the link layer to
the PHY layer. Data is sampled on the rising edge of TxClk and is valid only
when *TxEnb is asserted.

TxAdd[4:0]
(ATM mode)

H3
H2

J4
J3
J2

UTOPIA Transmit Address. The address is driven from the ATM layer to the
PHY layer and selects the port that receives the next cell(s). When using the
modes One Rx/Tx CLAV or Multiplexed Status Polling, it is also used to poll the
status of the transmit FIFOs.

Address is sampled on the rising edge of TxClk.

TxAdd[4:0]
(POS mode)

H3
H2

J4
J3
J2

POS Interface Transmit Address. The address is driven from the link layer to
the PHY layer and selects the port that receives the next data packet. It is also
used to poll the status of the transmit FIFOs through the PTPA pin.

Address is sampled on the rising edge of TxClk.

TxSOC
(ATM mode)

UTOPIA Transmit Start Of Cell (SOC). TxSOC is asserted when TxData contains
the first word of a cell. An interrupt is generated when TxSOC is asserted when
already receiving a cell from the UTOPIA interface.

TxSOC is sampled on the rising edge of TxClk.

TxSOP
(POS mode)

POS Interface Transmit Start Of Packet (SOP). TxSOP is asserted when TxData
contains the first word of a packet. TxSOP is sampled on the rising edge of
TxClk.

*TxEnb
(ATM mode)

UTOPIA Transmit Data Enable (active-low). *TxEnb indicates that TxData[15:0]
contains valid cell data. *TxEnb is sampled on the rising edge of TxClk.

*TxEnb
(POS mode)

POS Interface Transmit Data Enable (active-low). *TxEnb indicates that
TxData[15:0] contains valid packet data. *TxEnb is sampled on the rising edge
of TxClk.

TxClav[3:0]
(ATM mode)

F3
E1
E2

High-Z

UTOPIA Transmit Cell Available. Supports Cell-Level Handshake. Indicates that
the transmit FIFO can accept a complete cell. The mode One (polling mode)
Rx/Tx CLAV requires only TxClav[0]. TxClav[3:0] are updated on the rising
edge of TxClk. These pins require 470 ohm pull down resistors.

DTPA [3:0]
(POS mode)

F3
E1
E2

High-Z

POS Interface Direct Transmit Packet Available (DTPA). Transition HIGH
indicates that a (predefined) minimum number of bytes is available in the
corresponding FIFO. Once HIGH, the DTPA pin indicates that the FIFO is not
full. Transition LOW indicates that the FIFO is full or almost full (programmable
by the user). DTPA[3:0] is updated on the rising edge of TxClk. These pins
require 470 ohm pull down resistors.

Table A-1. UTOPIA/POS Level 2 Interface (2 of 5)

Name

No.

I/O

Type

Functional Description

CX2970x

Appendix A CX29704

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

A-3

PTPA
(POS mode)

High-Z

Polled Transmit Packet Available (PTPA). The PTPA[0] and DTPA[0] are
physically the same pin with different functionality according to the selected
mode. When operating in single TPA pin mode, DTPA pin[0] acts as PTPA.
Transition HIGH indicates that a predefined number of bytes (in the Tx-FLL) is
valid in the polled Tx FIFO. Transition LOW indicates that the FIFO is full or
nearly full (as programmed in the Tx-FHL Register). PTPA is driven by the PHY
when its address is polled on the address pins. Otherwise, it must be
high-Zed.This pin requires a 470 ohm pull down resistor.

TxPrty
(ATM mode)

UTOPIA Transmit Parity. TxPrty indicates odd parity of TxData[15:0]. Interrupt
is optionally generated when a mismatch is found. The use of this pin is
optional since cells with parity errors are transmitted. TxPrty is sampled on the
rising edge of TxClk.

TxPrty
(POS mode)

POS Interface Transmit Parity. TxPrty indicates parity of TxData[15:0]. TxPrty
is sampled on the rising edge of TxClk.

TxClk
(ATM mode)

UTOPIA Transmit Clock. Driven by the ATM layer. TxData[15:0], TxAdd[4:0],
TxSOC, *TxEnb and TxPrty signals are sampled on the rising edge of this
clock. TxClav[3:0] is updated on the rising edge of this clock.

TxClk
(POS mode)

POS Interface Transmit Clock. Driven by the link layer. TxData[15:0],
TxAdd[4:0], TxSOP, *TxEnb and TxPrty, TxEOP, TxMOD, TxERR signals are
sampled on the rising edge of this clock. DTPA[3:0] is updated on the rising
edge of this clock.

RxData[15:0]
(ATM mode)

A5
B6
A6
B7
A7
B8
A8
D9
C9
A9

D10
C10
C11
B11
A13
C13

High-Z

UTOPIA Receive Data. Cell data is transferred from the PHY layer to the ATM
layer. Data is updated on the rising edge of RxClk and is valid only when
*RxEnb is sampled while asserted. These pins require 10 k ohm pull up
resistors.

Table A-1. UTOPIA/POS Level 2 Interface (3 of 5)

Name

No.

I/O

Type

Functional Description

Appendix A CX29704

CX2970x

A.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A-4

Mindspeed Technologies

29704-DSH-001-B

RxData[15:0]
(POS mode)

A5
B6
A6
B7
A7
B8
A8
D9
C9
A9

D10
C10
C11
B11
A13
C13

High-Z

POS Interface Receive Data. Packet data is transferred from the PHY layer to
the link layer. Data is updated on the rising edge of RxClk and is valid only
when *RxEnb is sampled while asserted. These pins require 10 k ohm pull up
resistors.

RxAdd[4:0]
(ATM mode)

B3
C4
B5
C6
D7

UTOPIA Receive Address. The ATM layer drives the address to the PHY layer
and selects the port from which the next cell(s) is taken. When using modes
One Rx/Tx CLAV or Multiplexed Status Polling, it is also used to poll the status
of the receive FIFOs.

Address is sampled on the rising edge of RxClk.

RxAdd[4:0]
(POS mode)

B3
C4
B5
C6
D7

POS Interface Receive Address. The link address layer drives the PHY layer
and selects the port from which the next packet-data is taken. It is also used to
poll the status of the receive FIFOs using the PRPA pin.

Address is sampled on the rising edge of RxClk.

RxSOC
(ATM mode)

A16

High-Z

UTOPIA Receive Start Of Cell. RxSOC is asserted when RxData[15:0] contains
the first word of the cell. RxSOC is updated on the rising edge of RxClk. This
pin requires a 1k ohm pull down resistor.

RxSOP
(POS mode)

A16

High-Z

POS Interface Receive Start Of Packet. RxSOP is asserted when RDAT[15:0]
contains the first word of the packet. RxSOP is updated on the rising edge of
RxClk. This pin requires a 1k ohm pull down resistor.

*RxEnb
(ATM mode)

C17

UTOPIA Receive Data Enable (active-low). When asserted, it indicates that the
PHY port has permission to transfer valid cell data, if available. *RxEnb is
sampled on the rising edge of RxClk.

*RxEnb
(POS mode)

C17

POS Interface Receive Data Enable (active-low). When asserted, it indicates
that the PHY port has permission to transfer valid packet data, if available.

*RxEnb is sampled on the rising edge of RxClk.

RxClav[3:0]
(ATM mode)

A14
B14
C14
D14

High-Z

UTOPIA Receive Cell Available. Support Cell Level Handshake indicates that
the receive FIFO has a complete cell available.

The mode One (polling mode) Rx/Tx CLAV requires only RxClav[0].

RxClav[3:0] are sampled on the rising edge of RxClk.

These pins require 470 ohm pull down resistors.

DRPA[3:0]
(POS mode)

A14
B14
C14
D14

High-Z

POS Interface Receive Packet Available. Indicates that the receive FIFO has at
least one End-Of-Packet available or a predefined number of bytes.
DRPA[3:0] are sampled on the rising edge of RxClk. These pins require 470
ohm pull down resistors.

Table A-1. UTOPIA/POS Level 2 Interface (4 of 5)

Name

No.

I/O

Type

Functional Description

CX2970x

Appendix A CX29704

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

A-5

PRPA
(POS mode)

A14

High-Z

Received Polled Packet Available. Indicates that data is valid in the polled Rx
FIFO. Logic 1 indicates at least one End-Of-Packet or a predefined number of
bytes is available in the FIFO. Logic 0 indicates there is no End-Of-Packet in the
FIFO and the number of valid bytes is below the predefined threshold. The PHY
drives the PRPA when its address is selected on the address pins. Otherwise,
it must be high-Zed. This pin is physically the same pin as DTPA[0], which
functions according to the POS Interface configuration. This pin requires a 470
ohm pull down resistor.

RxPrty
(ATM mode)

B15

High-Z

UTOPIA Receive Parity. RxPrty indicates odd parity of RxData[15:0]. RxPrty is
updated on the rising edge of TxClk. This pin requires a 1k ohm pull down
resistor.

RxPrty
(POS mode)

B15

High-Z

POS Interface Receive Parity. RxPrty indicates parity of RxData[15:0]. RxPrty
is updated on the rising edge of RxClk. This pin requires a 1k ohm pull down
resistor.

RxClk
(ATM mode)

C12

UTOPIA Receive Clock. Driven by the ATM layer. RxData[15:0], RxSOC,
RxClav, and RxPrty signals are updated on the rising edge of this clock.
RxAdd[4:0] and *RxEnb are sampled on the rising edge of this clock.

RxClk
(POS mode)

C12

POS Interface Receive Clock. Driven by the link layer. RxData[15:0], RxSOP,
DRPA, RxPrty, RxSOP, RxEOP, RxMOD, and RxERR signals are updated on the
rising edge of this clock. RxAdd[4:0] and *RxEnb are sampled on the rising
edge of this clock.

NOTE(S):

I = Input, O = Output, E = PECL, T = TTL

Table A-1. UTOPIA/POS Level 2 Interface (5 of 5)

Name

No.

I/O

Type

Functional Description

Appendix A CX29704

CX2970x

A.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A-6

Mindspeed Technologies

29704-DSH-001-B

A.2.2 POS Level 2 Interface Specific

Table A-2. POS Level 2 Interface Specific

Name

No.

I/O

Type

Functional Description

STPA

High-Z

Tx Selected Packet Available. Transition HIGH indicates that the number of
words are less than the value predefined by the Tx-FLL in the selected FIFO
(the FIFO to which data is currently being sent). Transition LOW indicates that
the number of words (32-bit) are more than the value predefined in the Tx-FHL
in the selected FIFO. The PHY drives the STPA when its address is selected on
the address pins. Otherwise, it must be high-Zed. This pin requires a 1k ohm
pull down resistor.

TxMOD
(POS mode)

Transmit Word Modulo. Indicates the length of the current word being
transmitted. TxMOD should always be LOW, except during the last word
transfer of a packet (TxEOP). Logic 1 indicates that only the eight MSBs of the
last word are valid. Logic 0 indicates that all 16 bits of the last word of a packet
are valid.

TxEOP
(POS mode)

Transmit End-Of-Packet. Marks the end of a packet on the data bus. When
TxEOP is HIGH, it indicates that the last word of a packet is present on the data
bus (TDAT). Assertion of both TxEOP and TxSOP is legal, and is used to
indicate one- or two-byte-long packets.

TxERR
(POS mode)

Transmit Error. Indicates the current packet is aborted and should be
discarded. TxERR should be asserted only during the last word of a packet.

RVAL
(POS mode)

C16

High-Z

Receive Signal Validity. The RVAL indicates the validity of the receive data.
When the RVAL is HIGH, receive data pins are valid. Otherwise, the receive
signals must be discarded. RVAL transitions LOW on a FIFO empty condition
or on End-Of-Packet. No transaction with the receive FIFO can be performed
while the RVAL is deasserted. RVAL allows monitoring of the selected FIFO
during a data transfer. The monitoring of other FIFOs is done with the DRPA
pins. After deassertion, the RVAL is reasserted after the current FIFO is
deselected. RVAL is driven by the PHY when its address is selected on the
address pins. Otherwise, it must be high-Zed. This pin requires a 1k ohm pull
down resistor.

RxMOD
(POS mode)

D16

High-Z

Receive Word Modulo. Indicates the length of the current word being received.
RxMOD should always be LOW, except during the last word transfer of a
packet (RxEOP). Logic 1 indicates that only the eight MSBs of the last word
are valid. Logic 0 indicates that all 16 bits of the last word of a packet are valid.
This pin requires a 1k ohm pull down resistor.

RxEOP
(POS mode)

B16

High-Z

Receive End-Of-Packet. Marks the end of a packet on the data bus. When
RxEOP is HIGH, it indicates that the last word of a packet is present on the data
bus (TDAT). Assertion of both RxEOP and RxSOP is legal and is used to
indicate one- or two-byte-long packets. This pin requires a 1k ohm pull down
resistor.

RxERR
(POS mode)

A18

High-Z

Receive Error. Indicates the current packet is aborted and should be discarded.
RxERR should be asserted only during the transfer of the last word of a
packet. This pin requires a 1k ohm pull down resistor.

NOTE(S):

I = Input, O = Output, E = PECL, T = TTL

CX2970x

Appendix A CX29704

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

A-7

A.2.3 Line Interface Pins

Table A-3. Line Interface Pins

Name

No.

I/O

Type

Functional Description

RxD0+
RxD0
RxD1+
RxD1
RxD2+
RxD2
RxD3+
RxD3

V3
Y1

Y14
Y15

W18

V18

Line Receive Data.
Ports 03 differential data inputs. These inputs contain NRZ encoded data.
Ports 03 receive clocks are recovered from these inputs.

TxD0+
TxD0
TxD1+
TxD1
TxD2+
TxD2
TxD3+
TxD3

V9
Y9

Y17

W17

T17

U20

Line Transmit Data.
Port 03 differential data outputs. These outputs contain NRZ encoded data.

SD0,
SD1,
SD2,
SD3

T20

R18

Signal Detect. Single-ended PECL input. This signal indicates the presence of a
valid signal from the optical transceiver per port. Active-High. A Low signal
indicates a loss of signal.

RefCLK

W12

19.44 MHz Reference Clock Input. This clock should have an accuracy
of ± 20 ppm.

PCAP0,
PCAP1,
PCAP2,
PCAP3,

Y2
Y7

W15

Y20

External PLL capacitor. These pins are provided to connect the external
capacitor to the internal PLLs. See

Figure 2-3

NCAP0,
NCAP1,
NCAP2,
NCAP3,

Y16

W20

External PLL capacitor. These pins are provided to connect the external
capacitor to the internal PLLs. See

Figure 2-3

REXT0, REXT1

Y10
Y11

External PLL resistor. These pins are provided to connect an external resistor
to the internal PLL. See

Figure 2-3

PHYBPSS

Analog test mode. Reserved for manufacturer's testing. Should be connected
to GND.

RECCLK0,
RECCLK1,
RECCLK2,
RECCLK3

V1
T4

T18
T19

Recovered clock divided by 8. This is a 19.44 MHz clock optionally active for
each port or optionally an 8 kHz clock synchronized with each frame received.

Appendix A CX29704

CX2970x

A.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A-8

Mindspeed Technologies

29704-DSH-001-B

A.2.4 Data Communication Channel Interface Pins

Table A-4. Data Communication Channel Interface Pins

Name

No.

I/O

Type

Functional Description

RSDCD14

C15

J20

The received section-DCC bytes (D1D3) are serialized out using these pins,
clocked by RSDCC14. A dedicated pin is available for each port. Per-port
disabling of this pin is optional.

RSDCC14

P3
A4

A15
H19

The received section DCC (D1D3) clock. This is a 216 kHz clock (50% duty
cycle), which is active for part of the frame time, and produces a nominal rate
of 192 kHz to update the RSDCD14 pins. A dedicated pin is available for each
port. Per-port disabling of this pin is optional.

RLDCD14

D12
D20

The received line-DCC bytes (D4D12) are serialized out using these pins,
clocked by RLDCC14. A dedicated pin is available for each port. Per port
disabling of this pin is optional.

RLDCC14

N2
D1

A17

F19

The received line DCC (D4D12) clock. This is a 648 kHz clock (50% duty
cycle), which is active for part of the frame time and produces a nominal rate
of 576 kHz to update the RLDCD14 pins. A dedicated pin is available for each
port. Per port disabling of this pin is optional.

TSDCD14

D18
P17

The transmit section-DCC bytes (D1D3) are serialized using these pins,
clocked by TSDCC14. A dedicated pin is available for each port. Per-port
disabling of this pin is optional.

TSDCC14

B10
C18
N18

The transmit section DCC (D1D3) clock. This is a 216 kHz clock (50% duty
cycle), which is active for part of the frame time, and produces a nominal rate
of 192 kHz to sample the TSDCD14 pins. A dedicated pin is available for each
port. Per-port disabling of this pin is optional.

TLDCD14

K1
C8

B13
K20

The transmit line-DCC bytes (D4D12) are serialized using these pins, clocked
by TLDCC14. A dedicated pin is for each port. Per-port disabling of this pin is
optional.

TLDCC14

B17

M19

The transmitted line DCC (D4D12) clock. This is a 648 kHz clock (50% duty
cycle) that is active for part of the frame time and produces a nominal rate of
576 kHz to sample the TLDCD14 pins. A dedicated pin is available for each
port. Per-port disabling of this pin is optional.

CX2970x

Appendix A CX29704

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

A-9

A.2.5 Microprocessor Interface Pins

Table A-5. Microprocessor Interface Pins

Name

No.

I/O

Type

Functional Description

D[15:0]

G20
H18
H20

J17
J18
J19

K17
K18
K19
L20
L18
L19

M20
M18
M17

N20

I/O

Microprocessor interface data bus

A[8:0]

C19
E17
C20

D19

E18
E19
F18

G17

E20

Microprocessor interface address bus

*CS

G18

Chip Select (active-low)

W/*R

G19

Write/Read control signal (High = Write, Low = Read).

*DSTRB

F20

Data strobe (active-low).

*READY

B20

High-Z

Ready (active-low)

In Read cycle, when asserted, indicates to the microprocessor that the data on
D[15:0] is valid and ready to be read. In Write cycle, when asserted, signals the
µP that the Write cycle was completed. This pin requires a 1k ohm pull up
resistor.

*INTR

A19

Open
Drain

Interrupt signal (active-low, open drain).
When asserted, interrupt is active; Hi-Z when not asserted. This pin requires a
1k ohm pull up resistor.

The Interrupt request is deasserted three cycles after all the Interrupt registers
are read.

Appendix A CX29704

CX2970x

A.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A-10

Mindspeed Technologies

29704-DSH-001-B

A.2.6 Alarms Status Serial Interface Pins

A.2.7 JTAG Interface Pins

A.2.8 Scan Interface Pins

Table A-6. Alarms Status Serial Interface Pins

Name

No.

I/O

Type

Functional Description

ASDO

N19

Alarms Status Data Out

*ASSTB

P20

Alarms Status Strobe (active-low)

ASCLK

P19

Alarms Status Clock

ASENB

P18

Alarms Status Enable
When tied to VSS, ASDO and *ASCLK are disabled.

Table A-7. JTAG Interface Pins

Name

No.

I/O

Type

Functional Description

TDO

High-Z

Test data output (when in JTAG mode). Leave unconnected when JTAG is not
used.

TDI

Test data input (when in JTAG mode). Tie to VDD when JTAG is not used (TMS
is Low).

TCK

Test Clock pin (when in JTAG mode). Tie to VDD when JTAG is not used.

TMS

Test Mode Select pin. High = JTAG mode, Low = Normal mode.

*TRST

Test Reset pin (when in JTAG mode). Tie to VSS when JTAG is not used
(active-Low).

Table A-8. Scan Interface Pins

Name

No.

I/O

Type

Functional Description

B12

Test Mode. Engineering only. Enables scan mode testing. Active-high (Should
be tied to VSS).

SCANEN

A12

Scan Enable. Engineering only. Enables scan shift in/out of the device.
Active-high (Should be tied to VSS).

Appendix A CX29704

CX2970x

A.4 Package Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

A-14

Mindspeed Technologies

29704-DSH-001-B

A.4 Package Specifications

The CX29704 is packed in a 272-PBGA package with a body size of 27

× 27 mm

and a ball pitch of 1.27 mm.

Figure A-1. CX29704 Package Layout (Bottom View)

V SS

T X M OD

RLDCC

[ 1]

T X CLA

V [ 2]

T X SOC

T SDCC

[ 0]

T LDCC

[ 0]

V DD

T LDCD

[ 0]

T X DA T

A [ 15]

RLDCD

[ 0]

T X DA T

A [ 8]

T X DA T

A [ 6]

T X DA T

A [ 4]

T X DA T

A [ 2]

B P SSG

RE CCL

K 0

V SSA

RX D0-

T DI

RLDCD

[ 1]

V DD

V SS

T X CLA

V [ 3]

T SDCD

[ 0]

T X E NB

T X A DD

[ 1]

T X A DD

[ 4]

T X CLK

T X DA T

A [ 14]

T X DA T

A [ 11]

RLDCC

[ 0]

T X DA T

A [ 5]

T X DA T

A [ 3]

RSDCD

[ 0]

SD1

V SSD

V DDA

P CA P 0+

T RST

RX A DD

[ 0]

T DO

RX E RR

ST P A

T X CLA

V [ 1]

T X P RT

T X A DD

[ 0]

T X A DD

[ 3]

V SS

T X DA T

A [ 13]

T X DA T

A [ 10]

T X DA T

A [ 7]

RSDCC

[ 0]

T X DA T

A [ 0]

SD0

V SSD

RX D0+

V SSA

V DDD

RSDCC

[ 1]

T CK

RX A DD

[ 1]

V SS

T X E OP

V DD

T X CLA

V [ 0]

V SS

T X A DD

[ 2]

V DD

T X DA T

A [ 12]

T X DA T

A [ 9]

V SS

T X DA T

A [ 1]

V DD

RE CCL

K 1

V SS

V DDA

P CA P 0-

T X D0+

RX DA T

A [ 0]

RX A DD

[ 2]

T M S

RSDCD

[ 1]

V DDD

V SSA

T X D0-

V SSD

RX DA T

A [ 2]

RX DA T

A [ 1]

RX A DD

[ 3]

V DD

V SSD

RX D1+

V DDA

RX DA T

A [ 4]

RX DA T

A [ 3]

T SDCD

[ 1]

RX A DD

[ 4]

V SSA

RX D1-

V SSA

P CA P 1+

RX DA T

A [ 6]

RX DA T

A [ 5]

T LDCD

[ 1]

V SS

P CA P 1-

V DDA

V DDD

RX DA T

A [ 9]

T LDCC

[ 1]

RX DA T

A [ 8]

RX DA T

A [ 7]

V SS

V DDD

T X D1+

V SSA

T X D1-

V SS

T SDCC

[ 1]

RX DA T

A [ 11]

RX DA T

A [ 10]

V SS

V DD

V DDA

RE X T 1

V DD

RX DA T

A [ 11]

RX DA T

A [ 12]

V DD

V SS

V SSD

V SSA

RE X T 2

SCA NE

T M

RX CLK

RLDCD

[ 2]

V SS

V DDA

RE FCLK

V SSA

RX DA T

A [ 14]

T LDCD

[ 2]

RX DA T

A [ 15]

V SS

V SSA

V SSD

RX CLA

V [ 0]

RX CLA

V [ 1

RX CLA

V [ 2

RX CLA

V [ 3

V DDA

V SSA

V DDA

RX D2+

RSDCC

[ 2]

RX P RT

RSDCD

[ 2]

V DD

V DDD

P CA P 2+ RX D2-

RX SOC

RX E OP

RV A L

RX M OD

V SSD

V SSA

V DDD

P CA P 2-

RLDCC

[ 2]

T LDCC

[ 2]

RX E NB

V SS

UP A DD

R[ 1]

V DD

UP A DD

R[ 7]

V SS

UP DA T

A [ 3]

UP DA T

A [ 6]

V DD

UP DA T

A [ 14]

V SS

T SDCD

[ 3]

V DD

T X D3+

V SS

V SSA

T X D2-

T X D2+

RX E RR RE SE T

T SDCC

[ 2]

T SDCD

[ 2]

UP A DD

R[ 4]

UP A DD

R[ 6]

UP DA T

A [ 1]

UP DA T

A [ 4]

UP DA T

A [ 7]

UP DA T

A [ 10]

UP DA T

A [ 13]

T SDCC

[ 3]

A SE NB

SD3

RE CCL

K 2

V DDD

RX D3-

RX D3+

V SSD

I NT R

V DD

UP A DD

R[ 0]

UP A DD

R[ 3]

UP A DD

R[ 5]

RLDCC

[ 3]

WRNRD

RSDCC

[ 3]

UP DA T

A [ 5]

UP DA T

A [ 8]

UP DA T

A [ 11]

T LDCC

[ 3]

A SDO

A SCLK

V DD

RE CCL

K 3

V DDD

V DDA

V SSA

V DDA

Appendix B CX29702

CX2970x

B.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B-2

Mindspeed Technologies

29704-DSH-001-B

B.2 Pin Description

B.2.1 UTOPIA/POS Level 2 Interface

Table B-1. UTOPIA/POS Level 2 Interface

Name

Number

I/O

Type

Functional Description

TxClav[1:0]
(ATM mode)

High-Z

UTOPIA Transmit Cell Available. Supports Cell-Level
Handshake. Indicates that the transmit FIFO can accept a
complete cell. The mode One (polling mode) Rx/Tx CLAV
requires only TxClav[0]. TxClav[1:0] are updated on the rising
edge of TxClk. These pins require 470 ohm pull down
resistors.

DTPA [1:0]
(POS mode)

High-Z

POS Interface Direct Transmit Packet Available (DTPA).
Transition HIGH indicates that a (predefined) minimum
number of bytes is available in the corresponding FIFO. Once
HIGH, the DTPA pin indicates that the FIFO is not full.
Transition LOW indicates that the FIFO is full or almost full
(programmable by the user). DTPA[1:0] is updated on the
rising edge of TxClk. These pins require 470 ohm pull down
resistors.

RxClav[1:0]
(ATM mode)

A14
B14

High-Z

UTOPIA Receive Cell Available. Support Cell Level Handshake
indicates that the receive FIFO has a complete cell available.
The mode One (polling mode) Rx/Tx CLAV requires only
RxClav[0]. RxClav[1:0] are sampled on the rising edge of
RxClk. These pins require 470 ohm pull down resistors.

DRPA[1:0]
(POS mode)

A14
B14

High-Z

POS Interface Receive Packet Available. Indicates that the
receive FIFO has at least one End-Of-Packet available or a
predefined number of bytes. DRPA[1:0] are sampled on the
rising edge of RxClk. These pins require 470 ohm pull down
resistors.

CX2970x

Appendix B CX29702

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

B-3

B.2.2 POS Level 2 Interface Specific

Table B-2. POS Level 2 Interface Specific

Name

No.

I/O

Type

Functional Description

STPA

High-Z

TxMOD
(POS mode)

TxEOP
(POS mode)

TxERR
(POS mode)

Transmit Error. Indicates the current packet is aborted and should be
discarded. TxERR should be asserted only during the last word of a packet.

RVAL
(POS mode)

C16

High-Z

RxMOD
(POS mode)

D16

High-Z

RxEOP
(POS mode)

B16

High-Z

RxERR
(POS mode)

A18

High-Z

NOTE(S):

I = Input, O = Output, E = PECL, T = TTL

Appendix B CX29702

CX2970x

B.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B-4

Mindspeed Technologies

29704-DSH-001-B

B.2.3 Line Interface Pins

Table B-3. Line Interface Pins

Name

Number

I/O

Type

Functional Description

RxD0+
RxD0
RxD1+
RxD1

V3
Y1

Line Receive Data.

Ports 01 differential data inputs. These inputs contain NRZ

encoded data.
Ports 01 receive clocks are recovered from these inputs.

TxD0+
TxD0
TxD1+
TxD1

V9
Y9

Line Transmit Data.
Port 01 differential data outputs. These outputs contain NRZ
encoded data.

SD0,
SD1

Signal Detect. Single-ended PECL input. This signal indicates
the presence of a Valid signal from the optical transceiver per
port. Active-High. A Low signal indicates a loss of signal.

RefCLK

W12

19.44 MHz Reference Clock Input. This clock should have an
accuracy of ± 20 ppm.

PCAP0,
PCAP1

Y2
Y7

External PLL capacitor. These pins are provided to connect the
external capacitor of the internal PLLs. See

Figure 2-3

NCAP0,
NCAP1

External PLL capacitor. These pins are provided to connect the
external capacitor to the internal PLLs. See

Figure 2-3

REXT0
REXT1

Y10
Y11

External PLL resistor. These pins are provided to connect an
external resistor for the internal PLL. See

Figure 2-3

PHYBPSS

Analog test mode. Reserved for manufacturer's testing.
Should be connected to GND.

RECCLK0,
RECCLK1

V1
T4

Recovered clock divided by 8. This is a 19.44 MHz clock
optionally active for each port or optionally an 8 kHz clock
synchronized with each frame received.

CX2970x

Appendix B CX29702

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

B-5

B.2.4 Data Communication Channel Interface Pins

Table B-4. Data Communication Channel Interface Pins

Name

Number

I/O

Type

Functional Description

RSDCD12

The received section-DCC bytes (D1D3) are serialized out
using these pins, clocked by RSDCC12. A dedicated pin is
available for each port. Per-port disabling of this pin is
optional.

RSDCC12

P3
A4

The received section DCC (D1D3) clock. This is a 216 kHz
clock (50% duty cycle), which is active for part of the frame
time, and produces a nominal rate of 192 kHz to update the
RSDCD12 pins. A dedicated pin is available for each port.
Per-port disabling of this pin is optional.

RLDCD12

The received line-DCC bytes (D4D12) are serialized out using
these pins, clocked by RLDCC12. A dedicated pin is available
for each port. Per port disabling of this pin is optional.

RLDCC12 N2

The received line DCC (D4D12) clock. This is a 648 kHz clock
(50% duty cycle), which is active for part of the frame time
and produces a nominal rate of 576 kHz to update the
RLDCD12 pins. A dedicated pin is available for each port. Per
port disabling of this pin is optional.

TSDCD12

The transmit section-DCC bytes (D1D3) are serialized using
these pins, clocked by TSDCC12. A dedicated pin is available
for each port. Per-port disabling of this pin is optional.

TSDCC12

B10

The transmit section DCC (D1D3) clock. This is a 216 kHz
clock (50% duty cycle), which is active for part of the frame
time, and produces a nominal rate of 192 kHz to sample the
TSDCD12 pins. A dedicated pin is available for each port.
Per-port disabling of this pin is optional.

TLDCD12

K1
C8

The transmit line-DCC bytes (D4D12) are serialized using
these pins, clocked by TLDCC12. A dedicated pin is for each
port. Per-port disabling of this pin is optional.

TLDCC12

H1
B9

The transmitted line DCC (D4D12) clock. This is a 648 kHz
clock (50% duty cycle) that is active for part of the frame time
and produces a nominal rate of 576 kHz to sample the
TLDCD12 pins. A dedicated pin is available for each port.
Per-port disabling of this pin is optional.

Appendix B CX29702

CX2970x

B.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B-6

Mindspeed Technologies

29704-DSH-001-B

B.2.5 Microprocessor Interface Pins

Table B-5. Microprocessor Interface Pins

Name

No.

I/O

Type

Functional Description

D[15:0]

G20
H18
H20

J17
J18
J19

K17
K18
K19
L20
L18
L19

M20
M18
M17

N20

I/O

Microprocessor interface data bus

A[8:0]

C19
E17
C20

D19

E18
E19
F18

G17

E20

Microprocessor interface address bus

*CS

G18

Chip Select (active-low)

W/*R

G19

Write/Read control signal (High = Write, Low = Read).

*DSTRB

F20

Data strobe (active-low).

*READY

B20

High-Z

Ready (active-low)

*INTR

A19

Open
Drain

Interrupt signal (active-low, open drain).
When asserted, interrupt is active; Hi-Z when not asserted. This pin requires a
1k ohm pull up resistor.

The Interrupt request is deasserted three cycles after all the Interrupt registers
are read.

CX2970x

Appendix B CX29702

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

B-7

B.2.6 Alarm Status Serial Interface Pins

B.2.7 JTAG Interface Pins

B.2.8 Scan Interface Pins

Table B-6. Alarms Status Serial Interface Pins

Name

No.

I/O

Type

Functional Description

ASDO

N19

Alarms Status Data Out

*ASSTB

P20

Alarms Status Strobe (active-low)

ASCLK

P19

Alarms Status Clock

ASENB

P18

Alarms Status Enable
When tied to VSS, ASDO and *ASCLK are disabled.

Table B-7. JTAG Interface Pins

Name

No.

I/O

Type

Functional Description

TDO

High-Z

Test data output (when in JTAG mode). Leave unconnected when JTAG is not
used.

TDI

Test data input (when in JTAG mode). Tie to VDD when JTAG is not used (TMS
is Low).

TCK

Test Clock pin (when in JTAG mode). Tie to VDD when JTAG is not used.

TMS

Test Mode Select pin. High = JTAG mode, Low = Normal mode.

*TRST

Test Reset pin (when in JTAG mode). Tie to VSS when JTAG is not used
(active-Low).

Table B-8. Scan Interface Pins

Name

No.

I/O

Type

Functional Description

B12

Test Mode. Engineering only. Enables scan mode testing. Active-high (Should
be tied to VSS).

SCANEN

A12

Scan Enable. Engineering only. Enables scan shift in/out of the device.
Active-high (Should be tied to VSS).

Appendix B CX29702

CX2970x

B.4 Package Specifications

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

B-12

Mindspeed Technologies

29704-DSH-001-B

B.4 Package Specifications

The CX29702 is packed in a 272-PBGA package with a body size of 27x27 mm
and a ball pitch of 1.27 mm.

Figure B-1. CX29702 Package Layout (Bottom View)

V SS

T X M OD

RLDCC

[ 1]

T X SOC

T SDCC

[ 0]

T LDCC

[ 0]

V DD

T LDCD

[ 0]

T X DA T

A [ 15]

RLDCD

[ 0]

T X DA T

A [ 8]

T X DA T

A [ 6]

T X DA T

A [ 4]

T X DA T

A [ 2]

B P SSG

RE CCL

K 0

V SSA

RX D0-

T DI

RLDCD

[ 1]

V DD

V SS

T SDCD

[ 0]

T X E NB

T X A DD

[ 1]

T X A DD

[ 4]

T X CLK

T X DA T

A [ 14]

T X DA T

A [ 11]

RLDCC

[ 0]

T X DA T

A [ 5]

T X DA T

A [ 3]

RSDCD

[ 0]

SD1

V SSD

V DDA

P CA P 0+

T RST

RX A DD

[ 0]

T DO

RX E RR

ST P A

T X CLA

V [ 1]

T X P RT

T X A DD

[ 0]

T X A DD

[ 3]

V SS

T X DA T

A [ 13]

T X DA T

A [ 10]

T X DA T

A [ 7]

RSDCC

[ 0]

T X DA T

A [ 0]

SD0

V SSD

RX D0+

V SSA

V DDD

RSDCC

[ 1]

T CK

RX A DD

[ 1]

V SS

T X E OP

V DD

T X CLA

V [ 0]

V SS

T X A DD

[ 2]

V DD

T X DA T

A [ 12]

T X DA T

A [ 9]

V SS

T X DA T

A [ 1]

V DD

RE CCL

K 1

V SS

V DDA

P CA P 0-

T X D0+

RX DA T

A [ 0]

RX A DD

[ 2]

T M S

RSDCD

[ 1]

V DDD

V SSA

T X D0-

V SSD

RX DA T

A [ 2]

RX DA T

A [ 1]

RX A DD

[ 3]

V DD

V SSD

RX D1+

V DDA

RX DA T

A [ 4]

RX DA T

A [ 3]

T SDCD

[ 1]

RX A DD

[ 4]

V SSA

RX D1-

V SSA

P CA P 1+

RX DA T

A [ 6]

RX DA T

A [ 5]

T LDCD

[ 1]

V SS

P CA P 1-

V DDA

V DDD

RX DA T

A [ 9]

T LDCC

[ 1]

RX DA T

A [ 8]

RX DA T

A [ 7]

V SS

V DDD

T X D1+

V SSA

T X D1-

V SS

T SDCC

[ 1]

RX DA T

A [ 11]

RX DA T

A [ 10]

V SS

V DD

V DDA

RE X T 1

V DD

RX DA T

A [ 11]

RX DA T

A [ 12]

V DD

V SS

V SSD

V SSA

RE X T 2

SCA NE

T M

RX CLK

V SS

V DDA

RE FCLK

V SSA

RX DA T

A [ 14]

RX DA T

A [ 15]

V SS

V SSA

V SSD

RX CLA

V [ 0]

RX CLA

V [ 1

V DDA

V SSA

V DDA

RX P RT

V DD

V DDD

RX SOC

RX E OP

RV A L

RX M OD

V SSD

V SSA

V DDD

RX E NB

V SS

UP A DD

R[ 1]

V DD

UP A DD

R[ 7]

V SS

UP DA T

A [ 3]

UP DA T

A [ 6]

V DD

UP DA T

A [ 14]

V SS

V DD

V SS

V SSA

RX E RR RE SE T

UP A DD

R[ 4]

UP A DD

R[ 6]

UP DA T

A [ 1]

UP DA T

A [ 4]

UP DA T

A [ 7]

UP DA T

A [ 10]

UP DA T

A [ 13]

A SE NB

V DDD

V SSD

I NT R

V DD

UP A DD

R[ 0]

UP A DD

R[ 3]

UP A DD

R[ 5]

WRNRD

UP DA T

A [ 5]

UP DA T

A [ 8]

UP DA T

A [ 11]

A SDO

A SCLK

V DD

V DDD

V DDA

V SSA

V DDA

Appendix C CX29701

CX2970x

C.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C-2

Mindspeed Technologies

29704-DSH-001-B

C.2 Pin Description

C.2.1 UTOPIA/POS Level 2 Interface

Table C-1. UTOPIA/POS Level 2 Interface

Name

Number

I/O

Type

Functional Description

TxClav[0]
(ATM mode)

High-Z

UTOPIA Transmit Cell Available. Supports Cell-Level
Handshake. Indicates that the transmit FIFO can accept a
complete cell. The mode One Rx/Tx CLAV requires only
TxClav[0]. TxClav[0] is updated on the rising edge of TxClk.
This pin requires a 470 ohm pull down resistor.

DTPA [0]
(POS mode)

High-Z

POS Interface Direct Transmit Packet Available (DTPA).
Transition HIGH indicates that a (predefined) minimum
number of bytes is available in the corresponding FIFO. Once
HIGH, the DTPA pin indicates that the FIFO is not full.
Transition LOW indicates that the FIFO is full or almost full
(programmable by the user). DTPA[0] is updated on the rising
edge of TxClk. This pin requires a 470 ohm pull down resistor.

RxClav[0]
(ATM mode)

A14

High-Z

UTOPIA Receive Cell Available. Support Cell Level Handshake
indicates that the receive FIFO has a complete cell available.
The mode One Rx/Tx CLAV requires only RxClav[0]. RxClav[0]
is sampled on the rising edge of RxClk. This pin requires a 470
ohm pull down resistor.

DRPA[0]
(POS mode)

A14

High-Z

POS Interface Receive Packet Available. Indicates that the
receive FIFO has at least one End-Of-Packet available or a
predefined number of bytes. DRPA[0] is sampled on the rising
edge of RxClk. This pin requires a 470 ohm pull down resistor.

CX2970x/2/1

Appendix C CX29701

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

C-3

C.2.2 POS Level 2 Interface Specific

Table C-2. POS Level 2 Interface Specific

Name

No.

I/O

Type

Functional Description

STPA

High-Z

TxMOD
(POS mode)

TxEOP
(POS mode)

TxERR
(POS mode)

Transmit Error. Indicates the current packet is aborted and should be
discarded. TxERR should be asserted only during the last word of a packet.

RVAL
(POS mode)

C16

High-Z

RxMOD
(POS mode)

D16

High-Z

RxEOP
(POS mode)

B16

High-Z

RxERR
(POS mode)

A18

High-Z

NOTE(S):

I = Input, O = Output, E = PECL, T = TTL

Appendix C CX29701

CX2970x

C.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C-4

Mindspeed Technologies

29704-DSH-001-B

C.2.3 Line Interface Pins

Table C-3. Line Interface Pins

Name

Number

I/O

Type

Functional Description

RxD0+
RxD0

V3
Y1

Line Receive Data.Differential data inputs. These inputs
contain NRZ encoded data. Receive clocks are recovered from
these inputs.

TxD0+
TxD0

Line Transmit Data. Differential data outputs. These outputs
contain NRZ encoded data.

SD0

Signal Detect. Single-ended PECL input. This signal indicates
the presence of a Valid signal from the optical transceiver per
port. Active-High. A Low signal indicates a loss of signal.

RefCLK

W12

19.44 MHz Reference Clock Input. This clock should have an
accuracy of ± 20 ppm.

PCAP0

External PLL capacitor. These pins are provided to connect the
external capacitor of the internal PLLs. See

Figure 2-3

NCAP0

External PLL capacitor. These pins are provided to connect the
external capacitor to the internal PLLs. See

Figure 2-3

REXT0
REXT1

Y10
Y11

External PLL resistor. These pins are provided to connect an
external resistor for the internal PLL. See

Figure 2-3

PHYBPSS I T

Analog test mode. Reserved for manufacturer's testing.
Should be connected to GND.

RECCLK0

Recovered clock divided by 8. This is a 19.44 MHz clock
optionally active for each port or optionally an 8 kHz clock
synchronized with each frame received.

CX2970x/2/1

Appendix C CX29701

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

C-5

C.2.4 Data Communication Channel Interface Pins

Table C-4. Data Communication Channel Interface Pins

Name

Number

I/O

Type

Functional Description

RSDCD1

The received section-DCC bytes (D1D3) are serialized out
using this pin, clocked by RSDCC1. Disabling of this pin is
optional.

RSDCC1

The received section DCC (D1D3) clock. This is a 216 kHz
clock (50% duty cycle), which is active for part of the frame
time, and produces a nominal rate of 192 kHz to update the
RSDCD1 pin. Disabling of this pin is optional.

RLDCD1

The received line-DCC bytes (D4D12) are serialized out using
this pin, clocked by RLDCC1. Disabling of this pin is optional.

RLDCC1

The received line DCC (D4D12) clock. This is a 648 kHz clock
(50% duty cycle), which is active for part of the frame time
and produces a nominal rate of 576 kHz to update the RLDCD1
pin. Disabling of this pin is optional.

TSDCD1

The transmit section-DCC bytes (D1D3) are serialized using
this pin, clocked by TSDCC1. Disabling of this pin is optional.

TSDCC1

The transmit section DCC (D1D3) clock. This is a 216 kHz
clock (50% duty cycle), which is active for part of the frame
time, and produces a nominal rate of 192 kHz to sample the
TSDCD1 pin. Disabling of this pin is optional.

TLDCD1

The transmit line-DCC bytes (D4D12) are serialized using this
pin, clocked by TLDCC1. Disabling of this pin is optional.

TLDCC1

The transmitted line DCC (D4D12) clock. This is a 648 kHz
clock (50% duty cycle) that is active for part of the frame time
and produces a nominal rate of 576 kHz to sample the TLDCD1
pin. Disabling of this pin is optional.

Appendix C CX29701

CX2970x

C.2 Pin Description

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C-6

Mindspeed Technologies

29704-DSH-001-B

C.2.5 Microprocessor Interface Pins

Table C-5. Microprocessor Interface Pins

Name

No.

I/O

Type

Functional Description

D[15:0]

G20
H18
H20

J17
J18
J19

K17
K18
K19
L20
L18
L19

M20
M18
M17

N20

I/O

Microprocessor interface data bus

A[8:0]

C19
E17
C20

D19

E18
E19
F18

G17

E20

Microprocessor interface address bus

*CS

G18

Chip Select (active-low)

W/*R

G19

Write/Read control signal (High = Write, Low = Read).

*DSTRB

F20

Data strobe (active-low).

*READY

B20

High-Z

Ready (active-low)

*INTR

A19

Open
Drain

Interrupt signal (active-low, open drain).
When asserted, interrupt is active; Hi-Z when not asserted. This pin requires a
1k ohm pull up resistor.

The Interrupt request is deasserted three cycles after all the Interrupt registers
are read.

CX2970x/2/1

Appendix C CX29701

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C.2 Pin Description

29704-DSH-001-B

Mindspeed Technologies

C-7

C.2.6 Alarm Status Serial Interface Pins

C.2.7 JTAG Interface Pins

C.2.8 Scan Interface Pins

Table C-6. Alarms Status Serial Interface Pins

Name

No.

I/O

Type

Functional Description

ASDO

N19

Alarms Status Data Out

*ASSTB

P20

Alarms Status Strobe (active-low)

ASCLK

P19

Alarms Status Clock

ASENB

P18

Alarms Status Enable
When tied to VSS, ASDO and *ASCLK are disabled.

Table C-7. JTAG Interface Pins

Name

No.

I/O

Type

Functional Description

TDO

High-Z

Test data output (when in JTAG mode). Leave unconnected when JTAG is not
used.

TDI

Test data input (when in JTAG mode). Tie to VDD when JTAG is not used (TMS
is Low).

TCK

Test Clock pin (when in JTAG mode). Tie to VDD when JTAG is not used.

TMS

Test Mode Select pin. High = JTAG mode, Low = Normal mode.

*TRST

Test Reset pin (when in JTAG mode). Tie to VSS when JTAG is not used
(active-Low).

Table C-8. Scan Interface Pins

Name

No.

I/O

Type

Functional Description

B12

Test Mode. Engineering only. Enables scan mode testing. Active-high (Should
be tied to VSS).

SCANEN

A12

Scan Enable. Engineering only. Enables scan shift in/out of the device.
Active-high (Should be tied to VSS).

CX2970x/2/1

Appendix C CX29701

OptiPHYTM-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer

C.4 Package Specifications

29704-DSH-001-B

Mindspeed Technologies

C-13

C.4 Package Specifications

The CX29701 is packed in a 272-PBGA package with a body size of 27x27 mm
and a ball pitch of 1.27 mm.

Figure C-1. CX29701 Package Layout (Bottom View)

V SS

T X M OD

T X SOC

T SDCC

[ 0]

T LDCC

[ 0]

V DD

T LDCD

[ 0]

T X DA T

A [ 15]

RLDCD

[ 0]

T X DA T

A [ 8]

T X DA T

A [ 6]

T X DA T

A [ 4]

T X DA T

A [ 2]

B P SSG

RE CCL

K 0

V SSA

RX D0-

T DI

V DD

V SS

T SDCD

[ 0]

T X E NB

T X A DD

[ 1]

T X A DD

[ 4]

T X CLK

T X DA T

A [ 14]

T X DA T

A [ 11]

RLDCC

[ 0]

T X DA T

A [ 5]

T X DA T

A [ 3]

RSDCD

[ 0]

V SSD

V DDA

P CA P 0+

T RST

RX A DD

[ 0]

T DO

RX E RR

ST P A

T X P RT

T X A DD

[ 0]

T X A DD

[ 3]

V SS

T X DA T

A [ 13]

T X DA T

A [ 10]

T X DA T

A [ 7]

RSDCC

[ 0]

T X DA T

A [ 0]

SD0

V SSD

RX D0+

V SSA

V DDD

T CK

RX A DD

[ 1]

V SS

T X E OP

V DD

T X CLA

V [ 0]

V SS

T X A DD

[ 2]

V DD

T X DA T

A [ 12]

T X DA T

A [ 9]

V SS

T X DA T

A [ 1]

V DD

V SS

V DDA

P CA P 0-

T X D0+

RX DA T

A [ 0]

RX A DD

[ 2]

T M S

V DDD

V SSA

T X D0-

V SSD

RX DA T

A [ 2]

RX DA T

A [ 1]

RX A DD

[ 3]

V DD

V SSD

V DDA

RX DA T

A [ 4]

RX DA T

A [ 3]

RX A DD

[ 4]

V SSA

RX DA T

A [ 6]

RX DA T

A [ 5]

V SS

V DDA

V DDD

RX DA T

A [ 9]

RX DA T

A [ 8]

RX DA T

A [ 7]

V SS

V DDD

V SSA

V SS

RX DA T

A [ 11]

RX DA T

A [ 10]

V SS

V DD

V DDA

RE X T 1

V DD

RX DA T

A [ 11]

RX DA T

A [ 12]

V DD

V SS

V SSD

V SSA

RE X T 2

SCA NE

T M

RX CLK

V SS

V DDA

RE FCLK

V SSA

RX DA T

A [ 14]

RX DA T

A [ 15]

V SS

V SSA

V SSD

RX CLA

V [ 0]

V DDA

V SSA

V DDA

RX P RT

V DD

V DDD

RX SOC

RX E OP

RV A L

RX M OD

V SSD

V SSA

V DDD

RX E NB

V SS

UP A DD

R[ 1]

V DD

UP A DD

R[ 7]

V SS

UP DA T

A [ 3]

UP DA T

A [ 6]

V DD

UP DA T

A [ 14]

V SS

V DD

V SS

V SSA

RX E RR RE SE T

UP A DD

R[ 4]

UP A DD

R[ 6]

UP DA T

A [ 1]

UP DA T

A [ 4]

UP DA T

A [ 7]

UP DA T

A [ 10]

UP DA T

A [ 13]

A SE NB

V DDD

V SSD

I NT R

V DD

UP A DD

R[ 0]

UP A DD

R[ 3]

UP A DD

R[ 5]

WRNRD

UP DA T

A [ 5]

UP DA T

A [ 8]

UP DA T

A [ 11]

A SDO

A SCLK

V DD

V DDD

V DDA

V SSA

V DDA

29704-DSH-001-B

Mindspeed Technologies

D-1

Appendix D Application Examples

D.1 Alarms Status Serial Interface (ASSI)

Figure D-1

illustrates a sample application for the ASSI. This application

provides permanent status of LOS, RxC, TxC, and LOF for each one of the ports.
In a similar manner, all other indications that the ASSI provides may be exploited.
An application using less indications is also an option.

The interface clock (ASCLK) shifts the serial data (ASDO) through the shift

registers. The data strobe (*ASSTB) latches the data at the appropriate location.

Figure D-1. ASSI Application Example

101344_044

CX29704

ASDO

ASCLK

*ASSTB

VCC

Shift

Latches

VCC

CLK

CLR

QA
QB
QC
QD
QE
QF
QG
QH

CLK

CLR

3
4
5
6

10
11
12
13

3
4
5
6

10
11
12
13

3
4
7
8
13
14
17
18

CLK

Q0
Q1
Q2
Q3

Q4
Q5

Q6
Q7

D0
D1
D2
D3

D4
D5

D6
D7

CLK

Q0
Q1
Q2
Q3

Q4
Q5

Q6
Q7

D0
D1
D2
D3

D4
D5

D6
D7

2
5
6
9

12
15
16
19

2
5
6
9

12
15
16
19

LOS 3
LOS 2
LOS 1
LOS 0
RxC 3
RxC 2
RxC 1
RxC 0

TxC 3
TxC 2
TxC 1
TxC 0

LOF 3
LOF 2
LOF 1
LOF 0

29704-DSH-001-B

Mindspeed Technologies

F-1

Appendix F References

ATM Forum--"ATM User Network Interface Specification," V3.1,
September 1994.

ATM Forum--"UTOPIA Level 2, v1.0," June 1995.

ATM Forum--"UTOPIA Level 1, v2.01," March 1994.

ITU-T Recommendation I.432, "B-ISDN User Network
Interface--Physical Interface Specification," June 1990.

ITU-T Recommendation G.709, "Synchronous Multiplexing Structure,"
March 1993.

Bell Communications Research--GR-253-CORE, Issue 2, Rev 1,
"SONET Transport Systems, Common Generic Criteria," December 1997.

American National Standard Institute--T1.646, "Broadband
ISDNPhysical Layer Specification for User Network Interfaces," 1995.

American National Standards Institute--T1.105, "SONETBasic
Description including Multiplex Structure, Rates, and Formats," 1995.

IEEE Standard Test Access Port- and Boundary-Scan Architecture,
October 1993.

10.

Saturn Group--"POS-PHY Level 2 Interface," December 1998

11.

Bell Communications Research--GR-436-CORE, "Digital Network
Synchronization Plan," Issue 1 Revision 1, June 1996.

12.

ITU-T Recommendation G.703--"Physical/Electrical Characteristics of
Hierarchical Digital Interfaces," 1991.

13.

ITU-T Recommendation G.704--"General Aspects of Digital
Transmission".

14.

Systems; Terminal Equipment--Synchronous Frame Structures Used at
1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels, July 1995.

15.

ITU Recommendation G.707--"Network Node Interface for the
Synchronous Digital Hierarchy," 1996.

16.

ITU Recommendation G.781--"Structure of Recommendations on
Equipment for the Synchronous Design Hierarchy (SDH)," January 1994.

17.

ITU Recommendation G.783--"Characteristics of Synchronous Digital
Hierarchy (SDH) Equipment Functional Blocks," 1996.

18.

IETF Network Working Group--RFC-2615, "Point-to-Point Protocol
(PPP) Over SONET/SDH Specification," June 1999.

19.

IETF Network Working Group--RFC-1662, "PPP in HDLC Like
Framing," July 1994.

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OptiPHY-F155