MC2046-2/C
Preliminary Issue E
22 October, 1999
Page 1
1.25Gbps Limiting Amplifier MC2046-2/C
Postamplifier/Quantiser for Gigabit Ethernet and Fiber Channel Applications
Main Features:
Low-cost IC, available as die or in QSOP16
and TSSOP20 packages. Fabricated in
advanced sub-micron BiCMOS process.
Very wide range of operation; suitable for up
to 1.5Gbps. 4mV input sensitivity at 1.25Gbps.
Pin-compatible, superior replacement for
Motorola MC10SX1125
Microcosm MC2044C/MC2045-2 Pin-
Compatible.
Programmable input-signal level detect. (On-
chip default, saving external components)
Fully differential
3.3 volt operation. (5v supported)
CMOS and PECL Link-Status variants.
Ordering Information
Part Number
Pin Package
MC2046CT20 TSSOP20
MC2046T20 TSSOP20
MC2046Q16 QSOP16
MC2046CQ16 QSOP16
MC2046DIEWP Waffle
Pack
MC2046WAFER Expanded whole 8" on a 10"
grip ring
General Description
:
The MC2046-2/C is a 2
nd
-generation, integrated,
high gain limiting amplifier intended for high speed
fiberoptics based communications. Normally placed
following the photodetector and transimpedance or
pre-amplifier, the limiting amplifier provides the
necessary gain to give PECL compatible logic
outputs.
The MC2046-2/C also includes a programmable
signal-level detector, allowing the user to set
thresholds at which the logic outputs are enabled.
Capable of operating over a very wide frequency
range, the MC2046-2 supports most fiberoptic
industry standards, but it is especially suited to
1.06Gbps Fiber Channel and 1.25Gbps Ethernet. It
is pin and functionally compatible with the
Motorola MC10SX1125 and earlier Microcosm
Post-amplifiers.
The MC2046-2 die has both PECL and CMOS
Status outputs. Packaged, the MC2046-2 has PECL
Status outputs and the MC2046-2C has CMOS
Status outputs.
Buffer
Limiting
Amp.
ECL
Buffer
Jam
Buffer
Reference
VccA
Cazp Cazn
VccE
GndA
GndE
Din
Din
Vref
Dout
Dout
ST
Jam
ST
Detection
Threshold
Circuit
Level
Detector
Iset
Vset
Vdet
MC2046-2/C
Preliminary Issue E
22 October, 1999
Page 2
Pin descriptions
TSSOP 20
Or Die
Pin No.
QSOP16
Pin No.
Name
Function
1
1
Cazn
Auto-zero capacitor pin. Connect Caz between this pin and Pin2.
2 2
Cazp
See
Pin
1
3
-
Iset
May be left unconnected or else may connect resistor for
programming threshold detection level See description of
Detection Threshold Circuit.
4
3
GndA
Ground pin for analogue section. Connect to most negative supply.
Must be at same potential as GndE.
5
4
Din
Differential Data Input.
6
5
Dinb
Inverse Differential Data Input
7
6
VccA
Supply pin for analogue section. Connect to most positive supply.
Must be at the same potential as VccE
8
7
Vref
Test point for on-chip voltage reference. This pin may be left
unconnected or else a capacitor may be connected between this pin
and the positive supply.
11
8
Jam
ECL and CMOS compatible logic input. When HIGH, data outputs
Dout and Doutb are disabled (Dout being held LOW and Doutb
being held HIGH).
12 9
STb
1
Signal detect status output. LOW when input signal level is above
detection threshold.
This output may be connected to the Jam input pin.
13 10
ST
1
Signal detect status output. HIGH when input signal level is above
detection threshold.
14,15
11
GndE
Ground pin for PECL output stage. Connect to the most negative
supply. Must be at the same potential as GndA
16
12
Doutb
PECL compatible differential data output. In phase with input Dinb-
Din.
17
13
Dout
PECL compatible differential data output. In phase with input Din-
Dinb.
18,19
14
VccE
Supply pin for PECL output stage. Connect to the most positive
supply. Must be at the same potential as VccA.
20
16
Vset
Input threshold-level setting circuit. Connect to Analogue Ground
via a resistor. See Application diagram. Must be connected to
ground even if function not required.
1
MC2046-2 - ECL outputs are 100k compatible. MC2046-2C - CMOS output levels.
Absolute maximum ratings
Symbol
Parameter
Rating
Units
Vcc
Power supply (Vcc-Gnd)
6
V
Ta
Operating ambient
-40 to +85
C
Tstg
Storage temperature
-65 to +150
C
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reliable operation at
these extremes for any length of time is not implied.
MC2046-2/C
Preliminary Issue E
22 October, 1999
Page 3
Recommended operating conditions
Symbol
Parameter
Rating
Units
Vcc
Power supply (Vcc-Gnd)
3.0 to 5.5
V
Ta
Operating ambient
-40 to +85
C
DC Electrical Characteristics (over recommended operating
conditions)
Symbol
Parameter
Min.
Typ.
Max.
Units
Vin
Minimum input signal
Maximum input signal
Single-ended
Differential
Single-ended
Differential
-
-
1
2
-
-
-
-
0.002
0.004
-
-
Vp
Vp-p
Vp
Vp-p
Vos
Input offset voltage
-
-
tba
V
Vn
Input RMS noise
-
-
93
V
Vth
Level detect programmability min
max
-
100
-
-
2
-
mVp-p
mVp-p
Vhys
Level detect hysteresis (optical)
1.75
2.25
2.75
dB
Iinl
JAM input current (at 0V)
-10
-
10
A
V
OH
Data
output
HIGH
-1.051 - -0.879
V
V
OL
Data
output
LOW
-1.892 - -1.548
V
V
OH
-V
OL
Differential
Data
output
0.627
-
0.879 V
Icc
Supply current (no ECL loads)
-
-
40
mA
AC Electrical Characteristics (over recommended operating
conditions)
Symbol
Parameter
Min.
Typ.
Max.
Units
BWL
Lower -3dB frequency
-
-
3
KHz
BWU
Upper -3dB frequency
1000
-
-
MHz
Rin
Differential input resistance
2.8
-
9.7
kOhms
Cin Input
capacitance
-
-
2 pF
Tpwd Pulse
Width
Distortion
-
-
30 pS
Tr,Tf
ECL out rise/fall times
(20-80% points)
- 200 250 pS
Raz
Auto-zero output resistance
-
25
-
kOhms
Tld
Level detect time constant
0.5
1
2.0
S
Microcosm MC2046-2/MC2046-2C/MC2044C compatibility
The MC2046-2/C and MC2044C are pin-compatible and functionally identical, except that the MC2044C has
lower internal bandwidth to improve input sensitivity. In all cases, the C suffix indicates CMOS level Link-Status
outputs, while the absence of the C indicates PECL levels.
MC2046-2/C
Preliminary Issue E
22 October, 1999
Page 4
Signal Path Description
Input biasing
The Data Input pins are internally DC biased at
approx. VccA 1V, via the Rin resistors. Although
the MC2046-2 can be DC coupled, normally it will
be AC coupled, using capacitors C1 & C2. Note
that Rin and C1,2 form a filter to low frequencies.
The capacitors must therefore be large enough to
pass the lowest input frequencies (consecutive `1's
or `0's) of interest. For example, setting C1,2 to
10nF will give a typical -3dB point of approx.
10KHz.
Autozero circuit
The MC2046-2 includes an autozero circuit. In the
absence of data, the feedback amplifier and
summing circuit cancel the inherent offset voltage
of the signal path, keeping the comparator at its
toggle point. The time constant of this circuit is set
by the combination of Raz and Caz, but is not
critical. Caz is normally set to 100nF.
Power supply decoupling &
optimising sensitivity
Generally, a 4-layer board is required to achieve
maximum sensitivity. A good layout on a 4+ layer
board should mean ferrite suppressors (as shown)
are unnecessary. Contact Microcosm for further
assistance in this area.
MC2046-2/C
Preliminary Issue E
22 October, 1999
Page 5
Caz 10nF
Din
Dout
Dout
Rin
10k
Rin
10k
Raz
10k
Raz
10k
Din
C1
C2
Comparator
Vcc
VccA
Optional Surface-
mount Ferrite beads
VccE
Gnd
GndA
GndE
Forward Gain Path block diagram.
VccA
GndA
Detection Threshold Circuit block diagram
Vref
Vset
Iset
Vdet
Ra
Rd
Rb
Rc
Rvset
Riset
Voltage controlled
current source VCCS1
Voltage controlled
current source VCCS2
Level detector
The MC2046-2 provides for programmable input-signal level detection, and this may be used to
automatically force the Data Outputs to a known state if the input signal falls below threshold. This is
normally used to allow data to propagate only when the signal is above the users' Bit-Error-Rate (BER)
requirement. It therefore also stops the data outputs toggling due to noise when no signal is present.
Referring to the block diagram shown on the front page, the Detection Threshold Circuit produces a
differential signal "Vdet". The Level Detector compares the input differential peak amplitude with this
voltage. The Detection Threshold Circuit is shown here in detail.
Vref is 0.5V below VccA. R
vset
and R
iset
are optional and, if connected, appear in parallel with on-chip
resistors R
b
and R
c
, respectively. For the following, let
R
b
'
be the parallel combination of R
b
and R
vset
,
and let
R
c
'
be the parallel combination of R
c
and R
iset
.
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