Micronas
page 1 of 10
Subject:
Data Sheet Concerned:
Supplement:
Edition:
Preliminary Data Sheet Supplement
VPC 3230D-C5
06.08.01
The VPC 3230D-C5 is hardware- and software-compatible to VPC 3230D-B3. Problems 15 and 21 have been cor-
rected in this version.
It provides the following new functions:
1. Additional horizontal and vertical sync outputs HSYA, VSYA to support analog RGB insertion (e. g. PIP or OSD/
Text)
2. Improved external memory controlling to suppress joint lines and joint field distortions
The new control bits as well as the modified pinning are described in the Preliminary data sheet.
Problem list for VPC 3230D-C5
Data Sheet Errata VPC 32xxD-C5 (for Preliminary Data Sheet: Edition July 26, 2001; 6251-472-1PD).
The following description replaces the corresponding specification on page 72 of the Preliminary Data Sheet (6251-
472-1PD) (applies to B3 and following versions)
No.
Problem
Description
Comment
OK
22.
no PAL+ helper output
In PAL+ mode, the demodulated helper
signal is not available at the luma output
pins
firmware change
workaround:
23.
data output hold time out
of spec
In case of 16 MHz output mode, max. load
on pins and min. V
SUPY/C/PA/LLC
, the data
output hold time is approx. 1 ns less than
specified
hardware redesign
workaround:
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
t
OH
Output Hold Time
14
ns
LLC2=32.0 MHz,
OMODE=1,
DBCLK=0/1
Additional Information for the VPC 32xxD
VPC 323xD
6251-472-1PD, Edition July 26, 2001
No. 7/ 6251-472-1PDS
Aug. 22, 2001
VPC 32xxD
VPC 32xxD
PRELIMINARY DATA SHEET SUPPLEMENT
page 2 of 10
Micronas
VPC 3230D-B3
06.10.00
The VPC 3230D-B3 is hardware- and software-compatible to VPC 3230D-B2. Problems 13 and 17 to 20 have been
corrected in this version.
It provides the following new functions:
1. New status bit `SWITCH' of Automatic Standard Recognition (ASR)
indicating a change of the chroma standard
2. New vertical synchronization `AV/VS_LOCK' of the PIP for two VPCD applications
to provide a stable PIP display in case of no input signal for VPC
main
Problem list for VPC 3230D-B3
Application Note VPC 32xxD-B3 (for Advance Information: Edition Jan. 19, 1999; 6251-472-1AI).
To ensure optimum EMI performance of the VPC 32xxD clock and data outputs, no external resistors and/or induc-
tors should be connected to these pins (applies to B1 and following versions)!
No.
Problem
Description
Comment
OK
15.
LLC1/LLC2 output timing
Clock skew between LLC1 and LLC2 out
of spec
This may cause disturbances like horizon-
tal jitter of the picture and/or an unstable
chroma demultiplex, in feature-boxes
using both (LLC1 and LLC2) clocks.
hardware redesign C4
workaround for feature
boxes using LLC1 and
LLC2: adjust overall
capacitive load on LLC1
to min. 33 pF and on
LLC2 to min. 22 pF.
C5
21.
wrong interlace in NTSC
In case of NTSC input and AV_LOCK or
VS_LOCK = 1, the interlace of the main
picture is wrong (2VPCD application only).
hardware redesign C4
workaround: set
DIS_INTL = 1 in NTSC
C5
Micronas
page 3 of 10
PRELIMINARY DATA SHEET SUPPLEMENT
VPC 32xxD
Data Sheet Errata VPC 32xxD-B3 (for Advance Information: Edition Jan. 19, 1999; 6251-472-1AI).
The following description must be added in Table 3-2 on page 40 of the Advance Information (6251-472-1AI)
(applies to B3).
FP Sub-
address
Function
Default
Name
h'148
Enable automatic standard recognition
bit[0]
0/1
PAL B,G,H,I
(50 Hz)
4.433618
bit[1]
0/1
NTSC M
(60 Hz)
3.579545
bit[2]
0/1
SECAM (50
Hz)
4.286
bit[3]
0/1
NTSC44
(60 Hz)
4.433618
bit[4]
0/1
PAL M
(60 Hz)
3.575611
bit[5]
0/1
PAL N
(50 Hz)
3.582056
bit[6]
0/1
PAL 60
(60 Hz)
4.433618
bit[10:7] reserved set to 0
bit[11]
1
reset status information bit `switch' in register
`asr_status' (cleared automatically)
0: disable recognition; 1: enable recognition
Note: For correct operation, do not change FP reg. 20h and 21h while
ASR is enabled!
0
ASR_ENABLE
h'14e
Status of automatic standard recognition
bit[0]
1
error of the vertical standard (neither 50 nor 60 Hz)
bit[1]
1
detected standard is disabled
bit[2]
1
search active
bit[3]
1
search terminated, but failed
bit[4]
1
no color found
bit[5]
1
standard has been switched (since last reset of this
flag with bit[11] of ASR_ENABLE)
bit[4:0]
00000
all ok
00001
search not started, because vwin error detected
(no input or SECAM L)
00010
search not started, because detected vert. standard
not enabled
0x1x0
search started and still active
01x00
search failed (found standard not correct)
01x10
search failed, (detected color standard not enabled)
10000
no color found (monochrome input or switch betw.
CVBS/SVHS necessary)
0
ASR_STATUS
VWINERR
DISABLED
BUSY
FAILED
NOCOLOR
SWITCH
VPC 32xxD
PRELIMINARY DATA SHEET SUPPLEMENT
page 4 of 10
Micronas
The following description must be added in Table 3-2 on page 35 of the Advance Information (6251-472-1AI)
(applies to B3).
The following description must be added in Table 3-2 on page 42 of the Advance Information (6251-472-1AI)
(applies to B1 and following versions).
I
2
C Sub-
address
Number
of bits
Mode
Function
Default
Name
PIP Control
h'84
16
w/r
VPC MODE:
bit[0]
0/1
dis-/enable field memory control for PIP
bit[1]
0/1
double/single VPC application
bit[2]
0/1
select VPC
pip
/VPC
main
mode
bit[3]
0/1
4:3/16:9 screen
bit[4]
0/1
13.5/16 MHz output pixel rate
bit[5]
0/1
vertical PIP window size is based on
a 625/525 line video
bit[7:6]
field memory type
00
TI TMS4C2972/3
01
PHILIPS SAA 4955TJ
10
reserved
11
other (OKI MSM5412222, ...)
bit[11:8] are evaluated only if bit[7:6] = 11
bit[8]
0/1
delay the video output compared to WE for
0/1 LLC1 clock, if DBLCLK = 0
0/1 LLC2 clock, if DBLCLK = 1
bit[9]
0/1
pos/neg polarity for WE and RE signals
bit[10]
0/1
pos/neg polarity for IE and OE signals
bit[11]
0/1
pos/neg polarity for RSTWR signal
bit[12]
reserved (set to 0)
bit[13]
0/1
vertical PIP position synchronized by input
video/vertical sync in case of no video
input, FLW = 0 and LLC PLL disabled.
For VPC
main
combined with a feature-box
without read/write mask only!
bit[14]
0/1
vertical PIP position synchronized by input
video/free running sync raster FLW
bit[15]
reserved (set to 0)
This register is updated when the PIPOPER register is written.
0
VPCMODE
ENA_PIP
SINGVPC
MAINVPC
F16TO9
F16MHZ
W525
FIFOTYPE
VIDEODEL
WEREINV
IEOEINV
RSTWRINV
AV_LOCK
VS_LOCK
FP Sub-
address
Function
Default
Name
h'17a
ACC PAL+ Helper gain adjust, gain is referenced to PAL burst
bit[11:0] 0...4094
(1591 corresponds to 100% helper gain)
4095
disabled (testmode only)
a value of 4095 allows manual adjust of Helper amplitude via ACCH
1591
HLPGAIN
Micronas
page 5 of 10
PRELIMINARY DATA SHEET SUPPLEMENT
VPC 32xxD
VPC 3230D-B2
15.12.99
The VPC 3230D-B2 is hardware- and software-compatible to VPC 3230D-B1. Problems 4, 8, and 16 have been cor-
rected in this version.
Problem list for VPC 3230D-B2
No.
Problem
Description
Comment
OK
13.
PIP picture corrupted
In case of WRMAIN active, a change of
the video input signal may corrupt the PIP
picture (single VPC application only).
hardware redesign B3
workaround:
set AVSTRT < 81 for
16 MHz mode or
AVSTRT < 65 for
13.5 MHz mode
B3
15.
LLC1/LLC2 output timing
Clock skew between LLC1 and LLC2 out
of spec
hardware redesign B3
17.
FF control signals sup-
pressed
In case of main picture = NTSC or VGA,
PIP picture = PAL or SECAM, W525 = 0
and MODSEL = 3, the FFOE, FFRE,
FFIE, and FFWE signals are suppressed
in field 1 for dedicated settings of VSTR,
e. g. VSTR = 134.
hardware redesign B3
B3
18.
TINT value overwritten
The ASR sets the TINT value (FP reg.
dc'h) to 0 automatically if the color stan-
dard changes from NTSC to PAL or
SECAM.
firmware change B3
workaround: rewrite
TINT value
B3
19.
clamp lock in visible at the
top edge of the picture
Copy-protected YC
r
C
b
input signals dis-
turb the internal clamp control. Therefore,
the clamp lock in remains visible at the top
edge of the picture.
hardware redesign B3
B3
20.
horizontal clamp stripes
on component and/or
CVBS signals
There have been reports of sporadic prob-
lems with VPC 32xxD at power-up. These
problems manifest themselves in the form
of clamping stripes.
hardware redesign B3
workaround:
replace the 10
F capac-
itors attached to the pins
66 (VRT) and 78 (VREF)
with 47
F
B3
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