ADVANCE INFORMATION

VDP 3108

MICRONAS INTERMETALL

Contents

Page

Section

Title

Introduction

1.1.

System Architecture

Functional Description

2.1.

Analog Front End

2.1.1.

Input Selector

2.1.2.

Clamping

2.1.3.

Automatic Gain Control

2.1.4.

Analog-to-Digital Converters

2.1.5.

ADC Range

2.1.6.

Digitally Controlled Clock Oscillator

2.2.

Color Decoder

2.2.1.

IF-Compensation

2.2.2.

Demodulator

2.2.3.

Chrominance Filter

2.2.4.

Frequency Demodulator

2.2.5.

Burst Detection

2.2.6.

Color Killer Operation

2.2.7.

Delay Line/Comb Filter

2.2.8.

Luminance Notch filter

2.2.9.

Skew Filter

2.2.10.

Picture Bus Color Space

2.3.

Digital Video Interfaces

2.3.1.

Picture Bus Interface

2.3.2.

Digital RGB Interface

2.3.3.

Priority Codec

2.4.

Display Processor

2.4.1.

Contrast Adjustment

2.4.2.

Black Level Expander

2.4.3.

Dynamic Peaking

2.4.4.

Brightness Adjustment

2.4.5.

Soft Limiter

2.4.6.

Chroma Interpolation

2.4.7.

Chroma Transient Improvement

2.4.8.

Dematrix

2.4.9.

RGB Processing

2.4.10.

FIFO Display Buffer

2.5.

Analog Back End

2.5.1.

CRT Measurement and Control

2.6.

Synchronization and Deflection

2.6.1.

Video Sync Processing

2.6.2.

Deflection Processing

2.6.3.

Vertical, East璚est Deflection

2.6.4.

Protection Circuitry

2.7

Reset and Standby Functions

Serial Interface

3.1.

C Bus Interface

3.2.

Control and Status Registers

VDP 3108

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Specifications

4.1.

Outline Dimensions

4.2.

Pin Connections and Short Descriptions

4.3.

Pin Descriptions (pin numbers for 68璓LCC)

4.4.

Pin Configuration

4.5.

Pin Circuits

4.6.

Electrical Characteristics

4.6.1.

Absolute Maximum Ratings

4.6.2.

Recommended Operating Conditions

4.6.3.

Characteristics

4.6.4.

Recommended Crystal Characteristics

4.7.

Application Circuit

Data Sheet History

VDP 3108

ADVANCE INFORMATION

MICRONAS INTERMETALL

Single-Chip Video Processor

1. Introduction

The entire video processing and controlling for a color
TV has been developed on a single chip in 0.8

�

CMOS

technology. Modular design and submicron technology
allow the economic integration of features in all classes
of TV sets.

Open architecture is the key word to the new DSP gener-
ation. Flexible standard building blocks have been de-
fined that offer continuity and transparency of the entire
system.

One IC contains the entire video and deflection process-
ing and builds the heart of a modern color TV. Its per-
formance and complexity allow the user to standardize
his product development. Hardware and software appli-
cations can profit from the modularity as well as man-
ufacturing, system support or maintenance. The main
features are:

� low cost, high performance

� all digital video processing

� multi-standard color decoder PAL/NTSC/SECAM

� 3 composite, 1 S璙HS input

� integrated high-quality AD/DA converters

� sync and deflection processing

� luminance and chrominance features, e.g.

peaking, color transient improvement

� programmable RGB matrix

� various digital interfaces

� embedded RISC controller (80 MIPS)

� one crystal, few external components

� single power supply 5 V

� 0.8

�

CMOS Technology

� 68-pin PLCC or 64-pin Shrink DIL Package

1.1. System Architecture

Two main modules have been defined:

Video Processor and

Display Processor.

They are designed as silicon building blocks. Their parti-
tioning permits a variety of IC configurations with the aim
to satisfy the particular requirements of different appli-
cations. Both, analog and digital interfaces, support
state of the art TV receivers as well as other environ-
ments. Fig. 1�1 shows the block diagram of the single-
chip Video Processor which consists of both modules.

feature
interface

V2/Y

G
B

20.25
MHz

Hor.
Flyback

H/V
Drive

Analog
RGB

Color Decoder

Display Processor

Sync and Deflection

Clock Gen.

NTSC/PAL/SECAM

2*ADC,

8 bit

�> RGB

Frontend

Backend

3*DAC,

10 bit

3 PLLs, horizontal output, vertical outputs

DCO

Fig. 1�1: VDP block diagram

Fast
Blank

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VDP 3108

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2. Functional Description

2.1. Analog Front End

This block provides the analog interfaces to all video in-
puts and mainly carries out analog-to digital conversion
for the following digital video processing. A block dia-
gram is given in figure 2�1.

Most of the functional blocks in the front end are digitally
controlled (clamping, AGC and clock-DCO). The control
loops are closed by the Fast Processor (`FP') embedded
in the decoder.

2.1.1. Input Selector

Up to four analog inputs can be connected. Three inputs
are for input of composite video or S璙HS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S璙HS carrier璫hrominance signal.
This input is internally biased and has a fixed gain ampli-
fier.

2.1.2. Clamping

The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling ca-
pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid-
eo signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.

2.1.3. Automatic Gain Control

A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/�4.5 dB in 64
logarithmic steps to the optimal range of the ADC .

The gain of the video input stage including the ADC is
213 steps/V for all three standards (PAL/NTSC/SECAM/
Y/C), with the AGC set to 0 dB.

2.1.4. Analog-to-Digital Converters

Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit reso-
lution. An integrated bandgap circuit generates the re-
quired reference voltages for the converters.

The two ADCs are of a 2-stage subranging type.

2.1.5. ADC Range

The ADC input range for the various input signals and
the digital representation is given in table 2�1 and figure
2�2.

2.1.6. Digitally Controlled Clock Oscillator

The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within

�

150 ppm.

output mux

input mux

clamp

level

bias/

DAC

freq.

frequ.

doubler
frequ.
divider

20.25
MHz

DAC

gain

ADC

AGC

reference

generation

ADC

VIN3

level

clamp

+6/�4.5dB

select

Fig. 2�1: Analog front end

VIN2

VIN1

CIN

color

decod-

digital

chro-

digital

CVBS

or Y

sys-

tem

clocks

DVC

�

150

ppm

CVBS/Y

CVBS/

Y/C

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: VDP3108

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: VDP3108