MAS 3528E

PRELIMINARY DATA SHEET

Micronas

Contents

Page

Section

Title

Introduction

1.1.

Features

1.2.

System Application

1.3.

Application Details

Functional Description

2.1.

Overview

2.2.

Architecture

2.3.

DSP Core

2.4.

Internal Program ROM and Firmware

2.5.

RAM and Registers

2.6.

Clock Management

2.7.

Interfaces

2.7.1.

C Control Interface

2.7.2.

S/PDIF-Input Interfaces

2.7.3.

S/PDIF-Output

2.7.4.

Serial Input Interface

2.7.4.1.

Multiline Serial Output

2.7.5.

Frame Synchronization

2.8.

Power-Supply Regions

2.9.

Functional Blocks and Operation

2.9.1.

Power-Up Sequence and Default Operation

2.9.2.

Input Switching

2.9.3.

Standard Selection and Decoding

2.9.4.

Dolby Digital Data Stream

2.9.5.

MPEG Layer-2 Data Stream

2.9.6.

PCM Audio Data

2.9.7.

Deemphasis

2.9.8.

Channel Expander

2.9.9.

Noise Generator

2.9.10.

Post Processing / Bass Management

2.9.10.1.

Extra Stereo Output

2.9.10.2.

Digital Volume

2.9.10.3.

Bass Management

2.9.11.

Output Format Selection

2.9.12.

DTS / S/PDIF Loop-Through

2.9.13.

Output Sampling Rate

2.10.

System Interaction

2.10.1.

Minimum Required Interconnections

2.10.2.

Required Special Modes in the System

2.10.3.

Minimum System Set-Up

Contents, continued

Page

Section

Title

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

Control Interface

3.1.

Start-Up Sequence

3.2.

C Interface Access

3.2.1.

General

3.2.2.

C Registers and Subaddresses

3.2.3.

Conventions for the Command Description

3.2.4.

The Internal Fixed Point Number Format

3.3.

C Control Register (Code 6A

hex

)

3.4.

C Data Register (Codes 68

hex

and 69

hex

) and the MAS 3528E DSP-Command Syntax

3.4.1.

Read Register (Code A

hex

)

3.4.2.

Write Register (Code B

hex

)

3.4.3.

Read Memory (Codes C

hex

and D

hex

)

3.4.4.

Short Read Memory (Codes C4

hex

and D4

hex

)

3.4.5.

Write Memory (Codes E

hex

and F

hex

)

3.4.6.

Short Write Memory (Codes E4

hex

and F4

hex

)

3.4.7.

Default Read

3.5.

Registers

3.6.

Special Memory Locations and User Interface

3.6.1.

Status Interface for Decoding

3.6.2.

Control Interface for Decoding Operation

3.6.3.

Hybrid User Interface Cells

Specifications

4.1.

Outline Dimensions

4.2.

Pin Connections and Short Descriptions

4.3.

Pin Descriptions

4.3.1.

Power Supply Pins

4.3.2.

Control Lines

4.3.3.

General Purpose Input/Output

4.3.4.

Clocking

4.3.5.

Serial Input Interface

4.3.6.

S/PDIF Input Interface

4.3.7.

S/PDIF Output Interface

4.3.8.

Serial Output Interface

4.3.9.

Miscellaneous

4.4.

Pin Configuration

4.5.

Internal Pin Circuits

4.6.

Electrical Characteristics

4.6.1.

Absolute Maximum Ratings

4.6.2.

Recommended Operating Conditions

4.6.2.1.

General Recommended Operating Conditions

4.6.2.2.

Reference Frequency Generation and Crystal Recommendations

4.6.2.3.

Input LevelsV

4.6.3.

Characteristics

4.6.3.1.

General Characteristics

4.6.3.2.

C Characteristics

4.6.3.3.

S/PDIF-Bus Input Characteristics

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

Contents, continued

Page

Section

Title

4.6.3.4.

S/PDIF-Bus Output Characteristics

4.6.3.5.

S Bus Characteristics Input

4.6.3.6.

S Characteristics Output

4.6.4.

Firmware Characteristics

Data Sheet History

References

1. Digital Audio Compression (AC-3), ATSC Standard, Advances Television Systems Committee, James C.

McKinney, Chariman, Dr. Robert Hopkins, Executive Director (Dec. 20, 1995)

2. Dolby Licensee Information Manual: Dolby Digital Consumer Decoder, Issue 3, 1999

License Notice

Dolby-B-NR, Dolby Digital, Dolby Pro Logic, and Dolby Surround Sound are trademarks of Dolby Laboratories.

Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or
any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished
end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a
license from Dolby Laboratories Licensing Corporation before designing such products.

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

Dolby Digital and MPEG-1 Layer-2 Audio Decoder

This datasheet applies to the MAS 3528E version
E7 and following versions.

1. Introduction

The Micronas MAS 3528E is a single-chip Dolby Digi-
tal and MPEG-1 Layer-2 decoder. Together with the
Surround Sound Processor DPL 4519G, it acts as a
complete implementation of a Dolby Digital consumer
decoder. In a television environment, these two inte-
grated circuits are complemented by the Micronas
Multistandard Sound Processor MSP 44x0G which
performs the standard TV sound decoding.

1.1. Features

Two multiplexed S/PDIF, IEC-958, IEC 61937,

AES/EBU, EIA-J CP-340 receivers

Two freely configurable multiplexed serial inputs

Decoders for 5.1-channel Dolby Digital (AC-3) and

MPEG-1 Layer-2

Handling of PCM input format

S/PDIF PCM output or loop-through for all input for-

mats (including DTS)

Optional surround encoding (Lt, Rt) or straight

downmixing to two channels (Lo, Ro)

Multi-channel I

S output

(four stereo data lines or one 8-channel line)

Dynamic range compression

Karaoke downmixing

Delay for center (0

...

5 ms)

Delay for surround (two channels, 0

...

15 ms)

Bandpass-shaped/white-noise generator

Bass management according to Dolby specification

(output configuration 0, 1, 2, 3, and DVD)

C-control

Fig. 11: Block diagram MAS 3528E

Table 11: ICs used for the Dolby Digital System
Solution

Type

Description

MSP 44x0G

Multistandard Sound Processor
with 48 kHz processing

DPL 4519G

Sound Processor for digital and
analog Surround Systems

MAS 3528E

Dolby Digital/MPEG-1 decoder

S/PDIF

Serial In

Clock

PIO

Serial Out

S/PDIF

out

RISC DSP Core

S/PDIF in

Serial inputs

Serial Control

S/PDIF out

I2S output

additional
inputs and outputs

/9+3/

(Dolby Digital,
MPEG-1 Layer-2, PCM)

CLKO

XTO XTI

18.432 MHz

MAS 3528E

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

1.2. System Application

The Micronas Dolby Digital system solution consists of
three dedicated integrated circuits:

The MSP 44x0G is the interface for all TV-sound

and analog input signals. It performs the TV-audio
demodulation including analog stereo, NICAM, and
Wegener Panda decompression. It has four pairs of
audio D/A-converters, two of them including sound
control facilities, and one additional subwoofer D/A-
converter.

The DPL 4519G adds the Dolby Surround Sound

features and has three pairs of audio D/A-convert-
ers, two of them including sound control facilities,
and one additional subwoofer D/A converter.

The MAS 3528E performs the Dolby Digital or

MPEG decoding and has additional functions that
are necessary for the Dolby Digital system.

While the MSP 44x0G is a stand-alone TV-sound solu-
tion, the combination with a DPL 4519G results in a
high-end TV with Dolby Pro Logic functionality.

With the addition of the MAS 3528E, the TV provides
full Dolby Digital/MPEG-1 capabilities.

A combination of the DPL 4519G with the MAS 3528E
is a fully functional Dolby Digital integration for multi-
media applications with a total of seven high-quality
audio D/A-converters.

Fig. 12: Configuration of the Micronas Dolby Digital TV system solution.

S/PDIF out

MAS 3528E

S/PDIF

S/Serial

DVD

DVB

DPL 4519G

MSP 44x0G

Tuner

VCR

L/(Sub)/R or
L/(C)/R

SL/SR

L/(Sub)/R or
L/C/R or C/C

Lt/Rt or Lo/Ro

SCART

SCART
(TV+Stereo)

SCART

1...6 ch

1...8 ch

8 ch

2 ch

1...8 ch

PCM/Dolby Digital
MPEG via I2S Serial

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

1.3. Application Details

Fig. 13: Block diagram of a MAS 3528E in a

television environment with all D/A-converters shown.

PCM

MPEG

AC-3

Noise

Gen.

Input

Buffer

Deemphas

SID*
SII*
SIC*

SID
SII
SIC

Amp./

Osc.

PLL

Synth.

CLKO

Pos

t
Pro

ess

i
ng

Delay

i
nes

ipl.

C/
Sub

Ls
Rs

L
R

Lt
Rt

SOD3
SOD2
SOD1

SOD

SOI

SOC

S-Mode: Multichannel Mode on D0

8 Channels, fs = 32, 44.1 or 48 kHz, 16, 18 ...32 Bit)

2-8 Ch. Input

, R

, L, R,

, S

, C, SUB)

AUDIO_
CL_OUT

6 Channel

Loop-through

Dolby

Pro Logic

Decoder

Bass

Treble

Balance

Volume

D/A

analog

Volume

D/A

analog

Volume

Bass

Treble

Balance

Volume

D/A

Sound-
Process.
Balance
Volume

Bass
Treble
Balance
Volume

D/A

analog

Volume

D/A

analog

Volume

D/A

2-8

Channel

Serial

Input

Demod.

A/D

Configuration Examples

normal

Dolby Digital/

Pro Logic

...
...
...

int

ext

SUB

ext

SUB

ext

int

)

ext

Speaker

Headphone

...

Subw

L, R

C, SUB

SL, SR

, R

int

Subw

int

L, R

C, SUB

SL, SR

, R

int

Subw

int

L,R

Dolby Digital / Pro Logic
Configurations:
Example 1:
- internal L, C, R
- internal woofer for low freq. of

L, (C), R

- ext. Surround speakers S

, S

- ext. Subwoofer for SUB channel
Example 2:
- internal Left and Right used as C
- internal woofer for low freq. of C
- ext. L, R
- ext. Surround speakers S

, S

- ext. Subwoofer for SUB channel

MAS 3528E

Dolby Digital Decoder

S/PDIF OUT

PCM-Format (Lt/Rt or L/R or Lo/Ro)
or Loop through (e.g. DTS)

S/PDIF In 1/2

AC3, MPEG L2
or PCM Format

SCART1

I2S_Out_L/R

Speaker

Headphone

SCART1

SCART2

I2S_Out_L/R

DPL 4519G

ProLogic

MPEG L2 Decoder

Decoder

MSP 44x0G

Multistandard
Sound Processor

SCART4_In

SCART1_In

SIF-IN

I2S_3_L

I2S_3_R

I2S_3_L

I2S_3_R

I2S_3_S

I2S_3_C

I2S_3_SUB

I2S_1_L

I2S_1_R

I2S_2_L

I2S_2_R

1 2 3

I2S_WS3

I2S_CL3

I2S_WS
I2S_CL

18.

432

18.

432

S_Inputs

Dolby Digital: (L

, R

, L, R, S

, S

, C, SUB)

ProLogic: (L

, R

, L, R, C, SubW)

Dol

y D

i
gi

-
S

ound

t
e

18.432 MHz

S-In: Slave

SPDO

I2S_WS3
I2S_CL3

S_Inputs

I2S_3_L

SUB

I2S_1_L
I2S_1_R

I2S_2_L
I2S_2_R

I2S_3_R

I2S_WS
I2S_CL

r
ad

e Mo

l
e

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

2. Functional Description

2.1. Overview

The MAS 3528E is intended for use in high-end con-
sumer audio applications. It receives S/PDIF or serial
data streams and decodes the Dolby Digital (AC-3),
MPEG or PCM-encoded audio formats.

Due to the automatic format detection, no controller
interaction is needed for the standard operation. On
the other hand, the controller has full access to all vital
information contained in the Dolby Digital bit stream.
The choice of different output formats, as defined by
Dolby, guarantees good adaption to various listening
environments.

2.2. Architecture

The hardware of the MAS 3528E consists of a high
performance RISC Digital Signal Processor (DSP) and
appropriate interfaces. Fig. 21 shows a hardware
overview of the IC; Fig. 22 on page 11 shows the
functional aspects.

2.3. DSP Core

The internal processor is a dedicated audio DSP. All
data input and output actions are based on a `non
cycle stealing' background DMA that does not cause
any computational overhead.

Fig. 21: The MAS 3528E architecture

ALU

MAC

Accumulators

Registers

RAM

ROM

S/PDIF
Input
Interface

Serial
Input
Interface

Slave
Interface

Quartz Osc./
Clock Input

System Clock
Synthesizer

Divider

Reference Clock

Processor Clock

SOD3

SOD2

SOD1

SOD

S/PDIF
Output
Interface

PIO
Interface

Parallel
Port

S/PDIF

Serial Audio

Add

i
ti

ona

S d

nes

CLKO

XTO

XTI

18.432 MHz

C-Bus

to controller

Serial Audio

S/PDIF

MAS 3528E

DSP-Core

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

2.4. Internal Program ROM and Firmware

The firmware implemented in the program ROM of the
MAS 3528E provides Dolby Digital decoding including
the required downmixing, output configurations and
delay lines (part of an Implementation of Dolby Digital),
MPEG-1 Layer-2 audio data decompression, handling
of PCM-encoded audio, and loop-through of DTS-for-
mats received via the S/PDIF-input.

For PCM and MPEG-signals, a deemphasis can be
applied to achieve a flat frequency response as
required by Dolby Pro Logic decoders.

On power-on, the DSP starts the firmware in an auto-
matic standard detection mode with the S/PDIF-input
selected. Therefore, only minimal controlling is neces-
sary. In addition, the I

C-interface provides a set of I

instructions that give access to internal DSP-registers
and memory areas.

2.5. RAM and Registers

The DSP-core has access to two RAM-banks denoted
D0 and D1. All RAM-addresses can be accessed in a
20-bit or a 16-bit mode via I

C-bus. For more details,

please refer to Section 3.4.on page 18.

For fast access of internal DSP-states, the processor
core has an address space of 256 data registers (see
Section 3.5. on page 22) which can be accessed via
I

C-bus.

2.6. Clock Management

The MAS 3528E is driven by a single clock at a fre-
quency of 18.432 MHz. The clock may either be pro-
vided from an external source to pin XTI or generated
with a crystal. At pin XTO, the clock signal is available
for other applications.

The internal reference clock and processor clock are
derived from the 18.432 MHz and synchronized to the
audio sample frequency of the decompressed bit
stream by a PLL. In case of Dolby Digital decoding, the
clock frequency may be selected between a high and a
low value by bit[16] in configuration memory cell
UIC_Out_Clk_Scale (D0:13DF) (see Table 37 on
page 31). It is highly recommended to use the high
system clock. The resulting processor clocks are given
in Table 21.

At pin CLKO, a clock output can be provided e.g. for
additional D/A-converters. The output frequency at
CLKO is the reference clock divided by a factor as
selected by bits[18:17] in D0:13DF. By default, CLKO
is disabled.

Table 22: Reference clock frequencies in
dependence of bit[16] of UIC_Out_Clk_Scale
(D0:13DF).

Format

/kHz

Reference Clock/MHz

bit[16] = 0

bit[16] = 1

Dolby
Digital

61.44

73.728

44.1

56.448

67.7376

40.96

49.152

MPEG,
PCM

73.728

44.1

67.7376

49.152

Table 21: Processor clock frequencies in
dependence of bit[16] of UIC_Out_Clk_Scale
(D0:13DF).

Format

/kHz

Processor Clock/MHz

bit[16] = 0

bit[16] = 1

Dolby
Digital

61.44

73.728

44.1

56.448

67.7376

40.96

49.152

MPEG,
PCM

36.864

44.1

33.8688

24.576

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

2.7. Interfaces

2.7.1. I

C Control Interface

For controlling, a standard I

C-interface is imple-

mented. A detailed description of all functions can be
found in Section 3. on page 17.

2.7.2. S/PDIF-Input Interfaces

Two multiplexed S/PDIF-input interfaces are installed
which are capable of PCM, Dolby Digital, MPEG, or
(without decoding) DTS auto-detection. In addition to
the signal input pins SPDI/SPDI2, a reference pin
SPREF is provided to support balanced signal sources
or twisted pair transmission lines. The following fea-
tures are supported:

Fast synchronization on input signal (<50 ms)

Burst-Mode support for Dolby Digital and

MPEG-bitstreams

Locking on 32, 44.1, 48 kHz sample frequencies

Incoming first 20 channel status bits are mirrored in

hex

(see Table 35 on page 22)

2.7.3. S/PDIF-Output

At pin SPDIFOUT, the baseband audio is provided as
an S/PDIF-signal.

Channel status bits in S/PDIF output (especially copy-
right, category code, and generation status) can be
configured in D0:13EA (see Table 37 on page 31).

Alternatively, this output can mirror the unprocessed
signal of the S/PDIF-input (Output_Conf: Register
2E

hex

). This loop-through is necessary for DTS (Digital

Theater System) signals where no internal decoding
action is performed.

2.7.4. Serial Input Interface

If the serial input interface carries Dolby Digital, MPEG
Layer-2, or PCM, the MAS 3528E processes the data.
The interface consists of the three pins: SIC, SII, and
SID. For MPEG and Dolby Digital decoding operation,
the SII pin must always be connected to V

, while for

PCM-data, the interface acts as an I

S-type and SII is

used as a word strobe. An example of an input signal
format is shown in Fig. 416 on page 52. The data val-
ues are latched with the falling edge of the SIC signal.
It is possible to use a word length of 16 or 32 bits. For
controlling details, please refer to memory address
D0:13D0 (I/O Control) and D0:13DF (Auxiliary Inter-
face Control) in Table 37 on page 31.

If the MPEG or Dolby Digital signal was formatted (e.g.
to 8-bit or 16-bit words) by the storing or transportation
medium (PC, memory), the serial data must be sent
"MSB first" as produced by the encoder.

2.7.4.1. Multiline Serial Output

The serial audio output interface of the MAS 3528E is
a standard I

S-like interface consisting of four data

lines SODx, the word strobe SOI, and the clock signal
SOC. The output bitstream can either carry eight chan-
nels on one line (SOD) or two channels on each of four
lines (SOD, SOD1, SOD2, SOD3). Furthermore, it is
possible to choose between different interface configu-
rations (with word strobe time offset and/or with
inverted SOI-signal). The serial output generates 32
bits per audio sample, but only the first 20 bits will
carry valid audio data. The 12 trailing bits are set to
zero by default (see Fig. 418 on page 53).

The configuration of the output interface is done in
D0:13D0 and D0:13DF (see Table 37 on page 31).

2.7.5. Frame Synchronization

For microprocessor interrupts, a frame synchronization
output pin (SYNC) is provided.

After decoding a valid header, the SYNC pin level
changes to High. Most of the status information (UIS
cells in Table 36 on page 23) is updated now. To
generate an edge for the controller, the level changes
to Low during processing the next header. After having
completed this, the SYNC pin level changes to High
again. If the level is Low for more than 1 ms, no decod-
ing is performed. Memory cell UIH_LAST_MESSAGE
(D0:13FF) provides background information thereof.

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

Notes for Dolby Digital:

After first CRC is done, the SYNC pin level changes to
High, all information for a frame is valid, and decoding
is performed. The SYNC pin level changes to Low
before new status information is written. Please take
into account that UIS_DYNRNG (D0:13B4),
UIS_DYNRNG2 (D0:13B5), and UIS_KARAOKEFLAG
(D0:13B6) are valid for the audio block only; the SYNC
pin does not signalize their validity.

Notes for MPEG:

After processing CRC, the SYNC pin level changes to
High, all information for a frame is valid, and decoding
is performed. The SYNC pin level changes to Low
before evaluating new header information.

2.8. Power-Supply Regions

The MAS 3528E has three power supply regions. The
VDD/VSS-pin pair supplies all digital parts including
the DSP-core.The XVDD/XVSS-pin pair is connected
to the signal pin output buffers.The AVDD/AVSS-sup-
ply is for the clock oscillator, PLL-circuits, and system
clock synthesizer.

2.9. Functional Blocks and Operation

A block diagram of the MAS 3528E functionality is
shown in Fig. 22.

2.9.1. Power-Up Sequence and Default Operation

After applying the appropriate voltages to the three
supply pins and releasing the reset signal, the circuit
starts normal operation with the S/PDIF as the
expected input and automatic standard recognition
(Dolby Digital, MPEG, PCM). No further action is nec-
essary for default operation or DTS loop-through.

A power-on reset can be issued at any time via pin
POR.

When the input format is changed (e.g. from Dolby
Digital to MPEG), the synchronization is lost and the
audio output is muted. The automatic standard recog-
nition then checks the new input format and, after suc-
cessful recognition, resumes normal operation.

Fig. 22: Functionality of the MAS 3528E

Input
Buffer

PCM

MPEG
Layer-2

AC-3
Decoder

Dee

Chan

nel

pan

der

sin

l
a

Lt/Rt/
Lo/Ro

L/R

LS/RS

C/SUB

l
t
ip

lex

div

Synthesizer

PLL

Amp./
Oscill.

18.432 MHz

Noise
Generator

Output
Buffers

Buffer Fill
Information

Reference clock

Processor clock

S/PDIF
Inputs

Serial
Inputs

Clock /
Quartz

SOD

SOD1

SOD2

SOD3

S/PDIF

Output

CLKO

MAS 3528E

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

2.9.2. Input Switching

Both input interfaces, the S/PDIF (default

in Fig. 2

2) or the serial input interface, may carry any of the
three data formats: Dolby Digital (AC-3), MPEG Layer-
2, or PCM. The filling status of the input buffer repre-
sents the data rate and therefore controls the system
clock. The input interface can be selected in the
UIC_IO control D0:13D0.

The DTS-format can only be received via the S/PDIF-
interface for loop-through.

2.9.3. Standard Selection and Decoding

In the default mode, an automatic standard recognition
(auto-detection) selects the decoding algorithm
according to the data format at the S/PDIF-input. The
detected standard is shown in the Global Operating
Status (D0:13BB). The standard selection for the I

inputs can be selected manually in the I/O control
D0:13D0

2.9.4. Dolby Digital Data Stream

The digital input signal can either be an S/PDIF or an
I

S-source. In the Dolby Digital mode, the IC performs

the following tasks:

Data input with clock synchronization

S/PDIF-channel selection (one of eight possible)

Decoding of AC-3 bitstream elements

Compression control for Dolby Digital signals

(D0:13D7...13D9)

Output mode control

Dolby Bass Management

Center and surround delays

Level adaption

If the signal source is the S/PDIF-input, the controller
may select one of eight content channels depending
on availability (D0:13BC). The respective service infor-
mation is displayed in cell Bit Stream Mode (D0:13A2).

The bit stream elements contain all necessary informa-
tion required to correctly handle the audio. All ele-
ments important for controller actions are displayed in
the status memory (see Table 36 on page 23).

The MAS 3528E decodes all Dolby Digital formats
from 1 to 5.1 audio channels. Accordingly, one to six of
the output channels are used for the decoded audio.
The output mode is selected in D0:13D6. An additional
downmix pair can either be Dolby Surround encoded
(Lt, Rt) or plain stereo (Lo, Ro; D0:13DE).

If the Dolby Digital input only contains a stereo pair,
the controller must recognize this (Dolby Surround
Mode; D0:13A6) and should activate an external Pro
Logic decoder (e.g. in the DPL 4519G).

2.9.5. MPEG Layer-2 Data Stream

In the MPEG mode a valid MPEG-1 Layer-2 data sig-
nal is expected. The steps for decoding are

Clock synchronization to data input

S/PDIF-channel selection (one of eight possible)

Side information extraction

Audio data decompression

Optional deemphasis

Digital volume

If the signal source is the S/PDIF-input, the controller
may select one of eight content channels depending
on availability (D0:13BC).

2.9.6. PCM Audio Data

PCM-data are received via S/PDIF or I

S. Sampling

frequency will be detected automatically and mirrored
in D0:13A0 (UIS_FS_CODE).

If the PCM-data are received via I

S-bus, the

MAS 3528E expects a valid wordstrobe, and I/O-con-
trol (D0:13D0) has to be set as described in Table 37.
In this case the deemphasis must be activated by the
controller if necessary.

2.9.7. Deemphasis

For the PCM- and MPEG-formats a deemphasis can
be applied to the signal

(D0:13E0). This is neces-

sary because the possibly following Dolby Pro Logic
encoding requires a flat audio frequency response. For
MPEG-encoded audio and via S/PDIF transmitted
PCM, this block is activated automatically. For proper
operation of PCM signals via I

S, the controller has to

determine whether the PCM signals have been pre-
emphasized or not.

2.9.8. Channel Expander

The outputs of the PCM/MPEG-decoders consist of
two channels each; the output of the Dolby Digital
decoder may have any number between one and six
(5.1) channels. To unify the output format between dif-
ferent modes the audio is always mapped to six chan-
nels

{

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

2.9.9. Noise Generator

A bandpass-shaped or white noise signal can be
routed to any combination of the six main output chan-
nels

{

. The required channel sequence must be done

by the controller in D0:13D1.

There is no noise signal available at the Extra Stereo
Output.

2.9.10. Post Processing / Bass Management

The implemented post processing functions

can be

applied to the following audio formats. They are

Downmixing to Lo/Ro or surround sound encoding

to Lt/Rt (D0:13DE) for Dolby Digital multichannel
signals

Mixing and digital filtering for the different Output

and Bass configurations according to the Dolby Dig-
ital Licensee Information Manual (D0:13D5,
D0:13D6, D0:13DA)

Digital volume control (D0:13E1...13E8) for all audio

formats

Appropriate delay lines for center and surround

channels (D0:13D2...13D4) for Dolby Digital multi-
channel signals

2.9.10.1. Extra Stereo Output

For headphone and VCR-recordings, a downmixed
output is provided that may be switched from Lt/Rt
(surround encoded, default) to Lo/Ro (headphone
encoded)

}

Both, the 6-channel output and the Extra Stereo Out-
put ± are routed to the serial data output interface ð.

Note: In order to prevent clipping due to the downmix-
ing in the Custom and Line Modes, the High-Level Cut
Compression Scale Factor (D0:13D8) must always be
left at 7FFFF

hex

when the Extra Stereo Output is used

in conjunction with non-downmixed channels
(D0:13D6).

2.9.10.2. Digital Volume

The digital volume control provided is mainly intended
for balancing purposes and initially set to 0 dB. Vol-
ume control, output configuration, and delays should
be set by the controller according to the actual listen-
ing situation.

2.9.10.3. Bass Management

Generally, not all of the five loudspeakers in a Dolby
Digital system can reproduce the full audio bandwidth.
Bass Management allows redirecting low frequencies
to loudspeakers which are capable of reproducing this
frequency range.

The MAS 3528E supports the following Bass Manage-
ment modes:

Bass Management mode 0 (D0:13DA = 8)

Attenuation of

15 dB in the SUB channel should be

compensated by a 15 dB gain in the D/A-converter.

Fig. 23: Bass Management configuration 0

Bass Management mode 1 (D0:13DA = 9)

Attenuation of

15 dB in the SUB channel should be

compensated by a 15 dB gain in the D/A-converter.

Fig. 24: Bass Management configuration 1

15 dB

5 dB

LFE

SUB

15 dB

5 dB

LFE

SUB

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

Bass Management mode 2 (D0:13DA = A

hex

)

Level adjustment is implemented with

12 db.

Fig. 25: Implementation of configuration 2

Bass Management mode 3 (D0:13DA = B

hex

)

Fig. 26: Alternative implementation of

configuration 2

Bass Management mode 4 (D0:13DA = C

hex

)

Fig. 27: Implementation of configuration 3

Bass Management mode 5 (D0:13DA = D

hex

)

The analog part of SUB should add a +10 db gain

Fig. 28: Implementation of configuration three with

subwoofer

Bass Management mode 6 (D0:13DA = E

hex

)

Fig. 29: Simplified Bass Management for

Multichannel Source Products (I)

Bass Management mode 7 (D0:13DA = F

hex

)

Fig. 210: Simplified Bass Management for

Multichannel Source Products (II)

Level

Adj

Level

Adj

Level

Adj

12 dB

15 dB

5 dB

LFE

SUB

1.5 dB

LFE

SUB

15 dB

5 dB

LFE

SUB

4.5 dB

LFE

SUB

4.5 dB

LFE

SUB

5 dB

4,5 dB

LFE

10.5 dB

5 dB

SUB

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

2.9.11. Output Format Selection

The output is an I

S-bus format with either eight audio

channels on one line (default) or two audio channels
on each of four lines (

, D0:13D0). If the 4x2-configu-

ration is selected, the clock and word strobe lines SOC
and SOI apply to all four data lines SOD...SOD3. Clock
and word strobe signals can be configured to different
standards (polarity, delay). The data word length is
always 32 bits.

In the 1x8 format, the output data are in the following
order:
L, LS, C, Lt/Lo, R, RS, Sub, Rt/Ro.

2.9.12. DTS / S/PDIF Loop-Through

An incoming DTS signal (via S/PDIF) will be reflected
in UIS_GOS (D0:13BB).

By default, a recognized DTS signal is looped-through.
This means that the signal at S/PDIF input is routed to
S/PDIF output without processing regardless of bit 1
in register 2E

hex

This automatism can be disabled by setting bit 12 in
register 2E

hex

to "1". Now, the controller is to choose

via bit 1 whether a PCM audio signal is output (in case
of a DTS signal the output is muted) or whether the
input data is looped-through.

2.9.13. Output Sampling Rate

The internally generated system clock is derived from
the filling status of the input data buffer by a PLL

This clock is synchronous to the original sampling rate
and is used throughout the complete data processing.
Except in the ambiguous case of PCM-data at the
serial audio input where the original sampling rate
must be defined (D0:13DB), no controller interaction is
needed for clock operation.

The output sampling rate is 32 kHz, 44.1 kHz, or
48 kHz, depending on the source.

Since in the Micronas Dolby Digital TV sound solution
all further signal processing is on a rate of 48 kHz, the
input stage of the DPL 4519G performs the sample
rate conversion if necessary.

2.10. System Interaction

2.10.1. Minimum Required Interconnections

The MAS 3528E requires the following connections for
normal operation:

Power supply with adequate blocking capacitors

(VDD, VSS, AVDD, AVSS, XVDD, XVSS)

Crystal with capacitors or clock input (XTI, XTO)

C-bus and reset-line (I2CC, I2CD) and reset line

(POR) for controlling

S/PDIF-input (SPDI/SPDI2, SPREF) or serial/I

S-

input (SID, SIC, SII or SID*, SIC*, SII*). In the stan-
dard Micronas-solution, the I

S-signal comes from

the MSP 44x0G

S-output (SOD, SOC, SOI). In the standard config-

uration, this signal is fed to the DPL 4519G.

Please refer to Fig. 420 on page 55 or to the applica-
tion kit for details.

2.10.2. Required Special Modes in the System

The MAS 3528E interfaces require no configuration.
The I

S outputs and inputs of the Dolby Pro Logic IC

DPL 4519G and the MSP 44x0G, however, must be
configured to send/accept the 8-channel multiplexed
digital PCM-data stream.

The DPL 4519G may generate up to seven analog sig-
nals (three pairs plus subwoofer). Further audio sig-
nals can be forwarded to the MSP 44x0G for D/A-con-
version.

Dolby Pro Logic encoded audio originating from the
MSP 44x0G (TV-sound) must be routed through the
MAS 3528E to the DPL 4519G for further processing.

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

2.10.3.Minimum System Set-Up

The following I

C-command sequence is necessary for

the DPL 4519G:

C-controlled reset

Write MODUS Register (set I

S-input to slave

mode)

Write I2S_CONFIG (multi sample mode, 32 bits,

clock to 8*32 bits)

Set I2S3 Resorting Matrix to "left/right eight

MAS 3528E". The signal pairs are now in the follow-
ing order: Lt/Rt, L/R, SL/SR, C/Sub

Select first I

S3-input pair as source for I

S Output

(because of 8*32-bit mode all 4*2 channels will be
looped through to the MSP 44x0G) and set to trans-
parent stereo

Select one input pair as source for Loudspeaker

Output (numbers 7...10 mean first...fourth pair)

Select one input pair as source for Aux Output

(numbers 7...10 mean first...fourth pair)

Set volume control for Loudspeaker Output

Set volume control for Aux Output

If a Multistandard Sound Processor is present in the
system, similar set-up commands are required. For
further details, please refer to the DPL 4519G or the
MSP 44x0G data sheets.

If both devices are used on the same I

C-bus, the

device addresses must be set to different values by
hardware means.

The D/A-conversion of audio signals may be freely
appointed between the DPL 4519G and the
MSP 44x0G. For an example, please refer to Table 2
4.

Table 23: Output configuration matrix. All registers are at I

C-subaddress 12

hex

of the respective device. Note that

only one code per register applies.

Device

DPL 4519G

MSP 44x0G

Register

Signal Pair

Loudsp.
00 08

hex

Aux
00 09

hex

SCART1
00 0A

hex

Loudsp.
00 08

hex

Aux
00 09

hex

SCART1
00 0A

hex

SCART2
00 41

hex

Lt/Rt (Lo/Ro)

07 20

hex

07 20

hex

07 20

hex

07 20

hex

07 20

hex

07 20

hex

07 20

hex

L/R

08 20

hex

08 20

hex

08 20

hex

08 20

hex

08 20

hex

08 20

hex

08 20

hex

SL/SR

09 20

hex

09 20

hex

09 20

hex

09 20

hex

09 20

hex

09 20

hex

09 20

hex

C/Sub

0A 20

hex

0A 20

hex

0A 20

hex

0A 20

hex

0A 20

hex

0A 20

hex

0A 20

hex

Use 0A 20

hex

for C/Sub output, 0A 00

hex

for Center signal on both outputs, 0A 10

hex

for Sub signal on both outputs

Table 24: Example: In the DPL 4519G use both loudspeaker output channels for center, the auxiliary output for
surround, the SCART1 output for Lt/Rt. In the MSP 44x0G use the loudspeaker output for L/R, both auxiliary output
channels for Sub and the SCART1 output for an additional Lt/Rt-signal.

Device

DPL 4519G

MSP 44x0G

Register

Signal Pair

Loudsp.
00 08

hex

Aux
00 09

hex

SCART1
00 0Aa

hex

Loudsp.
00 08

hex

Aux
00 09

hex

SCART1
00 0A

hex

SCART2
00 41

hex

Lt/Rt (Lo/Ro)

07 20

hex

07 20

hex

L/R

08 20

hex

SL/SR

09 20

hex

C/Sub

0A 00

hex

0A 10

hex

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

3. Control Interface

3.1. Start-Up Sequence

After power-up and a reset (see Section 3.3. on
page 18), the IC is in its default state (see Table 37
on page 31). The controller has to initialize all memory
cells for which a non-default setting is necessary.

3.2. I

C Interface Access

3.2.1. General

Control communication with the MAS 3528E is done
via an I

C slave interface. The device addresses are

hex

(write) and 3B

hex

(read) as shown in Table 31.

C clock synchronization is used to slow down the

interface if required.

3.2.2. I

C Registers and Subaddresses

The interface uses one level of subaddresses. The
MAS 3528E interface has 3 subaddresses allocated
for the corresponding I

C-registers.

The address 6A

hex

is used for basic control, i.e. reset

and task select. The other addresses are used for data
transfer from/to the MAS 3528E.

The I

C-control and data registers of the MAS 3528E

are 16 bits wide, the MSB is denoted as bit [15]. Trans-
missions via I

C-bus have to take place in 16-bit words

(two byte transfers, MSB sent first); thus for each reg-
ister access two 8-bit data words must be
sent/received via I

C-bus.

3.2.3. Conventions for the Command Description

The description of the various controller commands
uses the following formalism:

Abbreviations used in the following descriptions:

address

data value

count value

offset value

don't care

A data value is split into 4-bit nibbles which are

numbered zero-bound.

Data values in nibbles are always shown in hexa-

decimal notation.

A hexadecimal 20-bit number d is written, e.g. as

d = 17C63

hex

, its five nibbles are

d0 = 3

hex

, d1 = 6

hex

, d2 = C

hex

, d3 = 7

hex

, and

d4 = 1

hex

Variables used in the following descriptions:

dev_write

hex

device write

dev_read

hex

device read

data_write

hex

data register write

data_read

hex

data register read

control

hex

control register write

Bus signals

Start

Stop

ACK = Acknowledge

NAK = Not acknowledge

W Wait = I

C clock line is held low while the

MAS 3528E is processing the current
I

C command

Symbols in the telegram examples

Start Condition

Stop Condition

data byte

ignore

All telegram numbers are hexadecimal, data origi-
nating from the MAS 3528E are shown in gray.
Example:

<3A 68 dd dd>

write data to DSP

<3A 69 <3B

dd dd

read data from DSP

Fig. 31 shows I

C bus protocols for read and write

operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with the read command (3B

hex

). Fields with

signals/data originating from the MAS 3528E are
marked by a gray background. Note that in some
cases, the data reading process must be concluded by
a NAK condition.

Table 31: I

C device address

W/R

0/1

Table 32: Subaddresses

Sub-
address

C-

Register

Function

hex

data

Controller writes to
MAS 3528E data register

hex

data

Controller reads from
MAS 3528E data register

hex

control

Controller writes to
MAS 3528E control register

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

Fig. 31: I

C bus protocol for the MAS 3528E (MSB first; data must be stable while clock is high)

3.2.4. The Internal Fixed Point Number Format

In the following sections, two number representations
are used: The fixed point notation `v' and the 2's com-
plement number notation `r'.

The conversion between the two forms of notation is
easily done (see the following equations).

r = v*524288.0+0.5; (

1.0

v < 1.0)

(EQ 1)

v = r/524288.0; (

524288 < r < 524287)

(EQ 2)

3.3. I

C Control Register (Code 6A

hex

)

The I

C control register is a write-only register. Its

main purpose is the software reset of the MAS 3528E.
The software reset is done by writing a 16-bit word to
the MAS 3528E with bit 8 set. The four least significant
bits are reserved for task selection. In standard Dolby
Digital/MPEG-decoding, these bits must always be set
to 0.

3.4. I

C Data Register (Codes 68

hex

and 69

hex

) and

the MAS 3528E DSP-Command Syntax

The DSP-core of the MAS 3528E has two RAM-banks
denoted D0 and D1. The word size is 20 bits. All RAM-
addresses can be accessed in a 20-bit or a 16-bit
mode via I

C-bus. For fast access of internal DSP-

states, the processor core also has an address space
of 256 data registers. All register and RAM-addresses
are given in hexadecimal notation.

The control of the DSP in the MAS 3528E is done via
the I

C data register by using a special command syn-

tax. These commands allow the controller to access
the DSP-registers and RAM-cells and thus monitor
internal states, set the parameters for the DSP-firm-
ware, control the hardware, and even provide a down-
load of alternative software modules.

The DSP-commands consist of a "Code" which is sent
to I

C-data register together with additional parame-

ters.

The MAS 3528E firmware scans the I

C interface peri-

odically and checks for pending or new commands.
The commands are then executed by the DSP during
its normal operation without any loss or interruption of
the incoming data or outgoing audio data stream.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms. However, the typical response
time is less than 0.5 ms. Table 34 on page 19 shows
the basic controller commands that are available by
the MAS 3528E.

high data word

low data word

Example: I2C write access

SDA

SCL

1
0

dev_read (3B

hex

)

Example: I

C read access

dev_write (3A

hex

)

data_read (69

hex

)

dev_write (3A

hex

)

data_write (68

hex

)

high data word

low data word

W = Wait
A = 0 - Acknowledge (Ack)
N = 1 - Not Acknowledge (NAK)
S = Start
P = Stop

Table 33: Control register bit assignment1)

1) x = don't care, R = reset, T3...T0 0 task selection

dev_write

control

d3,d2

d1,d0

...

dev_write

data_write

Code,...

...,...

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

Table 34 gives an overview of the different com-
mands which the DSP-core may receive. The "Code"
is always the first data nibble transmitted after the
"data_write" byte. A second auxiliary code nibble is
used for the short memory access commands.

Because of the 16-bit width of the I

C-data register, all

actions always transmit telegrams with multiples of 16
data bits.

Table 34: Basic controller command codes

Code
(hex)

Command

Function

Read from register

Controller reads an internal register of the MAS 3528E.

Write to register

Controller writes an internal register of the MAS 3528E.

Read D0 memory

Controller reads a block of the DSP memory.

Read D1 memory

Controller reads a block of the DSP memory.

Write D0 memory

Controller writes a block of the DSP memory.

Write D1 memory

Controller writes a block of the DSP memory.

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

3.4.1. Read Register (Code A

hex

)

The MAS 3528E has an address space of 256 DSP-
registers. Some of the registers (r = r1,r0 in the figure
above) are direct control inputs for various hardware
blocks, others control the internal program flow. In
Section 3.5. on page 22, the registers of interest with
respect to the Dolby Digital/MPEG-decoding firmware
are described in detail. In contrast to memory cells,
registers cannot be accessed as a block but must
always be addressed individually.

Example:
Read the content of register (2E

hex

<3A 68 A2 E0>

define register

<3A 69 <3B

xx xd dd dd

and read

3.4.2. Write Register (Code B

hex

)

The controller writes the 20-bit value
(d = d4,d3,d2,d1,d0) into the MAS 3528E register
(r = r1,r0). A list of registers is given in Section 3.5. on
page 22

Example: Disable automatic S/PDIF loop-through for
DTS by writing the value 1000

hex

into the register with

the number 2E

hex

<3A 68 B2 E0 10 00>

3.4.3. Read Memory (Codes C

hex

and D

hex

)

The MAS 3528E has 2 memory areas called D0 and
D1. Both areas have different read and write com-
mands. The memory areas D0 can be read by using
the codes C

hex

The Read D0 Memory command gives the controller
access to all 20 bits of D0-memory cells of the
MAS 3528E. The telegram to read three words starting
at location D0:100 is

<3A 68 C0 00 00 03 01 00>
<3A 69 <3B

xx xd dd dd

The Read D1 Memory command (D

hex

)is provided to

get information from D1 memory cells of the
MAS 3528E.

3.4.4. Short Read Memory (Codes C4

hex

and D4

hex

)

Because most cells in the Dolby Digital user interface
are only 16 bits wide, it is faster and more convenient
to access the memory locations with a special 16-bit
mode for reading:

This command is similar to the normal 20-bit read
command and uses the same command codes C

hex

and D

hex

for D0 and D1-memory, respectively, how-

ever, it is followed by a 4

hex

rather than a 0

hex

1) send command

2) get register value

dev_write

data_write

A,r1

r0,0

dev_write

data_read

dev_read

d3,d2

d1,d0

x,d4

x,x

dev_write

data_write

B,r1

r0,d4

d3,d2

d1,d0

1) send command (e.g. Read D0)

2) get memory value

dev_write

data_write

C,0

0,0

dev_write

data_read

dev_read

n3,n2

n1,n0

a3,a2

a1,a0

....repeat for n data values....

d3,d2

d1,d0

x,d4

x,x

d3,d2

d1,d0

x,d4

x,x

1) send command (e.g. Short Read D0)

2) get memory value

dev_write

data_write

C,4

0,0

dev_write

data_read

dev_read

n3,n2

n1,n0

a3,a2

a1,a0

....repeat for n data values....

d3,d2

d1,d0

d3,d2

d1,d0

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

The Short Read D1 Memory command works similarly
to the Read D1 Memory command but with the code
D

hex

followed by a 4

hex

Example: Read 16 bits of D1:123 has the following I

protocol:

<3A 68 D4 00

read 16 bits from D1

00 01

one word to be read

01 23>

start address

<3A 69 <3B

dd dd

start reading

3.4.5. Write Memory (Codes E

hex

and F

hex

)

The memory areas D0 and D1 can be written by using
the codes E

hex

and F

hex

, respectively.

With the Write D0/D1 Memory command n 20-bit
memory cells in D0/D1 can be initialized with new
data.

Example: Write 80234

hex

to D0:FFB has the following

C protocol:

<3A 68 E0 00

write D0 memory

00 01

1 word to write

0F Fb

start address FFB

hex

00 08

value = 80234

hex

02 34>

3.4.6. Short Write Memory (Codes E4

hex

and F4

hex

)

For faster access, only the lower 16 bits of each mem-
ory cell are accessed. The four MSBs of the cell are
cleared. The command uses the same codes E

hex

and

hex

for D0/D1 as for the 20-bit command but followed

by a 4 rather than a 0.

3.4.7. Default Read

The Default Read command is the fastest way to get
information from the MAS 3528E. Executing the
Default Read in a polling loop can be used to detect a
special state during decoding.

The Default Read command immediately returns the
lower 16 bit content of a specific RAM location as
defined by the pointer D0:FFB. The pointer must be
loaded before the first Default Read action occurs. If
the MSB of the pointer is set, it points to a memory
location in D1 rather than to one in D0.

Example: For watching D1:123, the pointer D0:FFB
must be loaded with 8123

hex

<3A 68 E0 00

write to D0 memory

00 01

one word to write

0F Fb

start address FFB

00 08

value = 8

hex

...

01 23>

...0123

hex

Now the Default Read commands can be issued as
often as desired:

<3A 69 <3B

Default Read command

dd dd

16 bit content of the

address as defined by the
pointer

<3A 69 <3B

dd dd

... and do it again

dev_write

data_write

E,0

0,0

n3,n2

n1,n0

a3,a2

a1,a0

d3,d2

d1,d0

d3,d2

d1,d0

....repeat for n data values....

0,0

0,d4

0,0

0,d4

e.g. Write D0

dev_write

data_write

E,4

0,0

n3,n2

n1,n0

a3,a2

a1,a0

d3,d2

d1,d0

d3,d2

d1,d0

....repeat for n data values....

e.g. Short Write D0

data_read

dev_read

d3,d2

d1,d0

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

3.5. Registers

In Table 35, the internal registers that are useful for
controlling the MAS 3528E are listed. They are acces-
sible by Read/Write Register I

C commands (see

Section 3.4.1. and Section 3.4.2. on page 20).
Note: Registers not given in this table must not be
written.

Table 35: Command Register Table

R/W

Function

Default
(hex)

Name

R/W

Loop-through and Sync Pin Controlling

bit[12]

0: automatic active loop-through if DTS is

recognized or the input format at
S/PDIF_in cannot be determined
(default)

1: bit[1] controls

loop-through

bit[11:2]

reserved: do not change!

bit[1]

0: normal operation
1: connect SPDI_in to SPDIF OUT

(loop-through)

bit[0]

sync bit (will be automatically detected and
set by internal software)

00000

Output_Conf

PIO Configuration

Configuration of pins must be zero.

00000

PIO_Config

PIO Data Input

The input level of every PI pin in the input mode can be
read out of this register; the bit number corresponds to
the PI number.

bit[n]

0: input is low

bit[n]

1: input is high

PIO_Data_In

PIO Data Output

The output level of every PI pin in the output mode can
be defined by this register; the bit number corresponds to
the PI number.

bit[n]

0: output is low

bit[n]

1: output is high

PIO_Data_Out

R/W

PIO Direction

Every bit switches the PI pin with the corresponding num-
ber from input to output.

bit[n]

0: input mode

bit[n]

1: output mode

bit[14:16]

must be zero if PI14, PI15, and PI16 are
used as alternative inputs SID*, SII*, and
SIC*.

00000

PIO_Direction

Incoming S/PDIF Channel Status Bits

bit[19:0]

mirrors first 20 channel status bits

SPI0CS

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

3.6. Special Memory Locations and User Interface

Operation of the DSP and the interfaces can be
observed and controlled via the memory locations of
the user interface. These memory cells are located at
the high end of the D0-RAM.

Status cells are written by the DSP and read by the
controller, configuration cells are written by the control-
ler and read by the DSP, hybrid cells can be written
and read by either side.

Note: Memory addresses not given in this table
must not be accessed.

3.6.1. Status Interface for Decoding

The following table contains the memory locations of
the firmware status information. Addresses are hexa-
decimal, memory cell content is binary when written
without indicator and hexadecimal when written with a
hex-suffix.

Table 36: Status memory cells

Memory
Address
(hex)

Function

Mode

Name

D0:13A0

Sample Rate of Input Bitstream

Dolby Digital

(Table 5.1 of ATSC Spec. A/52)

MPEG

PCM

bit[1:0]

48 kHz

44.1 kHz

32 kHz

not detected (default)

UIS_FSCOD

D0:13A1

Bit Stream Identification (bsid)

Dolby Digital

(Section 5.4.2.1 of ATSC Spec. A/52)

bit[4:0]

hex

...1f

hex

current bsid value

Bit streams that have a bsid higher than the decoder's version number may be
incompatible. In this case, the decoding is inhibited. The version number for
the implemented firmware is 8.

UIS_BSID

D0:13A2

Bit Stream Mode (bsmod)

Dolby Digital

(Table 5.2 of ATSC Spec. A/52)

bit[2:0]

000

main audio service: complete main (CM)

001

main audio service: music and effects (ME)

010

associated service: visually impaired (VI)

011

associated service: hearing impaired (HI)

100

associated service: dialogue (D)

101

associated service: commentary (C)

110

associated service: emergency (E)

111

acmod = 001, associated service: voice over (VO)

111

acmod = 010-111, main audio service: karaoke

This information is valid after selecting (D0:13D0) an available (D0:13BC)
channel (data stream) from the S/PDIF-input. Prior to this, the bsmod can be
directly derived from the Pc-preambles of the S/PDIF-data (D0:13BD...13C4).

UIS_BSMOD

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13A3

Audio Coding Mode (acmod)

Dolby Digital

(Table 5.3 of ATSC Spec. A/52)

bsmod != '111' bsmod = '111' (Karaoke)

bit[2:0]

000

1+1

Ch1, Ch2

Voice Over (VO)

001

1/0

010

2/0

L, R

011

3/0

L, C, R

L, M, R

100

2/1

L, R, S

L, R, V1

101

3/1

L, C, R, S

L, M, R, V1

110

2/2

L, R, SL, SR

L, R, V1, V2

111

3/2

L, C, R, SL, SR L, M, R, V1, V2

For user information: indicates the applied main channel.

UIS_ACMOD

D0:13A4

Center Mix Level (cmixlev)

Dolby Digital

(Table 5.4 of ATSC Spec. A/52)

bit[1:0]

0.707 (

3.0 dB)

0.595 (

4.5 dB)

0.500 (

6.0 dB)

reserved (

6.0 dB),

nominal downmix level of center with
respect to left and right channels

Used in the internal algorithm.

UIS_CLEV

D0:13A5

Surround Mix Level (surmixlev)

Dolby Digital

(Table 5.5 of ATSC Spec. A/52)

bit[1:0]

0.707 (

3.0 dB)

0.500 (

6.0 dB)

reserved (

6.0 dB),

nominal downmix level of surround channels

Used in the internal algorithm.

UIS_SLEV

D0:13A6

Dolby Surround Mode (dsurmod)

Dolby Digital

(Table 5.6 of ATSC Spec. A/52)

bit[1:0]

not indicated

not Dolby Surround encoded

Dolby Surround encoded

reserved (not indicated)

As soon as the audio is Dolby Surround encoded, the controller must activate
the Dolby Pro Logic decoder (e.g. in the DPL 4519G) without any user interac-
tion.

UIS_DSURMOD

D0:13A7

Low Frequency Effects Channel (lfeon)

Dolby Digital

(Section 5.4.2.7 of ATSC Spec. A/52)

bit[0]

LFE off

LFE on

The user may want to choose a different output configuration depending on
the availability of the LFE.

UIS_LFEON

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

D0:13A8

Dialogue Nomalization (dialnorm)

Dolby Digital

(Section 5.4.2.8 of ATSC Spec. A/52)

bit[4:0]

hex

...

average dialog level

1 dB...

31 dB below

hex

100% digital

hex

reserved

Used in the internal algorithm.

UIS_DIALNORM

D0:13AA

Language Code (langcode, langcod)

Dolby Digital

(Sections 5.4.2.11 and 5.4.2.12 of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

langcode = 0 (langcod nonexistent in stream)

bit[7:0]

langcod

The controller may check all S/PDIF-data streams (channels) for the desired
language.

UIS_LANGCOD

D0:13AB

Mixing Level and Room Type

Dolby Digital

(audprodie, mixlevel, roomtyp)
(Sections 5.4.2.13, 5.4.2.14 and 5.4.2.15 of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

audprodie = 0 (mixlevel, roomtyp nonexistent in
data stream)

bit[6:2]

mixlevel

bit[1:0]

roomtyp

For user information.

UIS_MIXLEVEL_
ROOMTYP

D0:13AC

Dialogue Nomalization 2 for Dual Mono Mode 1+1

Dolby Digital

(dialnorm2)
(Section 5.4.2.16 of ATSC Spec. A/52)

bit[4:0]

hex

...1F

hex

average dialog level

1dB...

31dB

below 100% digital

hex

reserved

Used in the internal algorithm.

UIS_DIALNORM2

D0:13AE

Language Code 2 for Ch2 in

Dolby Digital

Dual Mono Mode 1+1 (langcod2e, langcod2)
(Section 5.4.2.19 and 20 of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

langcod2e = 0 (langcod2 nonexistent in stream)

bit[7:0]

langcod2

Used in the internal algorithm.

UIS_LANGCOD2

D0:13AF

Mixing Level and Room Type for Ch2 in

Dolby Digital

Dual Mono Mode 1+1 (audprodi2e, mixlevel2, roomtyp2)
(Section 5.4.2.21, 22 and 23 of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

audprodi2e = 0 (mixlevel2, roomtyp2 nonexistent
in stream)

bit[6:2]

mixlevel2

bit[1:0]

roomtyp2

For user information.

UIS_MIXLEVEL2_
ROOMTYP2

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13B0

Copyright Bit (copyrightb)

Dolby Digital

(Section 5.4.2.24of ATSC Spec. A/52)

bit[0]

not protected

protected by copyright

UIS_COPYRIGHT
B

D0:13B1

Original Bit Stream (origbs)

Dolby Digital

(Section 5.4.2.25 of ATSC Spec. A/52)

bit[0]

copy of a bit stream

original bit stream

UIS_ORIGBS

D0:13B2

Time Code 1

Dolby Digital

(Section 5.4.2.27of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

timecod1e = 0 (time code 1 nonexistent)

bit[13:0]

time code 1(first half)

bit[13:9]

time in hours (0...23 valid)

bit[8:3]

time in minutes (0...59 valid)

bit[2:0]

time in 8-second increments (0 = 0 seconds)

(1 = 8 seconds)
:
(7 = 56 seconds)

For external synchronization purposes.

UIS_TIMECOD1

D0:13B3

Time Code 2

Dolby Digital

(Section 5.4.2.28of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

timecod2e = 0 (time code 2 nonexistent)

bit[13:0]

time code 2 (second half)

bit[13:11]

time in 8-second increments, see time code 1

bit[10:6]

time in frames (0...29 valid)

bit[5:0]

time in 1/6 frames

For external synchronization purposes.

UIS_TIMECOD2

D0:13B4

Dynamic Range Gain Word (dynrnge, dynrng)

Dolby Digital

(Section 5.4.3.3 and 5.4.3.4 of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

dynrnge = 0 (dynrng nonexistent in stream)

bit[7:0]

current dynrng value

Used in the internal algorithm.

UIS_DYNRNG

D0:13B5

Dynamic Range Gain Word 2 for Ch2 in

Dolby Digital

dual mono mode (dynrng2e, dynrng2)
(Section 5.4.3.5 and 5.4.3.6 of ATSC Spec. A/52)

bit[15:0]

FFFF

hex

dynrng2e = 0 (dynrng2 nonexistent in stream)

bit[7:0]

current dynrng value

Used in the internal algorithm.

UIS_DYNRNG2

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

D0:13B6

Karaoke Flag

Dolby Digital

bit[0]

no Karaoke info in bit stream

Karaoke info in bit stream

UIS_
KARAOKEFLAG

D0:13B7

Frame Count

Dolby Digital, MPEG

bit[19:0]

counts 0, 1, 2, 3, 4, ..., 1048575 (= FFFFF

hex

), 1, ...

UIS_FRAME_
COUNTER

D0:13B8

MPEG Header Bits 12...31

MPEG

bit[19]

ID (must be 1 for MPEG-1)

bit[18:17]

Layer

reserved

Layer 3

Layer 2

Layer 1

bit[16]

Protection

CRC

no CRC

bit[15:12]

bit rate (see table in IEC 11172-3, Layer 2)

hex

free

112

128

160

192

224

256

320

384

forbidden

bit[11:10]

sampling frequency (MPEG-1 Layer-2)

44.1 kHz

48 kHz

32 kHz

reserved

...

UIS_MPEG_
HEADER

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13B8

(continued)

bit[9]

padding bit

bit[8]

private bit

bit[7:6]

Mode

stereo

joint stereo

dual channel

reserved

bit[5]

Joint Stereo Mode Extension ms_stereo

off

bit[4]

Joint Stereo Mode Extension Intensity Stereo

off

bit[3]

not protected

protected

bit[2]

Original/Copy

copy

original

bit[1:0]

Emphasis

none

50/15 µs

reserved

CCITT J.17

D0:13B9

MPEG Status

MPEG

bit[5]

mono

stereo

bit[4]

CRC error

bit[3:2]

other decoding error (not enough data)

bit[1:0]

header error

UIS_MPEG_
STATUS

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

D0:13BB

Global Operation Status (GOS)

S/PDIF-Input

bit[7:5]

GOS_Type
0

GOS_NODEC, not decodable

GOS_PCM_WARN, channel status not plausible

GOS_DATA, data type

GOS_PCM

4...6

reserved

GOS_I2S

bit[4:1]

Appl_Type
0

AC-3

MPEG Layer-2

PCM

time code

noise generator

DTS

unknown

bit[0]

unsynchronized (default)

valid bit stream detected

This status cell reflects the result of the decoding with the parameters given. If
an incorrect input data type (D0:13D0) is selected, the input data stream will
not be decodable.

The GOS_PCM_WARN-flag is set when the S/PDIF-channel status indicates
PCM-encoded audio, but valid synchronization headers (Dolby Digital or
MPEG) are found.

UIS_GOS

D0:13BC

Bit Stream Information

S/PDIF-Input

each bit:

channel available

channel not available

bit[7]

bit stream number 7

...
bit[0]

bit stream number 0

Available bit streams (channels) in the S/PDIF-data.

UIS_DSI

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13BD
...
D0:13C4

Pc Information of Selected Data Stream (burst_info)

S/PDIF-Input

(Section 4.4.3 of Annex B of ATSC Spec. A/52)

bit[15:13]

hex

...7

hex

channel number (data_stream_number)

bit[12:8]

data_type_dependent, see below

bit[7]

error flag (error_flag)

data may be valid

data burst may contain errors

bit[6:5]

reserved

bit[4:0]

hex

reserved

hex

AC-3 data

hex

reserved

hex

pause

hex

MPEG Layer-1

hex

MPEG-1 Layer-2, 3, or MPEG-2 without extension

hex

MPEG-2 data with extension

hex

reserved

hex

MPEG-2 Layer-1 low fs

hex

MPEG-1 Layer-2, 3 low fs

hex

reserved

hex.

...D

hex.

DTS

hex.

...1F

hex.

reserved

This memory cell mirrors the Pc-word of the S/PDIF-preamble (burst_info) of
the selected of eight possible data streams (channels) if available.

UIS_PC<i>,
i = 0...7

Meaning of Field data_type_dependent

Dolby Digital

AC-3: (Section 4.7 of Annex B of ATSC Spec. A/52)

bit[12,11]

reserved, shall be '00'

bit[10:8]

value of bsmod as described in D0:13A2

D0:13C7

S/PDIF Status

S/PDIF

bit[3:2]

no error

parity error

bit[1]

Data Mode
0

PCM

compressed audio data

bit[0]

S/PDIF Copy Active
0

inactive

active

UIS_SP_STATUS

D0:1FFF

Version Number

All

Returns the version number of the ROM-code as ASCII

UIS_VERSION

Table 36: Status memory cells, continued

Memory
Address
(hex)

Function

Mode

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

3.6.2. Control Interface for Decoding Operation

The following table gives the writable memory
addresses of the control interface for the decoding
firmware.

Table 37: Configuration memory cells

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

D0:13D0

I/O Control

00000

UIC_IO_CONTROL

Soft Mute

All

bit[15]

Soft Mute
0

Soft mute off

Soft mute on

This switch is provided for user-controlled fast audio mute.

CRC Check

Dolby Digital

MPEG

bit[14]

CRC1
0

CRC1 on

CRC1 off

bit[13]

CRC2
0

CRC2 on

CRC2 off

Dolby Digital:
CRC1 protects the header and 3/5 of the data, CRC2 protects the
remaining 2/5 of the data. It is recommended that both AC-3 CRC-
checks are enabled which yields to an automatic mute upon detec-
tion of an error. However, under special operating conditions (noisy
channel), it may be advantageous to turn one (preferably CRC2) or
both CRC-checks off. In this case, it is important to decrease the lis-
tening volume to prevent hearing injuries and damages to the equip-
ment.

MPEG:
For MPEG, only CRC1 is applied. It is recommended to enable
CRC1 to avoid strong digital noise in case of deranged or unreliable
signals.

S/PDIF Channel Select

S/PDIF

bit[12:10]

S/PDIF channel select

000 Channel

...
111 Channel

The S/PDIF may carry up to eight channels of compressed audio.
Their content is shown in the S/PDIF-Pc-preambles
(D0:13B8...13BF).

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13D0

(continued)

Input and Mode Selection

All

bit[9]

S/PDIF or I

S Input Select

S/PDIF input

S input

bit[8]

S input select

S input at SID (word mode)

Continuos data stream at SID
(SII connected to ground)

bit[7:6]

Input data type

Auto-detection

AC-3 (Dolby Digital)

MPEG Layer-2

PCM

00000

UIC_IO_CONTROL

Output Interface Mode

All

bit[5]

default

S output mode: invert wordstrobe

bit[1]

S output channels

1 channel

2 channels

The clock and wordstrobe outputs SOC
and SOI apply to all 4 data outputs
SOD...SOD3

bit[0]

S output mode

no delay (as used in Sony Mode)

delay of data related to wordstrobe slope
(as used in Philips Mode)

Input Interface Mode

All

bit[4]

default

delay of data related to wordstrobe

bit[3]

default

invert wordstrobe

bit[2]

default

invert clock

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

D0:13D1

Noise Generator

All

(Sec. 4.10.2 of Dolby Digital Licensee Information Manual Issue 3)

bit[7]

Noise generator off

Noise generator on

bit[6]

Noise type

White noise

Band-pass shaped noise

bit[5:0]

000001

000010

000100

001000

010000

100000

LFE

000000

No channel selected

By combining the appropriate bits, more than one channel can out-
put noise. The noise type can be selected between white and band-
pass filtered with a maximum between 500 and 1000 Hz. The
required stepping actions have to be initiated by the controller.

00000

UIC_NOISE

D0:13D2

Center Channel Delay

Dolby Digital

(Sec. 4.10.1 of Dolby Digital Licensee Information Manual Issue 3)

bit [2:0]

000

0 ms

...
101

5 ms

00000

UIC_C_DELAY

D0:13D3

Left Surround Channel Delay

Dolby Digital

(Sec. 4.10.1 of Dolby Digital Licensee Information Manual Issue 3)

bit[3:0]

0000

0 ms

...
1111

15 ms

The surround delay for Dolby Pro Logic decoded signals must be set
in the DPL 4519G.

00001

UIC_SL_DELAY

D0:13D4

Right Surround Channel Delay

Dolby Digital

(Sec. 4.10.1 of Dolby Digital Licensee Information Manual Issue 3)

bit[3:0]

0000

0 ms

...
1111

15 ms

The surround delay for Dolby Pro Logic decoded signals must be set
in the DPL 4519G.

00000

UIC_SR_DELAY

D0:13D5

LFE Channel Enable

Dolby Digital

bit[0]

Route LFE Channel to subwoofer output
(if it exists in stream)

enable LFE

disable LFE

The subwoofer output is assembled from the LFE and the other
channels depending on the Output Configuration. This switch dis-
ables only content coming from the LFE.

00001

UIC_OUT_LFE

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13D6

Output Mode Control (Dolby Downmix)

Dolby Digital

(Section7.8 of ATSC Spec. A/52)

bit[4:3]

Dual mono setting of Dolby C decoder,
applicable only if Audio Coding Mode
is dual mono (acmod = 0). The actual
mixing depends on the number of
available output channels (speakers).

Stereo (straight output of both channels)

Left Mono (channel 1)

Right Mono (channel 2)

Mixed Mono (sum of both channels)

bit[2:0]

Listening Mode Selector
Defines the number of available (desired)
output channels (loudspeakers).

000

2/0

L, R Dolby Surround compatible

001

1/0

010

2/0

L, R

011

3/0

L, C, R

100

2/1

L, R, S

101

3/1

L, C, R, S

110

2/2

L, R, SL, SR

111

3/2

L, C, R, SL, SR

These downmixing options are independent of the setting of the
Extra Stereo Output (D0:13DE).

Undesired channels can be muted by setting the volume to zero or
by muting the outputs in the DPL 4519G or MSP 44x0G, respec-
tively.

Only listening modes 1/0, and 2/0 should be used if dual mono is
transmitted.

00007

UIC_OUT_MODE_
CONTROL

D0:13D7

Compression Control

Dolby Digital

(Operational Modes, Dialog Normalization)
(Sec. 3.7 of Dolby Digital Licensee Information Manual Issue 3)

bit[1:0]

Setting of Dolby C decoder

Custom Mode 0 (analog dialog
normalization)

Custom Mode 1 (internal digital dialog
normalization)

Line Mode

Compression RF out

The implemented dynamic range compression uses the transmitted
variables dynrng, compr, and dialnorm. In Line Mode and in the Cus-
tom Modes, the dynamic compression may be scaled down by using
the user-controlled high-level cut and low-level boost factors.

Note that in Custom Mode 0, the effect of dynrng must be imple-
mented in the analog part of the audio equipment.

Note that in the Custom Mode downmix, an internal digital attenua-
tion of 11 dB is applied that must be compensated externally.

00001

UIC_
COMPRESSION_
CONTROL

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

D0:13D8

High-Level Cut Compression Scale Factor

Dolby Digital

(Sec. 3.7 and Sec. 4.11.9 of Dolby Digital Licensee Information Man-
ual Issue 3)

bit[19:0]

00000

hex

(full dynamic)...7FFFF

hex

(full compression)

This factor scales down potential attenuation (i.e. dynamic compres-
sion) of loud portions of the audio as defined by dynrng. High-Level
Cut is only used in Line Mode (except in downmix) and in the Cus-
tom Modes.

Note: In order to prevent clipping due to the downmixing in the Cus-
tom and Line Modes, the High-Level Cut Compression Scale Factor
must always be left at 7FFFF

hex

when the Extra Stereo Output

(D0:13DE) is used in conjunction with non-downmixed channels
(D0:13D6).
Please refer to section 4.5.8. of Dolby Digital Licensee Information
Manual Issue 3.

7FFFF

UIC_CUT_X

D0:13D9

Low-Level Boost Compression Boost Factor

Dolby Digital

(Sec. 3.7 and Sec. 4.11.9 of Dolby Digital Licensee Information Man-
ual Issue 3)

bit[19:0]

00000

hex

(full dynamic)...7FFFF

hex

(full compression)

This factor scales down potential amplification (i.e. dynamic com-
pression) of weak portions of the audio as defined by dynrng. Low-
Level Boost is only used in Line Mode and in the Custom Modes.

7FFFF

UIC_BOOST_Y

D0:13DA

Bass Management

All

(see chapter 2.9.10.3.;Sec. 4.7 of Dolby Digital Licensee Information
Manual Issue 3)

bit[4:0]

0000

Direct loop-through of all six channels
without channel mixing

1000

Dolby Configuration 0

1001

Dolby Configuration 1

1010

Dolby Configuration 2

1011

Dolby Alternative Configuration 2

1100

Dolby Configuration 3 (No Subwoofer Out)

1101

Dolby Configuration 3 (Subwoofer Out)

1110

DVD Configuration (Bass to L/R)

1111

DVD Configuration (Bass to Subwoofer)

Note: If Bass Management is enabled, high processor clock must be
selected (D0:13DF; bit16 = 1)

The LFE-content can be disabled in D0:13D5.

The output configurations can be used for all input formats. How-
ever, for MPEG and PCM-dat, only the L and R input channels will
carry information.

00000

UIC_POST_
PROCESSING

D0:13DB

no longer required: do not write to this memory address

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13DD

Karaoke Mode

Dolby Digital

bit[1:0]

no vocals

vocal 1

vocal 2

vocal 1 (left) + vocal 2 (right)

00003

UIC_KARAOKE_
MODE

D0:13DE

Extra Stereo Output (Lt/Rt or Lo/Ro)

Dolby Digital

(surround encoded)

bit[0]

Lt/Rt stereo output

Lo/Ro stereo output

For headphone operation, the 2-channel output can be switched to
the Lo/Ro-mode.

Note: In order to prevent clipping due to the downmixing in the Cus-
tom and Line Modes, the High-Level Cut Compression Scale Factor
(D0:13D8) must always be left at 7FFFF

hex

when the Extra Stereo

Output is used in conjunction with non-downmixed channels
(D0:13D6).

00000

UIC_DOWNMIX_
MODE

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

D0:13DF

Output Clock Scaling

All

bit[19]

CLKO off

enable CLKO

disable CLKO

bit[18:17]

Division factor applied to the internal
reference clock
(see Table 22 on page 9) for the
CLKO-output

divide reference clock by 1

divide by 2

divide by 4

divide by 8

bit[16]

Low/high system clock for Dolby Digital
(please refer to Table 21 on page 9)

61/56/40 MHz for 48/44.1/32 kHz

73/67/49 MHz for 48/44.1/32 kHz

Sets the processor clock and the output clock at pin CLKO. The
clock frequencies are coupled to the audio data sampling rate of the
input signal by a PLL.

The high clock frequencies have to be used if the internal Dolby Dig-
ital Bass Management is used.

80004

UIC_OUT_CLK_
SCALE

Auxiliary Interface Control

All

bit[6]

S/PDIF input select

select SPDI input

select SPDI2 input

bit[5:3]

reserved (set to 0)

bit[2]

SOC Impedance

low impedance

high impedance

bit[1]

Serial input select

select SID, SII, SIC

select SID*, SII*, SIC*

bit[0]

reserved

Input/output interface selections.

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13E0

PCM/MPEG Deemphasis Control

MPEG/PCM

bit[1:0]

Deemphasis

automatic detection (only for PCM via
S/PDIF and all MPEG-inputs, no deem-
phasis if PCM via I

S-input is selected)

50/15 µs deemphasis

no deemphasis

J17 deemphasis

PCM-signals coming via the serial interface do not contain embed-
ded deemphasis information. The correct deemphasis must there-
fore be initiated by the controller.

PCM-signals coming via the S/PDIF-interface and MPEG-data
streams contain such information. In this case, the automatic detec-
tion should be enabled to achieve the correct deemphasis.

00000

UIC_DEEMPHASE
_CONTROL

D0:13E1
D0:13E2
D0:13E3
D0:13E4
D0:13E5
D0:13E6
D0:13E7
D0:13E8

Volume Control

All

Volume left channel
Volume center channel
Volume right channel
Volume surround left channel
Volume surround right channel
Volume subwoofer channel
Volume stereo left channel
Volume stereo right channel

bit[15:8]

hex

+12 dB

...
73

hex

0 dB

...
01

hex

114 dB

hex

mute

The resolution is 1 dB/step.

07300
(all)

UIC_L_VOLUME
UIC_C_VOLUME
UIC_R_VOLUME
UIC_SL_VOLUME
UIC_SR_VOLUME
UIC_LFE_VOLUM
E
UIC_L_ST_VOLUM
E
UIC_R_ST_VOLU
ME

D0:13EA

S/PDIF Channel Status Bits Control

All

bit[15]

L-bit (generation status)

bit[14:8]

category code

bit[7:6]

should be "0"

bit[5:3]

should be "0"

bit[2]

cp-bit (copyright protection)

bit[1]

should be "0" for PCM output

bit[0]

should be "0" for consumer use

These bits control the status word in the S/PDIF output. This control
is inactive if S/PDIF loop-through is selected.

Note: It must be made sure that bits 2, 8, .., 15 are set correctly.
Incorrect settings may affect the ability to make digital copies.

01904

UIC_CHANNEL
_STATUS

Table 37: Configuration memory cells, continued

Memory
Address
(hex)

Function

Mode

Reset
Value
(hex)

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

3.6.3. Hybrid User Interface Cells

Table 38: Hybrid User Interface Cells

Memory
Address
(hex)

Function

Reset
Value
(hex)

Name

D0:13FF

Message Constants

All

Messages
bit[19:0]
0

no error

all errors with an error number higher or equal to
this error number cause a restart

S/PDIF:sync lost during look for Pa, Pb, Pc, Pd

S/PDIF: sync lost during operation

Data Stream Error (Pa not correct)

Data Stream Error (Pb not correct)

Data Stream Error (Pc not correct)

Data Stream Error (Pd to big)

S timeout error

no input data type selected in I

S input mode

(i.e. auto-detection is ON)

input type over S/PDIF changed from pcm to data

AC-3: initial waiting time out

AC-3: sync waiting time out

AC-3: sync lost

AC-3: header corrupted

AC-3: CRC1 wait timeout

AC-3: CRC1 fail

AC-3: CRC2 wait timeout

AC-3: CRC2 fail

selected bit-stream-number not available

PCM recognition inconsistent, restart

DATA TYPE in BurstInfo not AC-3, PCM, MPEG, or
DTS.

AC-3 - Sampling frequency changed

invalid exponents detected

S/PDIF: Input type chosen manually (not autodetected)

AC3: Input buffer overrun
- the input pointer overwrites the actual frame

S/PDIF input parity error

MPEG: sampling frequency changed

MPEG no header found

MPEG: no Layer 2 header found

MPEG: restart forced

MPEG: not enough data to decode

MPEG: S/PDIF error

MPEG: decoding error

MPEG: input timeout

MPEG: sync error

MPEG: data rate too high (probably PCM input)

...

00000

UIH_LAST_
MESSAGE

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

D0:13FF

(continued)

[50:66]

User interface messages

LM_USER_CHANGE

LM_IO_CONTROL

LM_NOISE

LM_C_DELAY

LM_SL_DELAY

LM_RL_DELAY

LM_OUT_LFE

LM_OUT_MODE_CONTROL

LM_COMPRESSION_CONTROL

LM_CUT_X

LM_BOOST_Y

LM_POST_PROCESSING

LM_SAMP_FREQ

LM_OUTN_CHANNELS

LM_KARAOKE_MODE

LM_DOWNMIX_MODE

LM_OUT_CLK_SCALE

PCM: Sampling frequency changed in PCM Mode

The latest message that occurred is displayed in this cell. The con-
troller should frequently (e.g. once per frame) check and clear this
memory location.

After reading the message it is recommended to clear this cell (by
writing a "0") to see whether this message occurs again.

00000

UIH_LAST_
MESSAGE

Table 38: Hybrid User Interface Cells, continued

Memory
Address
(hex)

Function

Reset
Value
(hex)

Name

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

4. Specifications

4.1. Outline Dimensions

Fig. 41:
44-Pin Plastic Leaded Chip Carrier Package
(PLCC44K)
Weight approximately 2.5 g
Dimensions in mm

4.2. Pin Connections and Short Descriptions

not connected, leave vacant

If not used, leave vacant

obligatory, pin must be connected as described
in application information

VDD connect to positive supply
VSS connect to ground

15.7

0.3

10 x 1.27 = 12.7

0.1

1.2 x 45

1.6

0.1

8.6

x 45

1.1

1.27

SPGS704000-1(P44/K)/1E

17.52

0.12

17.52

0.12

16.5

0.1

16.5

0.1

10 x 1.27 = 12.7

0.1

4.75

0.15

4.05

0.1

1.9

0.05

0.27

0.03

0.71

0.05

0.48

0.06

0.9

0.2

Pin No.
PLCC
44-pin

Pin Name

Type

Connection

(if not used)

Short Description

VSS

SUPPLY

Ground supply for digital parts

VDD

SUPPLY

Positive supply for digital parts

I2CD

IN/OUT

VDD

C data line

I2CC

IN/OUT

VDD

C clock line

POR

Reset, active low

VSS

Test enable

AVSS

SUPPLY

Ground supply for analog circuits

AVDD

SUPPLY

Supply for analog circuits

XTI

Clock input/quartz oscillator pin 1

XTO

OUT

Quartz oscillator pin 2

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

CLKO

OUT

DSP clock output for the D/A-converter

SOD1

OUT

Serial output data 1

SOD2

OUT

Serial output data 2

SOD3

OUT

Serial output data 3

SPDIFOUT

OUT

S/PDIF output

PI4

IN (OUT)

VSS

PIO data [4]

SIC

VSS

Serial input clock

SII

VSS

Serial input frame identification

SID

VSS

Serial input data

XVSS

SUPPLY

Ground for output buffers

XVDD

SUPPLY

Positive supply for output buffers

PI8

IN (OUT)

VSS

PIO data [8]

SOC

OUT

Serial output clock

SOI

OUT

Serial output frame identification

SOD

OUT

Serial output data

PI12

IN (OUT)

VSS

PIO data [12]

PI13

IN (OUT)

VSS

PIO data [13]

SID* (PI14)

IN (OUT)

VSS

PIO data [14], SID* = alternative input for SID

SII* (PI15)

IN (OUT)

VSS

PIO data [15], SII* = alternative input for SII

SIC* (PI16)

IN (OUT)

VSS

PIO data[16], SIC* = alternative input for SIC

PI17

IN (OUT)

VSS

PIO data [17]

PI18

IN (OUT)

VSS

PIO data [18]

PI19

IN (OUT)

VSS

PIO data [19]

VDD

Test pin

VDD

Test pin

SPDI

VSS

S/PDIF input 1

SPREF

S/PDIF input (reference)

SPDI2

VSS

S/PDIF input 2

OUT

Test pin

OUT

Test pin

Pins are configured as input after reset.

Pin No.
PLCC
44-pin

Pin Name

Type

Connection

(if not used)

Short Description

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

4.3. Pin Descriptions

4.3.1. Power Supply Pins

Connection of all power supply pins is mandatory for
the functioning of the MAS 3528E.

VDD

SUPPLY

VSS

SUPPLY

The VDD/VSS pair is internally connected with all digi-
tal modules of the MAS 3528E.

XVDD

SUPPLY

XVSS

SUPPLY

The XVDD/XVSS pins are internally connected with
the pin output buffers.

AVDD

SUPPLY

AVSS

SUPPLY

The AVDD/AVSS pair is connected internally with the
analog blocks of the MAS 3528E, i.e. clock synthesizer
and supply voltage supervision circuits.

4.3.2. Control Lines

I2CC

SCL

IN/OUT

I2CD

SDA

IN/OUT

Standard I

C control lines.

4.3.3. General Purpose Input/Output

PI4, PI8, PI12...PI19

IN/OUT

General purpose input/output pins. PI14 to PI16 can
be used as alternative I

S bus inputs. Function is con-

trolled by the registers PIO_Config, PIO_Direction,
PIO_Data_Out, PIO_Data_In.

4.3.4. Clocking

XTI

This is the clock input of the MAS 3528E. The nominal
clock frequency is 18.432 MHz.

XTO

This connection is needed for the quartz oscillator.

CLKO

OUT

The CLKO is an oversupplying clock that is synchro-
nized to the digital audio data (SOD) and the frame
identification (SOI).

4.3.5. Serial Input Interface

SID

SII

SIC

Data, frame indication, and clock line of the standard
I

S (word mode) serial input interface.

PI16

SIC*

PI15

SII*

PI14

SID*

The SIC*, SID*, and SII* are alternative serial input
lines. This interface can be selected in memory cell
D0:13D0.

OUT

Test pin

SYNC

OUT

Reserved for frame synchronization

Pin No.
PLCC
44-pin

Pin Name

Type

Connection

(if not used)

Short Description

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

4.3.6. S/PDIF Input Interface

SPDI

SPDI2

SPREF

Input lines (SPDI/SPDI2) and ground reference line
(SPREF) of the S/PDIF-input interfaces. One of the
two alternate input lines is selected by in D0:13DF.

4.3.7. S/PDIF Output Interface

SPDIFOUT

OUT

S/PDIF-output line.

4.3.8. Serial Output Interface

SOD

OUT

SOD1

OUT

SOD2

OUT

SOD3

OUT

SOI

OUT

SOC

OUT

Data, frame indication, and clock line of the serial out-
put interface. The SOI indicates whether the left or the
right audio sample is transmitted. Besides the two
modes, it is possible to reconfigure the interface.

4.3.9. Miscellaneous

POR

The POR pin is used to reset the digital parts of the
MAS 3528E. POR is a low active signal.

The TE pin is for production test only and must be con-
nected with VSS in all applications.

SYNC
The SYNC pin is set while decoding Dolby Digital or
MPEG. Only during header processing, there is a short
Low period (20...300

s depending on the audio for-

mat)

4.4. Pin Configuration

Fig. 42: PLCC44 package

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40

AVSS

AVDD

XTI

XTO

N.C.

CLKO

SOD1

SOD2

SOD3

SPDIFOUT

SPREF

SPDI

PCS

PI19

PI18

PI17

PI16

PI15

PI14

PI13

POR

I2CC

I2CD

VDD

VSS

SYNC

EOD

RTR

RTW

SPDI2

SIC

SII

SID

XVSS

XVDD

PI4

PI8

SOC

SOI

SOD

PI12

MAS 3528E

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.

Symbol

Parameter

Pin Name

Min.

Max.

Unit

Ambient Operating Temperature

°C

Case Operating Temperature

115

°C

Storage Temperature

125

°C

TOT

Power Dissipation

VDD, XVDD,
AVDD

1250

SUPD

Digital Supply Voltage

VDD, XVDD

0.3

6.0

SUPA

Analog Supply Voltage

AVDD

0.3

6.0

SUP

Voltage differences between any
supply region

VDD,
AVDD,
XVDD

0.5

Voltage differences between differ-
ent Grounds

VSS,
AVSS,
XVSS

0.5

Idig

Input Voltage, all Digital Inputs

0.3

SUP

+0.3

Idig

Input Current, all Digital Inputs

Out

Current, all Digital Outputs

250

Output Load

300

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

4.6.2. Recommended Operating Conditions (T

= 0 to +65 °C)

4.6.2.1. General Recommended Operating Conditions

4.6.2.2. Reference Frequency Generation and Crystal Recommendations

4.6.2.3. Input Levels at V

= 4.5 V...5.5 V

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Ambient Operating Temperature

°C

SUPD

Digital supply voltage

VDD, XVDD

4.75

5.0

5.25

SUPA

Analog supply voltage

AVDD

4.75

5.0

5.25

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

External Clock Input Recommendations

CLK

Clock frequency

XTI

18.432

MHz

CLK

Amp

Clock amplitude

0.7

3.5

Crystal Recommendations

Ambient temperature range

XTI, XTO

°C

Load resonance frequency at
C

= 12 pF

18.432

MHz

f/f

Accuracy of frequency adjust-
ment

ppm

f/f

Frequency variation vs. temper-
ature

ppm

Equivalent series resistance

Shunt (parallel) capacitance

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Input low voltage

POR
I2CC,
I2CD

0.5

Input high voltage

2.6

ILD

Input low voltage

PI<i>,
SII,
SIC,
SID,
PR,
TE,

0.5

IHD

Input high voltage

SUP

0.5

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

4.6.3. Characteristics at T

= 0 to 65 °C, V

= 5.0 V, f

Crystal

= 18.432 MHz

4.6.3.1. General Characteristics

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Supply Current

SUP

Current consumption

all
supply pins

210

5.0 V, audio sampling
frequency 48 kHz
Dolby Digital, 61 MHz
fproc

Digital Outputs and Inputs

DigL

Output low voltage

PI<i>,
SOI,
SOC,
SOD,
SOD1,
SOD2,
SOD3,
EOD,
RTR,
RTW,
CLKO
SPDIF-OUT

0.5

at I

load

= 1 mA

DigH

Output high voltage

SUP

0.5

at I

load

= 1 mA

DigI

Input capacitance

all
digital Inputs

DLeak

Input leakage current

µA

0 V < V

< V

SUP

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

4.6.3.2. I

C Characteristics

Fig. 412: I

C timing diagram

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Output resistance

I2CC,
I2CD

load

= 5 mA,

= 4.5 V

I2C

C bus frequency

I2CC

400

kHz

I2C1

C START condition setup

time

I2CC,
I2CD

300

I2C2

C STOP condition setup

time

I2CC,
I2CD

300

I2C3

C clock low pulse time

I2CC

1250

I2C4

C clock high pulse time

I2CC

1250

I2C5

C data hold time before

rising edge of clock

I2CC

I2C6

C data hold time after

falling edge of clock

I2CC

I2COL

C output low voltage

I2CC,
I2CD

0.3

LOAD

= 5 mA

I2COH

C output high leakage

current

I2CC,
I2CD

µA

I2CH

= 5.5 V

I2COL1

C data output hold time

after falling edge of clock

I2CC,
I2CD

I2COL2

C data output setup time

before rising edge of clock

I2CC,
I2CD

250

I2C

= 400kHz

I2CC

I2CD as input

I2CD as output

I2C1

I2C5

I2C6

I2C2

I2C4

I2C3

1/f

I2C

I2COL2

IC2OL1

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

4.6.3.3. S/PDIF-Bus Input Characteristics

Fig. 413: Timing of the S/PDIF-input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Signal amplitude

SPDI,
SPDI2,

200

500

1000

Biphase frequency

SPDI,
SPDI2

3.072

MHz

1000 ppm, f

= 48 kHz

Biphase frequency

SPDI,
SPDI2

2.822

MHz

1000 ppm,

= 44.1 kHz

Biphase frequency

SPDI,
SPDI2

2.048

MHz

1000 ppm, f

= 32 kHz

Biphase period

SPDI,
SPDI2

326

at f

= 48 kHz,

(highest sampling rate)

Rise time

SPDI,
SPDI2

at f

= 48 kHz,

(highest sampling rate)

Fall time

SPDI,
SPDI2

at f

= 48 kHz,

(highest sampling rate)

Duty-cycle

SPDI,
SPDI2

at "1" and f

= 48 kHz

90%

10%

90%

10%

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

4.6.3.5. I

S Bus Characteristics Input

Fig. 415: Serial input of continuous data stream (SII must be held down). Data values are latched with falling clock

per default.

Fig. 416: Serial input of I

S signal (PCM). Data values are latched with rising clock per default.

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

SICLK

S clock input clock period

SIC

960

Burst mode, mean data
rate < 150 kbit/s

SIDDS

S data setup time before

falling edge of clock

SIC, SID

SICLK

100

SIDDH

S data hold time

SIC, SID

SIIDS

S word strobe setup time

before falling(/rising) edge of
clock

SIC, SII

SICLK

100

SIIDH

S word strobe hold time

SIC, SII

Burst wait time

SIC,
SID

480

SIC

(SII)

SID

SICLK

SIDDH

SIDDS

30 29 28 27 26 25 ... 7

31 30 29 28 27 26 25

left 32-bit audio sample

right 32-bit audio sample

SIC

SID

SII

I2S

...

data valid at

falling edge of clock

PRELIMINARY DATA SHEET

MAS 3528E

Micronas

4.6.3.6. I

S Characteristics Output

Fig. 417: I

S-output. Data values are valid with rising clock per default.

Fig. 418: Schematic timing of the SDO interface in 32 bit/sample mode

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

SCLKO

S clock output frequency

SOC

325

48 kHz sample rate
2

32 bits/sample

SOISS

S word strobe hold time

after falling edge of clock

SOC,
SOI

SCLKO

SOODC

S data hold time after

falling edge of clock

SOC,
SOD

SCLKO

SOC

SOI

SOD

SCLKO

SOISS

SOODC

30 29 28 27 26 25 ... 7

31 30 29 28 27 26 25

left 32-bit audio sample

right 32-bit audio sample

SOC

SOD

SOI

...

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

Fig. 419: Serial interface format for multichannel mode.

4.6.4. Firmware Characteristics

19 20

31 32

51 52

63 64

SCLOCK

SSYNC

SDATA

Subframe 1 (left) Audio Data

Aux Data "A"

Subframe 1 (right) Audio Data

Aux Data "B"

Subframe 1

MSB

LSB (20-bit)

MSB

LSB (20-bit)

MSB

Detail A

Detail B

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Synchronization Times for Dolby Digital Mode

DDsync

Synchronization on Dolby
Digital Bit Streams

140

= 48 kHz, AC-3

Synchronization Times for MPEG-Mode

mpgsync

Synchronization on MPEG
Bit Streams

120

= 48 kHz, MPEG

Ranges

PLLRange

Tracking range of sampling
clock recovery PLL

200

ppm

All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.

MAS 3528E

PRELIMINARY DATA SHEET

Micronas

Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com

Printed in Germany
Order No. 6251-509-1PD

5. Data Sheet History

1. Preliminary data sheet: "MAS 3528E Dolby Digital
and MPEG-1 Layer-2 Audio Decoder", Dec. 10, 2001,
6251-509-1PD. First release of the preliminary data
sheet.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MAS3528E

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MAS3528E