Document Outline
- Features
- Options
- Key SDRAM Component Timing Parameters
- Part Numbers
- Pin Assignment
- General Description
- Serial Presence-Detect Operation
- SPD Clock and Data Conventions
- SPD Start Condition
- SPD Stop Condition
- SPD Acknowledge
- Figure 1 Data Validity
- Figure 2 Definition of Start and Stop
- Figure 3 Acknowledge Response from Receiver
- Functional Block Diagram MT1LSDT232U (8MB)
- Pin Descriptions
- Serial Presence-Detect Matrix
- Commands
- Truth Table 1 - Commands and DQMB Operation
- Figure 4 Mode Register Definition
- Table 1 Burst Definition
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- IDD Specifications and Conditions
- Capacitance
- SDRAM Component AC Electrical Characteristics
- AC Functional Characteristics
- Serial Presence-Detect EEPROM DC Operating Conditions
- Serial Presence-Detect EEPROM AC Electrical Characteristics
- SPD EEPROM
- 100-Pin DIMM (8MB Version)
1
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
FEATURES
JEDEC pinout in a 100-pin, dual in-line memory
module (DIMM)
8MB (2 Meg x 32)
Utilizes 125 MHz SDRAM components
Single +3.3V 0.3V power supply
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge and Auto Refresh Modes
64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
OPTIONS
MARKING
Package
100-pin DIMM (gold)
G
Timing (Cycle Time)
8ns (125 MHz)
-8
PIN ASSIGNMENT (Front View)
100-Pin DIMM
PIN
FRONT
PIN
FRONT
PIN
BACK
PIN
BACK
1
V
SS
26
V
SS
51
V
SS
76
V
SS
2
DQ0
27
CKE0
52
DQ8
77
NC (CKE1)
3
DQ1
28
WE#
53
DQ9
78
DNU
4
DQ2
29
S0#
54
DQ10
79
NC (S1#)
5
DQ3
30
NC (S2#)
55
DQ11
80
NC (S3#)
6
V
DD
31
V
DD
56
V
DD
81
V
DD
7
DQ4
32
NC
57
DQ12
82
NC
8
DQ5
33
NC
58
DQ13
83
NC
9
DQ6
34
NC
59
DQ14
84
NC
10
DQ7
35
NC
60
DQ15
85
NC
11
DQMB0#
36
V
SS
61
DQMB1#
86
V
SS
12
V
SS
37
DQMB2#
62
V
SS
87
DQMB3#
13
A0
38
DQ16
63
A1
88
DQ24
14
A2
39
DQ17
64
A3
89
DQ25
15
A4
40
DQ18
65
A5
90
DQ26
16
A6
41
DQ19
66
A7
91
DQ27
17
A8
42
V
DD
67
A9
92
V
DD
18
A10
43
DQ20
68
BA0
93
DQ28
19
BA1
44
DQ21
69
NC (A11)
94
DQ29
20
NC (A12)
45
DQ22
70
NC (A13)
95
DQ30
21
V
DD
46
DQ23
71
V
DD
96
DQ31
22
DNU
47
V
SS
72
RAS#
97
V
SS
23
RFU
48
SDA
73
CAS#
98
SA0
24
RFU
49
SCL
74
RFU
99
SA1
25
CK0
50
V
DD
75
CK1
100
SA2
SYNCHRONOUS
DRAM MODULE
MT1LSDT232U
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/datasheet.html
KEY SDRAM COMPONENT TIMING
PARAMETERS
SPEED
CLOCK
ACCESS TIME
SETUP
HOLD
GRADE
FREQUENCY CL = 2* CL = 3*
TIME
TIME
-8
125 MHz
9ns
6ns
2ns
1ns
*CL = CAS (READ) latency
NOTE: Pin symbols in parentheses are not used on this
module but may be used for other modules in this
product family. They are for reference only.
PART NUMBERS
PART NUMBER
CONFIGURATION
DEVICE PACKAGE
MT1LSDT232UG-8_
2 Meg x 32
TSOP
NOTE: All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT1LSDT232UG-8C1.
GENERAL DESCRIPTION
The MT1LSDT232U is a high-speed CMOS, dynamic
random-access, 8MB solid-state memory organized in a
x32 configuration. This module is configured as a
single bank with a synchronous interface (all signals
are registered on the positive edge of the clock signals
CK0 and CK1). Read and write accesses to the SDRAM
2
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
GENERAL DESCRIPTION (continued)
module are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the bank and row to be
accessed (BA0 selects the bank; A0-A11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column
location for the burst access.
This module provides for a programmable READ or
WRITE burst terminate option. An auto precharge func-
tion may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The modules use an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while
accessing the alternate bank will hide the PRECHARGE
cycles and provide seamless, high-speed, random-
access operation.
This module is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM
operating performance, including the ability to syn-
chronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access. For
more information regarding SDRAM operation, refer to
the 64 Meg: x32 SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
This module incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM's
SCL (clock) and SDA (data) signals, together with SA(2:0),
which provide eight unique DIMM/EEPROM addresses.
3
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
Figure 3
Acknowledge Response From Receiver
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 2
Definition of Start and Stop
SCL
SDA
START
BIT
STOP
BIT
Figure 1
Data Validity
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD STOP CONDITION
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and its
slave address. If both the device and a WRITE operation
have been selected, the SPD device will respond with an
acknowledge after the receipt of each subsequent eight-
bit word. In the read mode the SPD device will transmit
eight bits of data, release the SDA line and monitor the
line for an acknowledge. If an acknowledge is detected
and no stop condition is generated by the master, the
slave will continue to transmit data. If an acknowledge
is not detected, the slave will terminate further data
transmissions and await the stop condition to return to
standby power mode.
4
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
FUNCTIONAL BLOCK DIAGRAM
MT1LSDT232U (8MB)
NOTE:
All resistor values are 10 ohms.
U1 = MT48LC2M32B2TG SDRAM
A0
SPD
SCL
SDA
A1
A2
RAS#
CAS#
CKE0
WE#
RAS#: SDRAM U1
CAS#: SDRAM U1
CKE: SDRAM U1
WE#: SDRAM U1
A0-A10: SDRAM U1
BA: SDRAM U1
BA: SDRAM U1
A0-A10
BA0
BA1
V
CC
V
SS
SDRAM U1
SDRAM U1
CK0
U1
CK1
15pF
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM1
U1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S0#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM0 CS#
DQMB1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
DQMB3
10pF
WP
47K
U2
5
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
72, 73, 28
RAS#, CAS#, WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with
S0#-S3#) define the command being entered.
25, 75
CK0, CK1
Input
Clock: CK0 and CK1 are driven by the system clock. All
SDRAM input signals are sampled on the positive edge
of CK. CK also increments the internal burst counter
and controls the output registers.
27
CKE0
Input
Clock Enable: CKE0 activates (HIGH) and deactivates
(LOW) the CK signal. Deactivating the clock provides
POWER-DOWN and SELF REFRESH operation (all banks
idle), or CLOCK SUSPEND operation (burst access in
progress). CKE is synchronous except after the device
enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same
mode. The input buffers, including CK0 and CK1, are
disabled during power-down and self refresh modes,
providing low standby power.
29
S0#
Input
Chip Select: S0# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands
are masked when S0# is registered HIGH. S0# is consid-
ered part of the command code.
11, 61, 37, 87
DQMB0-DQMB3
Input
Input/Output Mask: DQMB is an input mask signal for
write accesses and an output enable signal for read
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (after a two-clock latency) when
DQMB is sampled HIGH during a READ cycle.
68, 19
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
13, 63, 14, 64, 15, 65,
A0-A10
Input
Address Inputs: A0-A10 are sampled during the ACTIVE
16, 66, 17, 67, 18
command (row-address A0-A10) and READ/WRITE
command (column-address A0-A7, with A10 defining
auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled
during a PRECHARGE command to determine if both
banks are to be precharged (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE
REGISTER command.
49
SCL
Input
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
98-100
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
6
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
2-5, 7-10, 52-55, 57-60,
DQ0-DQ31
Input/
Data I/O: Data bus.
38-41, 43-46, 88-91,
Output
93-96
48
SDA
Input/Output
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
6, 21, 31, 42, 50,
V
DD
Supply
Power Supply: +3.3V 0.3V.
56, 71, 81, 92
1, 12, 26, 36, 47,
V
SS
Supply
Ground.
51, 62, 76, 86, 97
23, 24, 74
RFU
Reserved for Future Use: These pins should be left
unconnected.
22, 78
DNU
Do Not Use: These pins are not connected on this
module but are assigned pins on the compatible DRAM
version.
20, 30, 69, 70,
NC
No Connects: These pins are not connected on this
77, 79, 80
module but may be used on other modules in this
family.
32-35, 82-85
NC
No Connects: These pins are not connected.
7
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
NOTE: "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
ENTRY (VERSION)
MT1LSDT232U (Hex)
0
NUMBER OF BYTES USED BY MICRON
128
80
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
08
2
MEMORY TYPE
SDRAM
04
3
NUMBER OF ROW ADDRESSES
11
0B
4
NUMBER OF COLUMN ADDRESSES
8
08
5
NUMBER OF BANKS
1
01
6
MODULE DATA WIDTH
32
20
7
MODULE DATA WIDTH (continued)
0
00
8
MODULE VOLTAGE INTERFACE LEVELS
LVTTL
01
9
SDRAM CYCLE TIME,
t
CK
8
80
(CAS LATENCY = 3)
10
SDRAM ACCESS FROM CLOCK,
t
AC
6
60
(CAS LATENCY = 3)
11
MODULE CONFIGURATION TYPE
NONPARITY
00
12
REFRESH RATE/TYPE
15.6s/SELF
80
13
SDRAM WIDTH (PRIMARY SDRAM)
32
20
14
ERROR-CHECKING SDRAM DATA WIDTH
NONE
00
15
MINIMUM CLOCK DELAY,
t
CCD
1
01
16
BURST LENGTHS SUPPORTED
1, 2, 4, 8, PAGE
8F
17
NUMBER OF BANKS ON SDRAM DEVICE
4
04
18
CAS LATENCIES SUPPORTED
1, 2, 3
07
19
CS LATENCY
0
01
20
WE LATENCY
0
01
21
SDRAM MODULE ATTRIBUTES
UNBUFFERED
00
22
SDRAM DEVICE ATTRIBUTES: GENERAL
0E
0E
23
SDRAM CYCLE TIME,
t
CK
13
D0
(CAS LATENCY = 2)
24
SDRAM ACCESS FROM CLK,
t
AC
9
90
(CAS LATENCY = 2)
25
SDRAM CYCLE TIME,
t
CK
25
64
(CAS LATENCY = 1)
26
SDRAM ACCESS FROM CLK,
t
AC
22
58
(CAS LATENCY = 1)
27
MINIMUM ROW PRECHARGE TIME,
t
RP
24
18
28
MINIMUM ROW ACTIVE TO ROW ACTIVE,
t
RRD
20
14
29
MINIMUM RAS# TO CAS# DELAY,
t
RCD
24
18
30
MINIMUM RAS# PULSE WIDTH,
t
RAS
48
30
31
MODULE BANK DENSITY
8 MB
02
32
COMMAND AND ADDRESS SETUP TIME
2
20
33
COMMAND AND ADDRESS HOLD TIME
1
10
34
DATA SIGNAL INPUT SETUP TIME
2
20
35
DATA SIGNAL INPUT HOLD TIME
1
10
8
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.
SERIAL PRESENCE-DETECT MATRIX (continued)
BYTE
DESCRIPTION
ENTRY (VERSION)
MT1LSDT232U (Hex)
36-61
RESERVED
00
62
SPD REVISION
2.0
02
63
CHECKSUM FOR BYTES 0-62
E0
64
MANUFACTURER'S JEDEC ID CODE
MICRON
2C
65-71
MANUFACTURER'S JEDEC ID CODE (continue)
FF
72
MANUFACTURING LOCATION
01
02
03
04
05
06
07
08
09
73-90
MODULE PART NUMBER (ASCII)
x
91
PCB IDENTIFICATION CODE
1
01
2
02
3
03
4
04
5
05
6
06
7
07
8
08
9
09
92
IDENTIFICATION CODE (continue)
0
00
93
YEAR OF MANUFACTURE IN BCD
x
94
WEEK OF MANUFACTURE IN BCD
x
95-98
MODULE SERIAL NUMBER
x
99-127 MANUFACTURER-SPECIFIC DATA (RSVD)
9
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
COMMANDS
Truth Table 1 provides a general reference of
available commands. For a more detailed description
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 define the op-code written to the Mode Register.
3. A0-A10 provide row address and BA0, BA1 determine which bank is made active.
4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: both banks are precharged and BA0, BA1
are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
TRUTH TABLE 1 COMMANDS AND DQMB OPERATION
(Notes: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQMB
ADDR
DQs
NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column, and start READ burst)
L
H
L
H
X
Bank/Col
X
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
X
Bank/Col
Valid
4
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or
L
L
L
H
X
X
X
6, 7
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
L
L
L
L
X
Op-code
X
2
Write Enable/Output Enable
L
Active
8
Write Inhibit/Output High-Z
H
High-Z
8
of commands and operations, refer to the 64 Meg x32
SDRAM data sheet.
10
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
NOTE: 1. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column
within the block.
3. For a burst length of eight, A3-A7 select the
block-of-eight burst; A0-A2 select the starting
column within the block.
4. For a full-page burst, the full row is selected, and
A0-A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0-A7 select the unique
column to be accessed, and Mode Register bit M3
is ignored.
Table 1
Burst Definition
Burst
Starting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential Type = Interleaved
A0
2
0
0-1
0-1
1
1-0
1-0
A1 A0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2 A1 A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A7
Cn, Cn + 1, Cn + 2
Page
Cn + 3, Cn + 4...
Not Supported
(256)
(location 0-255)
...Cn - 1,
Cn...
Figure 4
Mode Register Definition
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A10
A11
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
11
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply Relative to V
SS
.... -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to V
SS
..................................... -1V to +4.6V
Operating Temperature, T
A
(ambient) ... 0C to +70C
Storage Temperature (plastic) ............ -55C to +125C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 2) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2
V
DD
+ 0.3
V
3
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-0.5
0.8
V
3
INPUT LEAKAGE CURRENT:
I
I
1
-5
5
A
Any input 0V
V
IN
V
DD
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT:
I
OZ
-5
5
A
DQs are disabled; 0V
V
OUT
V
DD
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= 4mA)
V
OL
0.4
V
NOTE: 1. All voltages referenced to V
SS
.
2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper
device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
3. V
IH
overshoot: V
IH
(MAX) = V
DD
+ 1.2V for a pulse width
3ns, and the pulse width cannot be greater than one third
of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -1.2V for a pulse width
3ns, and the pulse width cannot be greater than
one third of the cycle rate.
12
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
I
DD
SPECIFICATIONS AND CONDITIONS
(Notes: 1, 2, 3, 4) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
SIZE
-8
UNITS NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;
I
DD
1
8MB
120
mA
5, 7,
t
RC =
t
RC (MIN); CAS latency = 3
8, 9
STANDBY CURRENT: Power-Down Mode;
I
DD
2
8MB
2
mA
29
CKE = LOW; All banks idle
STANDBY CURRENT: Active Mode; CKE = HIGH; S0#-S3# = HIGH;
I
DD
3
8MB
50
mA
3, 6,
All banks active after
t
RCD met; No accesses in progress
8, 9
OPERATING CURRENT: Burst Mode; Continuous burst;
I
DD
4
8MB
185
mA
3, 7,
READ or WRITE; All banks active; CAS latency = 3
8, 9
AUTO REFRESH CURRENT:
t
RC =
t
RC (MIN); CL = 3
I
DD
5
8MB
225
mA
3, 6,
CKE = HIGH; S0#-S3# = HIGH
7, 8,
t
RC = 15.625s; CL = 3
I
DD
6
8MB
50
mA
9
SELF REFRESH CURRENT: CKE
0.2V
I
DD
7
8MB
2
mA
10
MAX
NOTE: 1. All voltages referenced to V
SS
.
2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper
device operation is ensured. (V
DD
and V
DD
Q must be powered up simultaneously. V
SS
and V
SS
Q must be at the same
potential.) The two AUTO REFRESH command wake-ups should be repeated any time the
t
REF refresh requirement is
exceeded.
3. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced to 1.5V crossover point.
4. I
DD
specifications are tested after the device is properly initialized.
5. I
DD
is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the
outputs open.
6. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid V
IH
or V
IL
levels.
7. The I
DD
current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is
slower as the CAS latency is reduced.
8. Address transitions average one transition every two clocks.
9.
t
CK = 8ns.
10. Enables on-chip refresh and address counters.
CAPACITANCE
(Notes: 1)
8MB
PARAMETER
SYMBOL
MIN
MAX
UNITS NOTES
Input Capacitance: CK0
C
I
1
13
15
pF
2
Input Capacitance: All other input-only pins
C
I
2
4
6
pF
2
Input/Output Capacitance: DQ0-DQ31, SDA
C
IO
6
8
pF
2
NOTE: 1. This includes 10pf load on CK0.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
13
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
*Specifications for the SDRAM components used on the module.
SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS
(Notes: 1, 2, 3, 4, 5; notes appear below and on next page.)
AC CHARACTERISTICS
-8
PARAMETER
SYMBOL
MIN
MAX
UNITS NOTES
Access time from CLK (pos. edge)
CL = 3
t
AC
6
ns
CL = 2
t
AC
9
ns
CL = 1
t
AC
22
ns
Address hold time
t
AH
1
ns
Address setup time
t
AS
2
ns
CLK high-level width
t
CH
3
ns
CLK low-level width
t
CL
3
ns
Clock cycle time
CL = 3
t
CK
8
ns
6
CL = 2
t
CK
13
ns
6
CL = 1
t
CK
25
ns
6
CKE hold time
t
CKH
1
ns
CKE setup time
t
CKS
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
2
ns
Data-in hold time
t
DH
1
ns
Data-in setup time
t
DS
2
ns
Data-out high-impedance time
CL = 3
t
HZ
6
ns
7
CL = 2
t
HZ
9
ns
7
CL = 1
t
HZ
22
ns
7
Data-out low-impedance time
t
LZ
1
ns
Data-out hold time
t
OH
2.5
ns
ACTIVE to PRECHARGE command
t
RAS
48
120,000
ns
ACTIVE to ACTIVE command period
t
RC
80
ns
AUTO REFRESH period
t
RCAR
80
ns
ACTIVE to READ or WRITE delay
t
RCD
24
ns
Refresh period ( 4,096 cycles)
t
REF
64
ms
PRECHARGE command period
t
RP
24
ns
ACTIVE bank A to ACTIVE bank B command
t
RRD
20
ns
Transition time
t
T
1
1.2
ns
8
WRITE recovery time
t
WR
1 CLK +
9
2ns
10
ns
10
Exit SELF REFRESH to ACTIVE command
t
XSR
80
ns
11
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range (0C
T
A
+70C) is ensured.
2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper
device operation is ensured. (V
DD
and V
DD
Q must be powered up simultaneously. V
SS
and V
SS
Q must be at the same
potential.) The two AUTO REFRESH command wake-ups should be repeated any time the
t
REF refresh requirement is
exceeded.
3. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or
between V
IL
and V
IH
) in a monotonic manner.
14
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
NOTES: (continued)
4. Outputs measured at 1.5V with equivalent load:
5. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced to 1.5V crossover point.
6. The clock frequency must remain constant during access or precharge states (READ, WRITE, including
t
WR, and
PRECHARGE commands). CKE may be used to reduce the data rate.
7.
t
HZ defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
. The
last valid data element will meet
t
OH before going High-Z.
8. AC characteristics assume
t
T = 1ns.
9. Auto precharge mode only. The precharge timing budget (
t
RP) begins 10ns after the last WRITE is executed.
10. Precharge mode only.
11. CLK must be toggled a minimum of two times during this period.
Q
50pF
15
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 1, 2, 3, 4, 5, 6) (0C
T
A
+70C)
PARAMETER
SYMBOL
-8
UNITS NOTES
READ/WRITE command to READ/WRITE command
t
CCD
1
t
CK
7
CKE to clock disable or power-down entry mode
t
CKED
1
t
CK
8
CKE to clock enable or power-down exit setup mode
t
PED
1
t
CK
8
DQM to input data delay
t
DQD
0
t
CK
7
DQM to data mask during WRITEs
t
DQM
0
t
CK
7
DQM to data high-impedance during READs
t
DQZ
2
t
CK
7
WRITE command to input data delay
t
DWD
0
t
CK
7
Data-in to ACTIVE command
CL = 3
t
DAL
5
t
CK
9, 10
CL = 2
t
DAL
3
t
CK
9, 10
CL = 1
t
DAL
3
t
CK
9, 10
Data-in to PRECHARGE command
t
DPL
2
t
CK
10, 11
Last data-in to burst STOP command
t
BDL
1
t
CK
7
Last data-in to new READ/WRITE command
t
CDL
1
t
CK
7
Last data-in to PRECHARGE command
t
RDL
2
t
CK
10, 11
LOAD MODE REGISTER command to ACTIVE or REFRESH command
t
MRD
2
t
CK
12
Data-out to high-impedance from PRECHARGE command
CL = 3
t
ROH
3
t
CK
7
CL = 2
t
ROH
2
t
CK
7
CL = 1
t
ROH
1
t
CK
7
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range (0C
T
A
+70C) is ensured.
2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper
device operation is ensured. (V
DD
and V
DD
Q must be powered up simultaneously. V
SS
and V
SS
Q must be at the same
potential.) The two AUTO REFRESH command wake-ups should be repeated any time the
t
REF refresh requirement is
exceeded.
3. AC characteristics assume
t
T = 1ns.
4. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or
between V
IL
and V
IH
) in a monotonic manner.
5. Outputs measured at 1.5V with equivalent load:
6. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced to 1.5V crossover point.
7. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
8. Timing actually specified by
t
CKS; clock(s) specified as a reference only at minimum cycle rate.
9. Timing actually specified by
t
WR plus
t
RP; clock(s) specified as a reference only at minimum cycle rate.
10. Based on
t
CK = 125 MHz.
11. Timing actually specified by
t
WR.
12. JEDEC specifies three clocks.
Q
50pF
16
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.3
3.5
s
Time the bus must be free before a new transition can start
t
BUF
4.7
s
Data-out hold time
t
DH
300
ns
SDA and SCL fall time
t
F
300
ns
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
4
s
Clock HIGH period
t
HIGH
4
s
Noise suppression time constant at SCL, SDA inputs
t
I
100
ns
Clock LOW period
t
LOW
4.7
s
SDA and SCL rise time
t
R
1
s
SCL clock frequency
t
SCL
100
KHz
Data-in setup time
t
SU:DAT
250
ns
Start condition setup time
t
SU:STA
4.7
s
Stop condition setup time
t
SU:STO
4.7
s
WRITE cycle time
t
WRC
10
ms
2
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7 V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT:
I
SB
30
A
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
I
CC
2
mA
SCL clock frequency = 100 KHz
NOTES: 1. All voltages referenced to V
SS
.
NOTES: 1. All voltages referenced to V
SS
.
2. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to the pull-up resistor, and the EEPROM does not respond to its slave address.
17
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM
TIMING PARAMETERS
SYMBOL
MIN
MAX
UNITS
t
AA
0.3
3.5
s
t
BUF
4.7
s
t
DH
300
ns
t
F
300
ns
t
HD:DAT
0
s
t
HD:STA
4
s
SPD EEPROM
SYMBOL
MIN
MAX
UNITS
t
HIGH
4
s
t
LOW
4.7
s
t
R
1
s
t
SU:DAT
250
ns
t
SU:STA
4.7
s
t
SU:STO
4.7
s
18
2 Meg x 32 SDRAM DIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ZM36.p65 Rev. 1/00
2000, Micron Technology, Inc.
2 MEG x 32
SDRAM DIMM
100-PIN DIMM
(8MB Version)
1.005 (25.53)
.995 (25.27)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.079 (2.00) R
(2X)
3.555 (90.30)
3.545 (90.04)
PIN 1 (51 on backside)
.250 (6.35) TYP
.050 (1.27)
TYP
.118 (3.00)
TYP
.039 (1.00)
TYP
.039 (1.00) R(2X)
PIN 50 (100 on backside)
2.850 (72.39)
.125 (3.175)
MAX
.054 (1.37)
.046 (1.17)
FRONT VIEW
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
PDF 
ZIP