GENERAL DESCRIPTION

The ML6411 is a Dual Video A/D converter, incorporating
two input sample and holds, two high speed 8-Bit A/D
converters, programmable gain control, selectable clamps,
multi-phase clocking, and reference voltage generation.
The ML6411 can be used to convert the following analog
signals to digital signals: two composite channels or S-
video channel.

All inputs are provided with appropriate input selectable
clamps to establish DC level. The clamps are full DC
restore circuits with the A-to-D converters in each
respective correction loop. The clamps are selectable to
16, 24, 64, and 128. The programmable gain control
provides various possibilities to select and adjust the gain
via two separate mechanisms: Sync-Suppressed Gain
Control (SGC) for sync suppressed video such as RGB, and
User Gain Control (UGC) for video formats that require
scalable gain settings. Each of these can be programmed
through a serial bus.

FEATURES

Complete video digitizer for Y/C and CV video

Contains A/D's with scalable gain, selectable clamps,
and clock generation (programmable via serial bus)

Two 8-Bit +/- ½ LSB Differential Non-Linearity with
30MHz guaranteed conversion

Two Gain Control Mechanisms for programmable
or sync-suppressed video gain control

Selectable Video Clamping: 16, 24, 64, 128

Selectable Video Gain: 3dB to 6dB

Operating total power dissipation less than 425mW

Power down mode and Tri-state output control

Applications: Video Capture, Video Editing, Video
Cameras, Y/C and CV analog to digital conversion

44-pin TQFP

REF1

AVCC1

AVCC2

AVCC3

DVCC

VCCO

CLAMP

GATE

DGND

DVCC

RESET

OEA

OEB

VINN

SCLK

SDAT

REFIN

REFOUT

VCC

AGNDI

AGND2

AGND3

GNDO

DGND

Y/CV1

BOOSTA

GNB<5:0>

GNA<5:0>

STDB <1:0>

STDA <1:0>

CLPA<1:0>
CLPB<1:0>

CLKDIV

AOUT<7:0>

BOUT<7:0>

3:10

C/CV2

CLK

Y OR CV1

CHANNEL A

C OR CV2

CHANNEL B

TIMING

GENERATOR

BOOSTB

CV/S_MODE

BPEAK

APEAK

CLAMP

LEVEL

SELECT

SERIAL BUS

UGC

USER GAIN

CONTROL

SGC

SYNC SUPPRESS

GAIN CONTROL

GAIN PRESET

ADC

LATCH

Y/CV1

24:31

LATCH

C/CV2

ADC

UGC

USER GAIN

CONTROL

SGC

SYNC SUPPRESS

GAIN CONTROL

GAIN PRESET

S/H

CHANNEL A

S/H

CHANNEL B

September 1999

PRELIMINARY

ML6411

Programmable Video Digitizer

with Selectable Gain and Clamps

BLOCK DIAGRAM

ML6411

PIN DESCRIPTION

PIN

NAME

FUNCTION

When high, power downs the chip.
TTL compatible

Clamp Gate Luma clamp gate input. Clamps to

selected level when high. TTL
compatible

3-10 B

OUT

<7:0> Either chroma bits 7 (B

OUT

7MSB) to 0

OUT

0 LSB) or composite bits 7 (MSB)

to 0 (LSB). TTL compatible

OEB

Output enable for the BOUT channel.
Active low. TTL compatible

VCC

Reference voltage. Tie to Digital V

GNDO

Output ground pin

CLK

Clock input pin. TTL compatible

VCCO

Output supply pin

DGND

Digital ground pin

DVCC

Digital supply pin

RESET

Resets the control registers to nominal
values. Active HIGH. TTL compatible
input

SCLK

Control Bus Clock. Address latched on
rising edge, data on falling edge

SDAT

Control data

REF

Internal reference tied to REF

OUT

REF

OUT

Internal reference tied to REF

PIN

NAME

FUNCTION

OEA

Output enable for the AOUT channel.
Active high. TTL compatible

24-31 A

OUT

<7:0> Luma bit 7 (A

OUT

7 MSB) thru Luma bit

0 (A

OUT

0 LSB) outputs or Composite

bit 7 (MSB) thru Composite bit 0 (LSB)
outputs. TTL compatible

DVCC

Digital supply pin

DGND

Digital ground pin

No connection

AVCC1

Analog supply pin

Y/CV1

Y or CV (primary composite) input pin

AGND1

Analog ground pin

AVCC2

Analog supply pin

VINN

Internal common mode bias of the A/D

AGND2

Analog ground pin

AVCC3

Analog supply pin

C/CV2

C (modulated chroma) or CV (2

composite for dual channel mode)
input pin

AGND3

Analog ground pin

REF1

Internal reference. Tie this pin thru
0.1uF capacitor to analog ground for
proper operation

ML6411

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, AVCC, DVCC, VCCO = 4.5V to 5.5V, T

= Operating Temperature Range (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

POWER CONSUMPTION

diss

Max power dissipation

Cload = 0pF

425

600

SUPPLY

AVCC

Analog supply voltage

4.5

5.5

DVCC

Digital supply voltage

4.5

5.5

VCCO

Output supply voltage

4.5

5.5

IDD

Digital supply current

FCLK = 30MHz

Output supply current

FCLK=30MHz, V

=NTSC,

40IRE modulated rate, Cload=0pF

shut

Shutdown current

INPUT SIGNALS (CLK, CLAMP GATE, OEA,

OEB)

Input Low Voltage

0.8

Input High Voltage

2.4

High level Input Current

- 0.1V

-5

µA

IN1

Input Capacitance

INPUT SIGNALS (Y / CV1, C / CV2)

Input Voltage

Peak-to-peak for 2V

1.0

2.0

3.0

Peak-to-peak for 1V

0.5

1.0

1.5

IN2

Input

Capacitance

charge

Clamp Charge Current

Clamp Gate = High,

700

µA

Digital Output < Clamp level

disch

Clamp Discharge Current

Clamp Gate = High,

700

µA

Digital Output > Clamp level

A TO D CONVERTER OUTPUTS (A

OUT

<7:0>, B

OUT

<7:0>)

Low level output voltage

Io = 2mA

0.6

High level output voltage

2.4

VCCO

Leakage current

Tri-state mode

-20

µA

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

DC Supply Voltage (AVCC, DVCC, VCCO) .... -0.3V to 7V
Analog & Digital Inputs/Outputs ........ -0.3 to AVCC+0.3V
Input Current Per Pin .............................. -25mA to 25mA
Storage Temperature Range...................... 65°C to 150°C
Junction Temperature ............................................. 125°C

OPERATING CONDITIONS

Temperature Range ........................................ 0°C to 70°C
Supply Range (AVCC, DVCC, VCCO) ........... 4.5V to 5.5V

ML6411

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SWITCHING CHARACTERISTICS

FCLK

Clock input max frequency

MHz

cph

Clock input min high time

See Figure 2

cpl

Clock input min low time

See Figure 2

Clamp Gate Width

magnitude 2V max

1.5

µs

Clamp Gate Width

magnitude > 2V

3.5

µs

ANALOG SIGNAL PROCESSING

Y/C Gain Match

CGAIN1 = CGAIN2 = 0

1.01

V/V

Chroma Crosstalk

= 5MHz and C

= at DC;

or Y

= at DC and C

= 5MHz

Differential Gain

= NTSC 40 IRE modulated ramp

FCLK = 27 MHz

Differential Phase

= NTSC 40 IRE modulated ramp

degree

FCLK = 27 MHz

Signal to Noise Ratio

= 2V, 10MHz sinewave,

FCLK = 20MHz

= 2V, 10MHz sinewave,

FCLK = 30MHz

Distortion

= 2V, 10MHz, FCLK = 20MHz

0.3

SFDR

= 2V, 10MHz, FCLK = 20MHz

TRANSFER FUNCTION

DC integral linearity

@ 27MHz

±0.8

LSB

DC differential linearity

@ 27MHz

±0.5

LSB

GAIN CONTROL

RES

Gain accuracy of UGC for a given gain level

Input = 1V

P-P or

P-P

(See Note 2)

-30mV

30mV

Absolute gain error

Gain accuracy for standard preset gain,

PRESET

OUTPUT TIMING

Sampling delay

See Figure 2

Output hold time

See Figure 2

Output delay time

See Figure 2

Output enable time

See Figure 2

Output disable time

See Figure 2

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Volt Peak-to-Peak = V

P-P

ML6411

SERIAL BUS

Unless otherwise specified, AVCC, DVCC, VCCO = 4.5V to 5.5V, T

= Operating Temperature Range (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

INPUT (SDAT)

Low Level Input Voltage

0.8

High Level Input Voltage

0.8

Low Level Input Current

= 0V

1.0

High Level Input Current

= DV

1.0

Input Impedance

CLK

= 100kHz

Input Capacitance

SYSTEM TIMING (SCLK)

CLOCK

CLK

Frequency

100

kHz

HYS

Input Hysteresis

0.2

SPIKE

Spike Suppression

Max Length for Zero Response

WAIT

Wait Time From STOP to START
On S

DATA

1.3

µs

HD/START

Hold Time for START On S

DATA

0.6

µs

SU/START

Setup Time for START On S

DATA

0.6

µs

LOW

Min LOW Time On S

CLK

1.3

µs

Min HIGH Time On S

CLK

0.6

µs

HD/DATA

Hold Time On S

DATA

5.0

µs

SU/DATA

Setup Time On

Fast mode

100

Slow mode

250

Rise Time for S

CLK

& S

DATA

300

Fall Time for S

CLK

& S

DATA

300

SU/STOP

Setup Time for STOP On S

DATA

0.6

µs

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.

Note 2: All specifications include reconstruction filter and line driver.

Note 3: Normalized to burst.

ML6411

FUNCTIONAL DESCRIPTION

GENERAL

The Universal Video Digitizer is a single-chip Video A/D
converter with an analog front end which is intended for
analog to digital conversion of 2V peak-to-peak (V

P-P

) or

P-P

signals at rates up to 30 MSPS through a high

performance A/D with ±½ DNL performance. It forms a
complete solution for data conversion of dual CV and Y/C
signals including gain settings and clamp settings by
incorporating clamps, user selectable gain controls (UGC
and SGC), bias and clock generation.

The ML6411 consist of two video clamps, two sample and
hold amplifiers, two three-stage pipeline A/D converters,
digital error correction circuitry, selectable clamps,
programmable gain control, bias voltage generation and
clock generation. The operating power dissipation is
425mW typical.

INPUT FOR VARIOUS VIDEO MODES

The ML6411 can digitize various analog video inputs:
S-Video (Y/C), or composite video (CV). Again, for each
video channel, the gain and clamps can be selected.
A description of each of these modes is described
below. The Table 1 below provides a summary of the
various modes.

Dual Channel Composite Video (CV1 and CV2) Mode

The composite input channels are provided through the Y/
CV1 (A channel) and C/CV2 (B channel) pins. To activate
this mode, the CV/S_Mode Bit (Register D, Bit D3) must set
HIGH (D3=1). This mode is selectable via serial bus. In
this mode, the two S&H circuits for each channel can be
clocked up to 30MHz. Each CV channel can be then
scaled for a desired gain setting using the User Gain
Control (UGC). Standard gain selection can also be
chosen using the preset gain modes for 2V

P-P

signals only.

For 1V

P-P

signals, the preset gain selection mode is not

available; however the UGC functions can be used to
select gain values. The preset gain modes are for typical
NTSC or PAL composite video and are selectable via serial
bus through the STDA<1:0> and STDB<1:0> (Register B,
Bits B4, B3, B2, and B1) bits. When using the preset gain
mode, the output signals are enhanced by amplifying the
input signal by the value of G

PRESET

(see Table 2). In

addition, the clamp levels can be selected for either
channel for 16, 24, 64, and 128 binary levels (depending
on the channel) via the serial bus through the CLPA<1:0>
and CLPB<1:0> bits (see Table 3).

S-Video (Y / C) Mode

The input channels are provided through the Y/CV1 (A
channel) and C/CV2 (B channel) pins. To activate this
mode, the CV/S_Mode Bit (Register D, Bit D3) must be set
LOW (D3=0). This mode is selectable via serial bus. In this
mode, the two S&H circuits for each channel can be
clocked up to 30MHz. Each channel (Y and C) can be
then scaled for a desired gain setting using the User Gain

Control (UGC). Standard gain selection can also be
chosen using the preset gain modes for 2V

P-P

signals only.

For 1V

P-P

signals, the preset gain selection mode is not

available; however the UGC functions can be used to
select gain values. The preset gain modes are for typical
NTSC or PAL S-Video and are selectable via serial bus
through the STDA<1:0> and STDB<1:0> (Register B, Bits
B4, B3, B2, and B1) bits. When using the preset gain
mode, the output signals are enhanced by amplifying the
input signal by the value of G

PRESET

(see Table 2). In

addition, the clamp levels can be selected for either
channel for 16, 24, 64, and 128 binary levels (depending
on the channel 24 not available for C-channel) via the
serial bus through the CLPA<1:0> and CLPB<1:0> bits (see
Table 3).

Input Voltage Selection

The ML6411 can support 1V

P-P

and 2V

P-P

input video.

Selection for the voltage input is programmed via control
register on the APEAK and BPEAK bits, A channel and B
channel, respectively (see Table 7).

GAIN SELECTION CONTROL (UGC AND SGC)

There are two separate control mechanisms that can be
used to scale gain settings for the incoming video format:
User Gain Control (UGC) and Sync-suppressed Gain
Control (SGC).

User Gain Control (UGC)

The user gain control function is achieved through a
variation of the full scale range of the A/D converters. This
will provide the user with approximately +/-3dB gain
variation as needed. Y reference and C reference are
supplied by two independent DACs. The user can adjust
the gain of each ADC independently providing the 6-Bit
code for the gain control through serial interface for each
A/D. Each step change can increment or decrement the
gain by 3% and allows for up to 64 different gain setting
levels per channel. The UGC can be used for both 1V and
2V

P-P

inputs. When using the UGC mode, the output

signals are enhanced by amplifying the input signal by the
value of G

UGC

. Table 4 provides a summary of the possible

incremental ranges. The gain accuracy of the UGC for
each of the 64 levels is +/-1.5%. The UGC gain settings
are selected via serial bus by programming Registers C, D,
and E on the GNA<5:0> bits for the A-channel and
GNB<5:0> bits for the B-channel.

Unity gain is set at default for GNA<5:0> = 100,000 and
GNB<5:0> = 100,000. For values of GNA<5:0> and
GNB<5:0> from 100,000 to 111,111, the gain increases
monotonically from 0dB (unity gain) to almost 3dB
(actually 1.48x), while from 100,000 to 000,000 the gain
decreases monotonically from 0dB (unity gain) to 3dB
(0.5x). Note that Table 4 provides only approximation of
gain values: actual gain values can vary from device to
device.

ML6411

Sync-suppress Gain Control (SGC)

This control function is used for video where the sync
signal is suppressed (i.e., chroma signal). In which case,
the SGC can be activated to provide a 25% gain boost to
each channel (Y and C). The SGC is activated via serial bus
(Register D, Bits D1 and D2), also called the BOOSTA and
BOOSTB programming bits. In the SGC mode, the output
signals are enhanced by amplifying the input signal by the
value of G

SGC

(see Table 5).

Using The Gain Control Blocks Together

The UGC combined provides digital gain control data to a
variable gain control circuit while the SGC is directly in
the A/D processing path. Hence the UGC sets variable
gain control of the A/D.

When the UGC and the SGC are enabled. In this mode,
the output gain is the combination of the different gain
setting mechanisms:

For 1V

P-P

signals,

Equation 1: Output Gain = [<Input Signal> x
G

UGC

x G

SGC

] + Clamp Level

For 2V

P-P

signals,

Equation 2: Output Gain = [<Input Signal> x
G

UGC

x G

SGC

x G

PRESET

] + Clamp Level

Note that separate G

UGC

, G

SGC

, and G

PRESET

values are

available for both channels A and B. There are up to 640
combinations of gain settings possible.

WARNING

Note that it is possible to exceed the output voltage ranges
for standard video using the combination of the gain
setting mechanisms on the input signal. The user should
take precaution in understanding the gain limits necessary
and make the proper selection for each of the gain
mechanism.

A/D CONVERTER

The A/D conversion is performed via a three stage pipeline
architecture. The first two stages quantize their input signal
to the three bits, then subtract the result from the input and
amplify by a factor of four. This creates a residue signal
which spans the full scale range of the following converter.
The subtraction and amplification is performed via a
bottom plate sampling capacitor feedback amplifier,
similar to the input sample and hold. The third stage
quantizes the signal to four bits. One bit from each of the
last two stages is used for error correction.

The first stage A/D performs the conversion at the end of
the sample and holds period, approximately one-half

cycle later, after the subtraction/amplification of the first
stage has settled. The third stage A/D performs the
conversion after another one-half cycle delay, when the
second stage has settled. Error correction is then
performed and, one clock cycle later, data is transferred to
the output latch. This creates a 3 clock latency.

INPUT SAMPLE AND HOLD

The input sample and hold consist of a bottom plate
sampling capacitor feedback amplifier. The input
capacitance is 0.4pF, plus transmission gate. The input to
the sample and hold is driven differentially. The sample
and hold samples the input signal during the positive half
cycle of the input clock, and holds the last value of the
input during the negative half cycle of the input clock. The
settling time of the amplifier is less than 10nS.

INPUT COUPLING AND DC CLAMP PROGRAM
SELECTION

All inputs are AC coupled into the positive sampling
capacitor of the sample and hold. Each input capacitor
becomes the integrating component for the DC restore
clamps. The direction of clamp current depends on the
data at the A/D output during the clamp gating pulse. For
the color channel (i.e. C in Y/C mode) the clamp level is
128. If the code is above this number during the gate
pulse, the current source will sink current from the input
capacitor in order to drive the input voltage lower.
Otherwise, the current source will source current to raise
the input voltage. Clamp currents are shown in Table 6.

The clamp values of 16, 24, 64, 128 can be select via
register program (Register A and B) through the serial bus.
Note that there is no Level 24 in the B channel. The
CLPA<1:0> controls the clamp settings for the
A-channel, while the CLPB<1:0> controls the clamp
settings for the B-channel. For example, clamp values can
be selected independently for the chroma channel in Y/C
mode (CLPB<1:0>). Once the clamp settings are selected,
the clamps are active when the ClampGate is asserted
HIGH. The ClampGate signal is an external signal provided
by a genlock/sync clock device that is genlocked to the
horizontal sync of the video input. The ML6431 can be used
to generate the ClampGate signal (see Application Section).

SERIAL PROGRAM

The ML6411 can be register programmed through the
serial bus. Clamping and gain setting can be selected for
various video formats. This serial bus is a standard three-
pin interface with data, clock, and ground. See Timing
Control information. Table 7 provides a description the
Register information. Please see section "Input Coupling
and DC Clamp Program Selection" and "Gain Select
Control".

FUNCTIONAL DESCRIPTION

(Continued)

ML6411

RESET DEFAULT MODE

The ML6411 provides a RESET pin that programs the
Control Registers as described in Table 8. The RESET pin is
active HIGH. Basically, the ML6411 on RESET defaults to:

S-Video mode. Ideally, for PAL S-Video since Preset
Mode (STDA and STDB bits) is set to unity gain boost
(G

PRESET

= 1) for both Y and C (see Table 2)

Y is clamped to 16. C is clamped to 128 (see Table 3)
and CLPA and CLPB bits)

Table 1. Various Video Modes Using the ML6411 and Key Features

FUNCTIONAL DESCRIPTION

(Continued)

UGC is set to unity gain (G

UGCA

= 1 and G

UGCB

= 1) to

either Y or C channels (see Table 4 and GNA and GNB
bits)

Input pin are set for 2V

P-P

inputs on both Y and C

MODE

REGISTER/BIT VALUES

CHANNEL

SIGNAL

INPUT

OUPUT

OPTIONS

Dual CV Register D,

CV1

Y/CV1 pin

OUT<7:0>

Gain Control Selection

Bit D3= CV/S_Mode =1

(UGC, SGC) and Clamp
Selection.
1V

P-P or

P-P

inputs.

Serial Bus Programable.

CV2

C/CV2 pin

OUT<7:0>

S-Video

Y/CV1 pin

OUT<7:0>

Gain Control Selection

Bit D3= CV/S_Mode =0

(UGC, SGC) and Clamp
Selection.
1V

P-P or

P-P

inputs.

Serial Bus Programable.

C/CV2 pin

OUT<7:0>

Note: Volt Peak-to-Peak = V

P-P

ML6411

Table 2. Video Standard Preset Gain Selection Modes

S-VIDEO MODE

TYPICAL INPUTS

GAIN SELECTION

GAIN FACTOR OF

OF AMPLIFIERS

AMPLIFIERS (nominal)

Channel A

Channel B

Channel A

Channel B

Channel A

Channel B

STANDARD

Y Input (mV)

C Input (mV)

STDA<1:0>

STDB<1:0>

PRESETA

PRESETB

S-Video NTSC

1320

1.061

S- Video PAL

1400

Preset Mode 1

1320

1.061

0.7495

Preset Mode 2

1428

1.02

Preset Mode 3

1400

0.7495

Preset Mode 4

1294

1.082

DUAL COMPOSITE VIDEO MODE

TYPICAL INPUTS

GAIN SELECTION

GAIN FACTOR OF

OF AMPLIFIERS

AMPLIFIERS (nominal)

Channel A

Channel B

Channel A

Channel B

Channel A

Channel B

STANDARD

CV1 Input (mV)

CV2 Input (mV)

STDA<1:0>

STDB<1:0>

PRESETA

PRESETB

Composite Video NTSC

1320

1.061

Composite Video PAL

1400

Preset Mode 1

1320

1.061

0.7495

Preset Mode 2

1428

1.02

Preset Mode 3

1400

0.7495

Preset Mode 4

1294

1.082

ML6411

Table 4. Gain Approximations for User Gain Control (UGC) Block

A-CHANNEL

GNA5 GNA4 GNA3 GNA2 GNA1 GNA0

GAIN

FACTOR

UGCA

(NOMINAL)

0.50

0.52

0.53

0.55

0.56

0.58

0.59

0.61

0.63

0.64

0.66

0.67

0.69

0.70

0.72

0.73

0.75

0.77

0.78

0.80

0.81

0.83

0.84

0.86

0.88

0.89

0.91

0.92

0.94

0.95

0.97

0.98

1.00

1.02

1.03

1.05

1.06

1.08

1.09

1.11

1.13

1.14

1.16

1.17

1.19

1.20

1.22

1.23

1.25

1.27

1.28

1.30

1.31

1.33

1.34

1.36

1.38

1.39

1.41

1.42

1.44

1.45

1.47

1.48

B-CHANNEL

GNB5 GNB4 GNB3 GNB2 GNB1 GNB0

GAIN

FACTOR

UGCB

(NOMINAL)

0.50

0.52

0.53

0.55

0.56

0.58

0.59

0.61

0.63

0.64

0.66

0.67

0.69

0.70

0.72

0.73

0.75

0.77

0.78

0.80

0.81

0.83

0.84

0.86

0.88

0.89

0.91

0.92

0.94

0.95

0.97

0.98

1.00

1.02

1.03

1.05

1.06

1.08

1.09

1.11

1.13

1.14

1.16

1.17

1.19

1.20

1.22

1.23

1.25

1.27

1.28

1.30

1.31

1.33

1.34

1.36

1.38

1.39

1.41

1.42

1.44

1.45

1.47

1.48

ML6411

REGISTER INFORMATION AND ORGANIZATION

REGISTER ADDRESS

DATA BIT

NAME

DESCRIPTION

BIT CODE RANGE

000

CLPA0

Sets Clamp Level for the A Channel

See Table 3

CLPA1

Sets Clamp Level for the A Channel

See Table 3

Reserved

Don't Care

Reserved

Don't Care

CLPB0

Sets Clamp Level for the B Channel

See Table 3

001

CLPB1

Sets Clamp Level for the B Channel

See Table 3

STDB0

Selects Standard Preset Gain Level for B Channel

See Table 2

STDB1

Selects Standard Preset Gain Level for B Channel

See Table 2

STDA0

Selects Standard Preset Gain Level for A Channel

See Table 2

STDA1

Selects Standard Preset Gain Level for A Channel

See Table 2

010

GNA0