DESCRIPTION
I Guaranteed AC performance
> 2.0GHz F
MAX
output toggle
> 3.0GHz F
MAX
input
< 800ps T
pd
(matched-delay between banks)
< 15ps within-device skew
< 190ps rise/fall time
I Low jitter design
< 1ps (rms) cycle-to-cycle jitter
< 10ps (pk-pk) total jitter
I Unique input termination and V
T
pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
I Precision differential LVDS outputs
I Matched delay: all outputs have matched delay,
independent of divider setting
I TTL/CMOS inputs for select and reset/disable
I Two LVDS output banks (matched delay)
Bank A: Buffered copy of input clock (undivided)
Bank B: Divided output (
2,
4,
8,
16),
two copies
I 3.3V power supply
I Wide operating temperature range: 40
C to +85
C
I Available in 16-pin (3mm 3mm) MLFTM package
FEATURES
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER/FANOUT
BUFFER W/ INTERNAL TERMINATION
Precision EdgeTM
SY89873L
FINAL
APPLICATIONS
I SONET/SDH line cards
I Transponders
I High-end, multiprocessor servers
1
Rev.: B
Amendment: /1
Issue Date:
February 2003
This 3.3V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC- or
DC-coupled) CML, LVPECL, HSTL or LVDS and divides down
the frequency using a programmable divider ratio to create a
frequency-locked, lower speed version of the input clock. The
SY89873L includes two output banks. Bank A is an exact
copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank. Available
divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz,
77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a V
T
pin. This feature allows the device to easily interface to
all AC- or DC-coupled differential logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The SY89873L is part of Micrel's high-speed Precision
EdgeTM timing and distribution family. For 2.5V applications,
consider the SY89872U. For applications that require an
LVPECL output, consider the SY89871U.
The /RESET input asynchronously resets the divider outputs
(Bank B). In the pass-through function (Bank A) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N). Refer to the Timing
Diagram.
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATION
Precision Edge is a trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
IN
50
50
/IN
S0
S1
QB1
/QB1
QB0
/QB0
QA
/QA
/RESET
V
T
V
REF-AC
Divided
by
2, 4, 8
or 16
Decoder
Enable
FF
Enable
MUX
IN
/IN
QA
/QA
622MHz LVDS
Clock Out
622MHz LVPECL
Clock In
622MHz/155.5MHz
SONET Clock Generator
Bank B: 155.5MHz: For OC-3 line card
Set to divide-by-4
Bank A: 622MHz: For OC-12 line card
Set to pass-through
155.5MHz LVDS
Clock Out
OC-12 or
OC-3
Clock Gen
QB
/QB
Precision EdgeTM
2
Precision EdgeTM
SY89873L
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY89873LMI
MLF-16
Industrial
873L
SY89873LMITR*
MLF-16
Industrial
873L
*Tape and Reel
Pin Number
Pin Name
Pin Function
1, 2, 3, 4
QB0, /QB0
Differential Buffered Output Clocks: Divide by 2, 4, 8, 16.
QB1, /QB1
LVDS compatible.
5, 6
QA, /QA
Differential Buffered Undivided Output Clock: LVDS compatible.
7, 14
VCC
Positive Power Supply: Bypass with 0.1
F//0.01F low ESR capacitors.
8
/RESET, /DISABLE
TTL/CMOS Compatible Output Reset and Disable: Internal 25k
pull-up. Input threshold
is V
CC
/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In
addition, when LOW, Banks A and B will be disabled.
9, 12
IN, /IN
Differential Input: Internal 50
termination resistors to V
T
input.
See "Input Interface Applications" section.
10
VREF-AC
Reference Voltage: Equal to V
CC
1.4V (approx.), and used for AC-coupled applications.
Maximum sink/source current is 0.5mA. See "Input Interface Applications" section.
11
VT
Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise,
see "Input Interface Applications" section.
13
GND
Ground: Exposed pad is internally connected to GND and must be connected to a ground
plane for proper thermal operation.
15, 16
S0, S1
Select Pins: LVTTL/CMOS logic levels. Internal 25k
pull-up resistor. Logic HIGH if left
unconnected (divided by 16 mode). S0 = LSB. Input threshold is V
CC
/2.
PIN DESCRIPTION
1
2
3
4
12
11
10
9
16 15 14 13
5
6
7
8
QB0
/QB0
QB1
/QB1
IN
VT
VREF-AC
/IN
GND
VCC
S1
S0
/RESET
,
/DISABLE
VCC
/QA
QA
16-Pin MLFTM
/RESET
S1
S0
Bank A Output
Bank B Outputs
/DISABLE
1
0
0
Input Clock
Input Clock
2
1
0
1
Input Clock
Input Clock
4
1
1
0
Input Clock
Input Clock
8
1
1
1
Input Clock
Input Clock
16
0
X
X
QA = LOW, /QA = HIGH
(1)
QB0 = LOW, /QB0 = HIGH
(2)
QB1 = LOW, /QB1 = HIGH
(2)
Note 1.
On the next negative transition of the input signal.
Note 2.
Asynchronous Reset/Disable function. See "Timing Diagram."
TRUTH TABLE
3
Precision EdgeTM
SY89873L
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) .................................. 0.5V to +4.0V
Input Voltage (V
IN
) .................................. 0.5V to V
CC
+0.3
LVDS Output Current (I
OUT
) ....................................
10mA
Input Current IN,
/IN (I
IN
) ..........................................
50mA
V
REF-AC
Input Sink/Source Current (I
VREF-AC
),Note 3 .
2mA
Lead Temperature (soldering, 10 sec.) ..................... 220
C
Storage Temperature (T
S
) ....................... 65
C to +150C
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) ...................................... +3.3V
10%
Ambient Temperature (T
A
) ......................... 40
C to +85C
Package Thermal Resistance
MLFTM
(
JA
)
Still-Air ............................................................. 60
C/W
500 lfpm ........................................................... 54
C/W
MLFTM
(
JB
), Note 4
Junction-to-Board ............................................ 32
C/W
T
A
= 40
C to +85C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply
3.0
3.3
3.6
V
I
CC
Power Supply Current
No load, Max V
CC
85
115
mA
R
IN
Differential Input Resistance
80
100
120
IN, /IN
V
IH
Input High Voltage
Note 2
0.1
V
CC
+0.3
V
IN, /IN
V
IL
Input Low Voltage
Note 2
0.3
V
CC
+0.2
V
IN, /IN
V
IN
Input Voltage Swing
Notes 2, 3
0.1
3.6
V
V
DIFF_IN
Differential Input Voltage Swing
Notes 2, 3, 4
0.2
V
|I
IN
|
Input Current
Note 2
45
mA
IN, /IN
V
REF-AC
Reference Voltage
Note 5
V
CC
1.525 V
CC
1.425 V
CC
1.325
V
Note 1.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2.
Specification for packaged product only.
Note 3.
Due to the internal termination (see
"Input Buffer Structure" ) the input current depends on the applied voltages at IN, /IN and V
T
inputs.
Do not apply a combination of voltages that causes the input current to exceed the maximum limit!
Note 4.
See
"Timing Diagram" for V
IN
definition. V
IN(MAX)
is specified when V
T
is floating.
Note 5.
See Figures 1c and 1d for V
DIFF
definition.
Note 6.
Operating using V
IN
is limited to AC-coupled PECL or CML applications only. Connect directly to V
T
pin.
DC ELECTRICAL CHARACTERISTICS
(Notes 1,
2)
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3.
Due to the limited drive capability use for input of the same package only.
Note 4.
Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
4
Precision EdgeTM
SY89873L
Micrel
V
CC
= 3.3V
10%; T
A
= 40
C to +85C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
I
IH
Input HIGH Current
125
20
A
I
IL
Input LOW Current
300
A
Note 1.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2.
Specification for package product only.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
V
CC
= 3.3V
10%; T
A
= 40
C to +85C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OUT
Output Voltage Swing
Notes 3, 4
250
350
450
mV
V
OH
Output High Voltage
Note 3
1.475
V
V
OL
Output Low Voltage
Note 3
0.925
V
V
OCM
Output Common Mode Voltage
Note 3
1.125
1.275
V
V
OCM
Change in Common Mode Voltage
50
50
mV
Note 1.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2.
Specification for package product only.
Note 3.
Measured as per Figure 1a, 100
across Q and /Q outputs.
Note 4.
See Figure 1c.
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
5
Precision EdgeTM
SY89873L
Micrel
V
CC
= 3.3V
10%; T
A
= 40
C to +85C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Output Toggle Frequency
Output Swing:
200mV
2.0
GHz
(Bank A and Bank B)
Maximum Input Frequency
Note 3
3.2
GHz
t
PD
Differential Propagation Delay
Input Swing < 400mV
550
660
800
ps
(IN-to-Q)
Input Swing
400mV
500
610
750
ps
t
SKEW
Within-Device Skew (diff.)
Note 4
7
15
ps
(QB0-to-QB1)
Within-Device Skew (diff.)
Note 4
12
30
ps
(Bank A-to-Bank B)
Part-to-Part Skew (diff.)
Note 4
250
ps
t
rr
Reset Recovery Time
Note 5
600
ps
T
jitter
Cycle-to-Cycle Jitter
Note 6
1
ps(rms)
Total Jitter
Note 7
10
ps(pk-pk)
t
r
, t
f
Rise / Fall Time (20% to 80%)
60
110
190
ps
Note 1.
Measured with 400mV input signal, 50% duty cycle. All outputs terminated with 100
between Q and /Q, unless otherwise stated.
Note 2.
Specification for package product only.
Note 3.
Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output
2, 4, 8, 16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
Note 4.
Skew is measured between outputs under identical transitions.
Note 5.
See
"Timing Diagram."
Note 6.
Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
jitter_cc
=T
n
T
n+1
,
where T is the time between rising edges of the output signal.
Note 7.
Total jitter definition: with an ideal clock input, of frequency
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
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