SY89835U
2.5V, 2GHz (3.2 Gbps) Ultra-Precision,
Differential 1:2 LVDS Fanout Buffer with
Internal Termination and Fail Safe Input
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
Micro
LeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
February 2006
M9999-020706
hbwhelp@micrel.com
or (408) 955-1690
General Description
The SY89835U is a 2.5V, high-speed 2GHz differential
Low Voltage Differential Swing (LVDS) 1:2 fanout buffer
optimized for ultra-low skew applications. Within device
skew is guaranteed to be less than 20ps over supply
voltage and temperature. A unique Fail-Safe Input (FSI)
protection prevents metastable conditions when no
signal is present or when the selected input clock fails to
a DC voltage (voltage between the pins of the
differential input drops sufficiently below 100 mV).
The SY89835U is part of Micrel's high-speed clock
synchronization family. For applications that require a
different I/O combination, consult Micrel's web site, and
choose from a comprehensive product line of high-
speed, low-skew fanout buffers, translators and clock
generators.
Data sheets and support documentation can be found
on Micrel's web site at:
www.micrel.com
.
Functional Block Diagram
Precision Edge
Features
Guaranteed AC performance over temperature and
voltage:
DC-to > 3.2Gbps throughput
210ps typical propagation delay (IN-to-Q)
<20ps within-device skew
<150ps rise/fall times
Fail Safe Input
Prevents outputs from oscillating
Ultra-low jitter design
<1ps
RMS
cycle-to-cycle jitter
<10ps
PP
total jitter
<1ps
RMS
random jitter
<10ps
PP
deterministic jitter
High-speed LVDS outputs
2.5V 5% power supply operation
Industrial temperature range: 40C to +85C
Available in 8-pin (2mm x 2mm) MLFTM package
Applications
Clock or data distribution
SONET clock or data distribution
Fibre Channel clock or data distribution
Gigabit Ethernet clock or data distribution
Markets
DataCom
Telecom
Storage
ATE
Precision test and measurement
Micrel, Inc.
SY89835U
February 2006
2
M9999-020706
hbwhelp@micrel.com
or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY89835UMG MLF-8
Industrial
835 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY89835UMGTR
(2)
MLF-8 Industrial 835 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only.
2. Tape
and
Reel.
Pin Configuration
8-Pin MLFTM (MLF-8)
Pin Description
Pin Number
Pin Name
Pin Function
1 VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitor and place as
close to VCC pin as possible. Power supply tolerance is 5%.
2, 3
IN, /IN
Differential Inputs: This input pair is the differential signal input to the device. Input
accepts DC-Coupled differential signals as small as 100mV
(200mV
PP
). The input is
internally terminated with 100 between IN and /IN. If the input swing falls below a
certain threshold (typically 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the output to its last valid state. Please refer to the "Input
Interface Applications" section for more details.
4 GND
Ground. GND pins and exposed pad must be connected to the most negative
potential of the device ground.
5, 6
7, 8
/Q1, Q1
/Q0, Q0
Differential Outputs (LVDS): Normally terminated with 100 across the pair (Q, /Q).
See "LVDS Outputs" section, Figure 2a.
Truth Table
IN /IN Q /Q
0 1 0 1
1 0 1 0
Micrel, Inc.
SY89835U
February 2006
3
M9999-020706
hbwhelp@micrel.com
or (408) 955-1690
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ............................... 0.5V to +4.0V
Input Voltage (V
IN
) ............................ 0.5V to V
CC
+0.3V
LVDS Output Current (I
OUT
)..................................10mA
Input Current
Source or Sink Current on (IN, /IN) ...............50mA
Lead Temperature (soldering, 20sec.) .................. 260C
Storage Temperature (T
s
) ....................65C to +150C
Operating Ratings
(2)
Supply Voltage (V
IN
)...................... +2.375V to +2.635V
Ambient Temperature (T
A
) ................... 40C to +85C
Package Thermal Resistance
(3)
MLFTM
Still-air (
JA
)........................................... 93C/W
Junction-to-board (
JB
) ......................... 32C/W
DC Electrical Characteristics
(4)
T
A
= 40C to +85C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
V
CC
Power Supply Voltage Range
2.375
2.5
2.625
V
I
CC
Power Supply Current
No load, max. V
CC
50
70
mA
R
DIFF_IN
Differential Input Resistance
(IN-to-/IN)
90
100
110
V
IH
Input HIGH Voltage
(IN, /IN)
1.2
V
CC
V
V
IL
Input LOW Voltage
(IN, /IN)
0
V
IH
0.1 V
V
IN
Input Voltage Swing
(IN, /IN)
see Figure 2c
0.1
V
CC
V
V
DIFF_IN
Differential Input Voltage Swing
(|IN - /IN|)
see Figure 2d
0.2
V
V
IN_FSI
Input Voltage Threshold that
Triggers FSI
30
100
mV
LVDS Outputs DC Electrical Characteristics
(4)
V
CC
= +2.5V 5%, R
L
= 100 across the outputs; T
A
= 40C to +85C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
V
OUT
Output Voltage Swing
See Figure 2c
250
325
mV
V
DIFF_OUT
Differential Output Voltage Swing
See Figure 2d
500 650 mV
V
OCM
Output Common Mode Voltage
1.125 1.20 1.275 V
V
OCM
Change in Common Mode
Voltage
50
50
mV
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
JB
and
JA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Micrel, Inc.
SY89835U
February 2006
4
M9999-020706
hbwhelp@micrel.com
or (408) 955-1690
AC Electrical Characteristics
(5)
V
CC
= +2.5V 5%, R
L
= 100 across the outputs; T
A
= 40C to +85C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
V
OUT
> 200mV NRZ Data
3.2
Gbps
f
MAX
Maximum
Frequency
Clock 2.0 3.0
GHz
t
PD
Propagation Delay IN-to-Q V
IN
: 100mV-200mV
> 200mV
150
100
300
210
500
400
ps
Within Device Skew
Note 6
5
20
ps
t
Skew
Part-to-Part Skew
Note 7
200
ps
Data Random Jitter
Note 8
1
ps
RMS
Deterministic Jitter
Note 9
10
ps
PP
Clock Cycle-to-Cycle Jitter Note 10
1
ps
RMS
t
Jitter
Total Jitter
Note 11
10
ps
PP
t
r,
t
f
Output Rise/Fall Times
(20% to 80%)
At full output swing.
40
75
150
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
5.
High-frequency AC parameters are guaranteed by design and characterization.
6.
Within device skew is measured between two different outputs under identical input transitions.
7.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
8.
Random jitter is measured with a K28.7 pattern, measured at f
MAX
.
9.
Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
1 PRBS pattern.
10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
T
n+1
,
where T is the time between rising edges of the output signal.
11. Total jitter definition: with an ideal clock input frequency of f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
Micrel, Inc.
SY89835U
February 2006
5
M9999-020706
hbwhelp@micrel.com
or (408) 955-1690
Functional Description
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or
when the amplitude of the input signal drops
sufficiently below 100mV
PK
(200mV
PP
).
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output
signal. No ringing and no undetermined state will
occur at the output under these conditions.
Please note that the FSI function will not prevent duty
cycle distortion in case of a slowly deteriorating (but
still toggling) input signal. Due to the FSI function, the
propagation delay will depend upon the rise and fall
time of the input signal and on its amplitude. Refer to
"Typical Operating Characteristics" for detailed
information.
Timing Diagrams
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