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Электронный компонент: SY89832UMITR

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1
Precision Edge
SY89832U
Micrel, Inc.
M9999-092005
hbwhelp@micrel.com or (408) 955-1690
September 2005
DESCRIPTION
s
Guaranteed AC performance over temperature
and voltage:
DC-to >2.0GHz throughput
<570ps propagation delay (IN-to-Q)
<20ps within-device skew
<200ps rise/fall time
s
Ultra-low jitter design:
<1ps
RMS
cycle-to-cycle jitter
<1ps
RMS
random jitter
<10ps
PP
deterministic jitter
<10ps
PP
total jitter (clock)
s
Unique, patent-pending input termination and VT pin
accepts DC and ACcoupled inputs
s
High-speed LVDS outputs
s
2.5V voltage supply operation
s
Industrial temperature range: 40
C to +85
C
s
Available in 16-pin (3mm


3mm) MLFTM package
FEATURES
2.5V ULTRA-PRECISION 1:4 LVDS
FANOUT BUFFER/TRANSLATOR
WITH INTERNAL TERMINATION
Precision Edge
SY89832U
APPLICATIONS
s
Processor clock distribution
s
SONET clock distribution
s
Fibre Channel clock distribution
s
Gigabit Ethernet clock distribution
1
The SY89832U is a 2.5V, high-speed, 2GHz differential
LVDS (Low Voltage Differential Swing) 1:4 fanout buffer
optimized for ultra-low skew applications. Within device skew
is guaranteed to be less than 20ps over supply voltage and
temperature.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREFAC
reference output is included for AC-coupled applications.
The SY89832U is a part of Micrel's high-speed clock
synchronization family. For 3.3V applications, see SY89833L.
For applications that require a different I/O combination,
consult Micrel's website at www.micrel.com, and choose
from a comprehensive product line of high-speed, low-skew
fanout buffers, translators and clock generators.
TYPICAL PERFORMANCE
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
622MHz Output
TIME (200ps/div.)
Output Swing
(75mV/div
.
)
IN
/IN
D
Q
Q3
/Q3
Q2
/Q2
Q1
/Q1
Q0
/Q0
EN
(LVTTL/CMOS)
VT
50
50
VREF-AC
1:4
Precision Edge
FUNCTIONAL BLOCK DIAGRAM
2
Precision Edge
SY89832U
Micrel, Inc.
M9999-092005
hbwhelp@micrel.com or (408) 955-1690
September 2005
IN
/IN
EN
Q
/Q
0
1
1
0
1
1
0
1
1
0
X
X
0
0
(1)
1
(1)
Note 1.
On next negative transition of the input signal (IN).
TRUTH TABLE
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89832UMI
MLF-16
Industrial
832U
Sn-Pb
SY89832UMITR
(2)
MLF-16
Industrial
832U
Sn-Pb
SY89832UMG
(3)
MLF-16
Industrial
832U with Pb-Free
NiPdAu
bar line indicator
Pb-Free
SY89832UMGTR
(2, 3)
MLF-16
Industrial
832U with Pb-Free
NiPdAu
bar line indicator
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25
C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number
Pin Name
Pin Function
15, 16
Q0, /Q0
LVDS Differential (Outputs): Normally terminated with 100
across the pair (Q, /Q). See "LVDS
1, 2
Q1, /Q1
Outputs" section, Figure 2a. Unused outputs should be terminated with a 100
resistor across
3, 4
Q2, /Q2
each pair.
5, 6
Q3, /Q3
8
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25k
pull-up resistor and will default
to logic HIGH state (enabled) if left open.
9, 12
/IN, IN
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50
. Note that these inputs will default to an intermediate state if
left open. Pleae refer to the "Input Interface Applications" section for more details.
10
VREFAC
Reference Voltage: These outputs bias to V
CC
1.4V. They are used when AC coupling the
inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with
0.01
F low ESR capacitor to V
CC
. See "Input Interface Applications" section for more details.
Maximum sink/source current is
1.5mA. Due to the limited drive capability, each VREF-AC pin
is only intended to drive its respective VT pin.
11
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input
Interface Applications" section for more detaiils.
13
GND
Ground. GND pins and exposed pad must be connected to the most negative potential of the
device ground.
7, 14
VCC
Positive Power Supply: Bypass with 0.1
F//0.01
F low ESR capacitors and place as close to
each VCC pin as possible.
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
Q1
/Q1
Q2
/Q2
IN
VT
VREF-AC
/IN
/Q0
Q0
VCC
GND
Q3
/Q3
VCC
EN
16-Pin MLFTM (MLF-16)
3
Precision Edge
SY89832U
Micrel, Inc.
M9999-092005
hbwhelp@micrel.com or (408) 955-1690
September 2005
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .................................. 0.5V to +4.0V
Input Voltage (V
IN
) ............................... 0.5V to V
CC
+0.3V
LVDS Output Current (I
OUT
) ....................................
10mA
Input Current
Source or Sink Current on (IN, /IN) ..................
50mA
VREF-AC Current
Source or Sink Current on (I
VT
) ..........................
2mA
Lead Temperature (soldering, 20sec.) ...................... 260
C
Storage Temperature (T
S
) ....................... 65
C to +150
C
Operating Ratings
(2)
Supply Voltage Range .......................... +2.375V to 2.625V
Ambient Temperature (T
A
) ......................... 40
C to +85
C
Package Thermal Resistance
(3)
MLFTM
(
JA
) Still-Air ........................................................ 60
C/W
(
JB
) .................................................................... 32
C/W
T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply
2.375
2.5
2.625
V
I
CC
Power Supply Current
No load, max. V
CC
.
75
100
mA
R
IN
Input Resistance (IN-to-VT)
45
50
55
R
DIFF-IN
Differential Input Resistance
(IN-to-/IN)
80
100
120
V
IH
Input HIGH Voltage (IN, /IN)
Note 5
V
CC
1.6
V
CC
V
V
IL
Input LOW Voltage (IN, /IN)
0
V
IH
0.1
V
V
IN
Input Voltage Swing (IN, /IN)
see Figure 2c.
0.1
1.7
V
V
DIFF_IN
Differential Input Voltage Swing
|IN /IN|
see Figure 2d.
0.2
V
V
REFAC
Output Reference Voltage
V
CC
1.525 V
CC
1.425 V
CC
1.325
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
JB
and
JA
values
are determined for a 4-layer board in stil-air number, unless otherrwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V
IH
(min) not lower than 1.2V.
DC ELECTRICAL CHARACTERISTICS
(4)
4
Precision Edge
SY89832U
Micrel, Inc.
M9999-092005
hbwhelp@micrel.com or (408) 955-1690
September 2005
V
CC
= 2.5V
5%, R
L
= 100
across the outputs; T
A
= 40
C to +85
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OUT
Output Voltage Swing
See Figure 2c.
250
325
mV
V
DIFF_OUT
Differential Output Voltage Swing
See Figure 2d.
500
650
mV
V
OCM
Output Common Mode Voltage
1.125
1.275
V
V
OCM
Change in Common Mode Voltage
50
50
mV
V
CC
= 2.5V
5%, T
A
= 40
C to +85
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
V
CC
V
V
IL
Input LOW Voltage
0
0.8
V
I
IH
Input HIGH Current
125
30
A
I
IL
Input LOW Current
300
A
Notes:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS
(6)
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(6)
5
Precision Edge
SY89832U
Micrel, Inc.
M9999-092005
hbwhelp@micrel.com or (408) 955-1690
September 2005
TIMING DIAGRAM
t
S
IN
t
pd
t
H
EN
V
CC
/2
V
OUT
V
CC
/2
V
IN
/IN
/Q
Q
V
CC
= +2.5V
5% or +3.3V
10%; R
L
= 100
across the outputs; T
A
= 40
C to +85
C unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Frequency
V
OUT
200mV
2.0
2.5
GHz
t
pd
Propagation Delay
IN-to-Q
V
IN
< 400mV
370
470
570
ps
IN-to-Q
V
IN
400mV
300
410
500
ps
t
SKEW
Within-Device Skew
Note 8
5
20
ps
Part-to-Part Skew
Note 9
200
ps
t
S
Set-Up Time
EN to IN, /IN
Note 10
300
ps
t
H
Hold Time
EN to IN, /IN
Note 10
300
ps
t
JITTER
Data
Random Jitter (RJ)
Note 11
1
ps
RMS
Deterministic Jitter (DJ)
Note 12
10
ps
PP
Clock
Cycle-to-Cycle Jitter
Note 13
1
ps
RMS
Total Jitter (TJ)
Note 14
10
ps
PP
t
r
,
t
f
Output Rise/Fall Times
At full output swing.
70
150
225
ps
(20% to 80%)
Notes:
7.
High-frequency AC parameters are guaranteed by design and characterization.
8.
Within device skew is measured between two different outputs under identical input transitions.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold times do not apply.
11. Random jitter is measured with a K28.7 pattern, measured at
f
MAX
.
12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
1 PRBS pattern.
13. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs.
t
JITTER_CC
= T
n
T
n+1
, where T is the time between rising edges of the output signal.
14. Total jitter definition: with an ideal clock input frequency of
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
(7)