Pin

Function

HSTL_CLK, /HSTL_CLK

Differential HSTL Inputs

LVPECL_CLK, /LVPECL_CLK

Differential LVPECL Inputs

CLK_SEL

Input CLK Select (LVTTL)

Output Enable (LVTTL)

-Q

, /Q

-/Q

Differential HSTL Outputs

GND

Ground

CCI

Core

CCO

Output

FEATURES

3.3V core supply, 1.8V output supply for reduced
power

LVPECL and HSTL inputs

22 differential HSTL (low-voltage swing) output pairs

HSTL outputs drive 50

to ground with no offset

voltage

Low part-to-part skew (200ps max.)

Low pin-to-pin skew (50ps max.)

Available in a 64-Pin EPAD HQFP

The SY89824L is a High Performance Bus Clock Driver

with 22 differential HSTL (High Speed Transceiver Logic)
output pairs. The part is designed for use in low voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultra low skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low Voltage Positive Emitter Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.

The SY89824L features low pin-to-pin skew (50ps max.)

and low part-to-part skew (200ps max.)--performance
previously unachievable in a standard product having such
a high number of outputs. The SY89824L is available in a
single space saving package, enabling a lower overall cost
solution.

PIN CONFIGURATION

3.3V 1:22 HIGH-PERFORMANCE,
LOW VOLTAGE
BUS CLOCK DRIVER

DESCRIPTION

ClockWorksTM

SY89824L

PIN NAMES

LOGIC SYMBOL

APPLICATIONS

High-performance PCs

Workstations

Parallel processor-based systems

Other high-performance computing

Communications

64-PIN

HQFP

17 18 19 20 21 22 23 24 25 26 27 28 29

61 60 59 58 57 56 55 54 53 52 51 50 49

CCO

HSTL_CLK

CLK_SEL

LVPECL_CLK

GND

CCI

30 31 32

CCO

HSTL_CLK

LVPECL_CLK

CCO

CLK_SEL

HSTL_CLK

LVPECL_CLK

Q0 - Q21

LEN

Rev.: C

Amendment: /1

Issue Date:

March 2000

ClockWorksTM

SY89824L

Micrel

(1)

CLK_SEL

-Q

-/Q

LOW

HIGH

LOW

HIGH

HSTL_CLK

/HSTL_CLK

LVPECL_CLK

/LVPECL_CLK

TRUTH TABLE

NOTE:

1. The OE (output enable) signal is synchronized with the low level of the

HSTL_CLK and LVPECL_CLK signal.

Level

Direction

Signal

HSTL

Input

HSTL_CLK, /HSTL_CLK

HSTL

Output

-Q

, /Q

-/Q

LVPECL

Input

LVPECL_CLK, /LVPECL_CLK

LVCMOS/LVTTL

Input

CLK_SEL, OE

SIGNAL GROUPS

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Value

Unit

CCI/

CCO

Pin Potential to Ground Pin

�0.5 to +4.0

Input Voltage

�0.5 to V

CCI

OUT

DC Output Current (Output HIGH)

�50

Tstore

Storage Temperature

�65 to +150

�

NOTE:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

= 0

�

= +25

�

= +70

�

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Output HIGH Voltage

(1)

1.0

1.2

1.0

1.2

1.0

1.2

Output LOW Voltage

(1)

0.4

Input HIGH Voltage

+0.1

1.6

+0.1

1.6

+0.1

1.6

Input LOW Voltage

�0.3

�0.1

�0.3

�0.1

�0.3

�0.1

Input Crossover Voltage

0.68

0.9

0.68

0.9

0.68

0.9

Input HIGH Current

+20

�350

+20

�350

+20

�350

�

Input LOW Current

�500

�

HSTL

= 0

�

= +25

�

= +70

�

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

CCI

Core

3.0

3.3

3.6

3.0

3.3

3.6

3.0

3.3

3.6

CCO

Output

1.6

1.8

2.0

1.6

1.8

2.0

1.6

1.8

2.0

CCI

Core

115

140

115

140

115

140

Power Supply

NOTE:

1. Outputs loaded with 50

to ground.

ClockWorksTM

SY89824L

Micrel

= 0

�

= +25

�

= +70

�

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

Input HIGH Voltage

2.0

Input LOW Voltage

0.8

Input HIGH Current

+20

�250

+20

�250

+20

�250

�

Input LOW Current

�600

�

NOTES:

1. Outputs loaded with 50

to ground. Airflow

300 LFPM.

2. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential

output signals.

3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same

voltage and temperature.

4. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same

voltage and temperature.

5. The V

(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.

6. V

CMR

is defined as the range within which the V

level may vary, with the device still meeting the propagation delay specification. The numbers in

AC ELECTRICAL CHARACTERISTICS

(1)

= 0

�

= +25

�

= +70

�

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

PHL

Propagation Delay

(2)

1.0

PLH

skew

Within-Device Skew

(3)

skpp

Part-to-Part Skew

(4)

200

Minimum Input Swing

(5)

600

LVPECL_CLK

CMR

Common Mode Range

(6)

�1.5

�0.4

�1.5

�0.4

�1.5

�0.4

LVPECL_CLK

OE Set-Up Time

(7)

1.0

OE Hold Time

0.5

Output Rise/Fall Time

300

800

300

800

300

800

(20% � 80%)

DC ELECTRICAL CHARACTERISTICS

= 0

�

= +25

�

= +70

�

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Input HIGH Voltage

CCI

� 1.165 V

CCI

� 0.880 V

CCI

� 1.165 V

CCI

� 0.880 V

CCI

� 1.165 V

CCI

� 0.880

Input LOW Voltage

CCI

� 1.810 V

CCI

� 1.475 V

CCI

� 1.810 V

CCI

� 1.475 V

CCI

� 1.810 V

CCI

� 1.475

Input HIGH Current

+150

�

Input LOW Current

0.5

�

LVCMOS/LVTTL

LVPECL

PRODUCT ORDERING CODE

Ordering

Package

Operating

Code

Type

Range

SY89824LHC

H64-1

Commercial

the table are referenced to V

CCI

. The V

level must be such that the

peak-to-peak voltage is less than 1.0V and greater than or equal to
V

(min.). The lower end of the CMR range varies 1:1 with V

CCI

. The

CMR

(min) will be fixed at 3.3V � |V

CMR

(min)|.

7. OE set-up time is defined with respect to the rising edge of the clock.

OE HIGH to LOW transition ensures outputs remain disabled during
the next clock cycle. OE LOW to HIGH transition enables normal
operation of the next input clock.

ClockWorksTM

SY89824L

Micrel

64 LEAD EPAD-TQFP (DIE UP) (H64-1)

Rev. 02

+0.05

�0.05
+0.002

�0.002

+0.006

�0.006

+0.012

�0.012

+0.002

�0.002

+0.15

�0.15

+0.03

�0.03

+0.05

�0.05

+0.012

�0.012

+0.05

�0.05

MICREL-SYNERGY

3250 SCOTT BOULEVARD

SANTA CLARA

CA 95054

USA

TEL

+ 1 (408) 980-9191

FAX

+ 1 (408) 914-7878

WEB

http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

� 2000 Micrel Incorporated

Электронный компонент: SY89824L