1
Precision EdgeTM
SY89808L
Micrel
FEATURES
s
9 differential HSTL (1.5V compatible) output pairs
s
500MHz maximum clock frequency
s
Triple-buffered enable function
s
3.3V core supply, 1.8V output supply for reduced
power
s
LVPECL and HSTL inputs
s
HSTL outputs drive 50
to ground with no
offset voltage
s
Low pin-to-pin skew (25ps max.)
s
Guaranteed over industrial 40
C to +85
C
temperature range
s
Available in 32-pin TQFP package
The SY89808L is a High-Performance Bus Clock Driver with
9 differential HSTL (High-Speed Transceiver Logic) 1.5V
compatible output pairs. The part is designed for use in low-
voltage (3.3V/1.8V) applications which require a large number
of outputs to drive precisely aligned, ultra-low skew signals to
their destination. The input is multiplexed from either HSTL or
LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the
CLK_SEL pin.
The Output Enable (OE) is synchronous and triple-buffered
so that the outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any potential of generating
a runt clock pulse when the device is enabled/disabled, as can
occur with an asynchronous control. The triple-buffering feature
provides a three-clock delay from the time the OE input is
asserted/de-asserted to when the clock appears at the outputs.
The SY89808L features an ultra-low pin-to-pin skew of less
than 25ps. The SY89808L is available in a 32-TQFP space
saving package, enabling a lower overall cost solution.
3.3V, 500MHz, 1:9 DIFFERENTIAL
HSTL (1.5V) FANOUT BUFFER/
TRANSLATOR
DESCRIPTION
Precision EdgeTM
SY89808L
LOGIC SYMBOL
APPLICATIONS
s
Workstations
s
Parallel processor-based systems
s
High-performance computing
s
Communications
CLK_SEL
HSTL_CLK
/HSTL_CLK
LVPECL_CLK
/LVPECL_CLK
OE
0
1
9
9
Q0 -- Q8
/Q0 -- /Q8
EN
ENABLE
LOGIC
Rev.: C
Amendment: /0
Issue Date:
Apr. 11, 2003
Precision EdgeTM
TYPICAL PERFORMANCE
200
300
400
500
600
700
800
900
0
200
400
600
800
1000
1200
1400
1600
AMPLITUDE (mV)
FREQUENCY (MHz)
Output Amplitude
vs. Frequency
Precision Edge is a trademark of Micrel, Inc.
TRUTH TABLE
OE
(1)
CLK_SEL
Q
0
Q
8
/Q
0
/Q
8
0
0
LOW
HIGH
0
1
LOW
HIGH
1
0
HSTL_CLK
/HSTL_CLK
1
1
LVPECL_CLK
/LVPECL_CLK
Note 1.
The OE (output enable) signal is synchronized with the low level
of the HSTL_CLK and LVPECL_CLK signal.
2
Precision EdgeTM
SY89808L
Micrel
Pin Number
Pin Name
Type
Pin Function
2, 3
HSTL_CLK,
HSTL
Differential clock input selected by CLK_SEL. Can be left floating if not
/HSTL_CLK
Input
selected. Floating input, if selected produces an indeterminate output. HSTL
input signal requires external termination 50
to GND.
5, 6
LVPECL_CLK,
LVPECL
Differential clock input selected by CLK_SEL. Can be left floating. Floating
/LVPECL_CLK
Input
input, if selected produces a LOW at the output (internal 75
pull-downs).
Requires external termination. 75k
pull-up.
4
CLK_SEL
LVTTL
Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH.
Input
11k
pull-up.
8
OE
LVTTL
Enable input synchronized internally to prevent glitching of the Q0-Q8 and
Input
/Q0-/Q8 outputs. Must be a minimum of three clock periods wide if
synchronous with the CLK inputs and must meet the t
S
and t
H
requirements
(refer to AC Electrical Characteristics). If asynchronous, must be a minimum
of four clock periods wide. 11k
pull-up.
31, 29, 27, 23,
Q0Q8
HSTL
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
21, 19, 15, 13,
Output
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
11
with 50
to GND. Q0Q8 outputs are static LOW when OE = LOW. Unused
output pairs may be left floating.
30, 28, 26, 22,
/Q0/Q8
HSTL
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
20, 18, 14, 12,
Output
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
10
with 50
to GND. /Q0/Q8 outputs are static HIGH when OE = LOW.
Unused output pairs may be left floating.
1
VCCI
VCC Core
Core V
CC
connected to 3.3V supply. Bypass with 0.1
F in parallel with
Power
0.01
F low ESR capacitors as close to V
CCI
pin as possible.
9, 16, 17, 24,
VCCO
VCC Output
Output Buffer V
CC
connected to 1.8V supply. Bypass with 0.1
F in parallel
25, 32
Power
with 0.01
F low ESR capacitors as close to V
CCO
pins as possible. All V
CCO
pins should be connected together on the PCB.
7
GND
Ground
Ground.
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY89808LTI
T32-1
Industrial
SY89808LTI
SY89808LTITR*
T32-1
Industrial
SY89808LTI
*Tape and Reel.
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCCI
HSTL_CLK
/HSTL_CLK
CLK_SEL
LVPECL_CLK
/LVPECL_CLK
GND
OE
VCCO
Q3
/Q3
Q4
/Q4
Q5
/Q5
VCCO
VCCO
Q0
/Q0
Q1
/Q1
Q2
/Q2
VCCO
VCCO
/Q8
Q8
/Q7
Q7
/Q6
Top View
Q6
VCCO
32-Pin TQFP (T32-1)
PIN DESCRIPTION
3
Precision EdgeTM
SY89808L
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
IN
) ..................................... 0.5V to V
CCI
V
CC
Pin Potential to Ground Pin
(V
CCI,
V
CCO
) ............................................ 0.5V to +4.0V
DC Output Current, Output HIGH (I
OUT
) .................. 50mA
Lead Temperature (soldering, 10 sec.) ..................... 220
C
Storage Temperature (T
S
) ....................... 65
C to +150
C
Operating Ratings
(Note 2)
Supply Voltage
(V
CCI
) ............................................... +3.15V to +3.45V
(V
CCO
) ................................................. +1.6V to +2.0V
Ambient Temperature (T
A
) ......................... 40
C to +85
C
Package Thermal Resistance
TQFP
(
JA
)
Still-Air ........................................................... 50
C/W
500lfpm .......................................................... 42
C/W
TQFP
(
JC
) .......................................................... 20
C/W
Power Supply T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CCI
V
CC
Core
3.15
3.3
3.45
V
V
CCO
V
CC
Output
1.6
1.8
2.0
V
I
CCI
I
CC
Core
Max V
CC
, No Load
--
80
110
mA
HSTL V
CCI
= 3.3V
5%; V
CCO
= 1.8V
10%; R
L
= 50
to GND; T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output HIGH Voltage
1.0
--
1.2
V
V
OL
Output LOW Voltage
0.2
--
0.4
V
V
IH
Input HIGH Voltage
V
X
+0.1
--
1.6
V
V
IL
Input LOW Voltage
0.3
--
V
X
0.1
V
V
X
Input Crossover Voltage
0.68
--
0.9
V
I
IH
Input HIGH Current
+20
--
350
A
I
IL
Input LOW Current
--
--
500
A
LVPECL V
CCI
= 3.3V
5%; V
CCO
= 1.8V
10%; T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Max
Units
V
IH
Input HIGH Voltage
V
CCI
1.165 V
CCI
0.880
V
V
IL
Input LOW Voltage
V
CCI
1.810 V
CCI
1.475
V
I
IH
Input HIGH Current
--
+150
A
I
IL
Input LOW Current
0.5
--
A
DC ELECTRICAL CHARACTERISTICS
LVCMOS/LVTTL V
CCI
= 3.3V
5%; V
CCO
= 1.8V
10%; T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
--
--
V
V
IL
Input LOW Voltage
--
--
0.8
V
I
IH
Input HIGH Current
+20
--
250
A
I
IL
Input LOW Current
--
--
600
A
4
Precision EdgeTM
SY89808L
Micrel
AC ELECTRICAL CHARACTERISTICS
V
CCI
= 3.3V
5%; V
CCO
= 1.8V
10%; All outputs are loaded with 50
to GND; T
A
= 40
C to +85
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
V
OUT
450mV
500
--
--
MHz
t
pd
Propagation Delay
CLK-to-Q
Note 3
0.800
1.000
1.200
ns
SEL-to-Q
Note 3
0.800
1.200
1.700
ns
t
SKEW
Within-Device Skew
Note 4
--
--
25
ps
t
SKPP
Part-to-Part Skew
Note 5
--
--
400
ps
V
pp
Minimum Input Swing
Note 6
150
--
--
mV
LVPECL_CLK
V
CMR
Common Mode Range
Note 7
1.5
--
0.4
V
LVPECL_CLK
t
S
OE Set-Up Time
Note 8
1.0
--
--
ns
t
H
OE Hold Time
0.5
--
--
ns
t
r
,
t
f
Output Rise/Fall Time (20% 80%)
250
450
700
ps
t
JITTER
Cycle-to-Cycle Jitter
Note 9
1
ps(rms)
Total Jitter
Note 10
10
ps(pk-pk)
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation
is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM
RATlNG conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3.
Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
Note 4.
The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the
same voltage and temperature.
Note 5.
The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
Note 6.
The V
PP
(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
Note 7.
V
CMR
is defined as the range within which the V
IH
level may vary, with the device still meeting the propagation delay specification. The
numbers in the table are referenced to V
CCI
. The V
IL
level must be such that the peak-to-peak voltage is less than 1.0V and greater than or
equal to V
PP
(min.). The lower end of the CMR range varies 1:1 with V
CCI
. The V
CMR
(min) will be fixed at 3.3V |V
CMR
(min)|.
Note 8.
OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the
next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
Note 9.
Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n
T
n1
where T is the time between rising edges of the
output signal.
Note 10. Total jitter definition: with an ideal clock source of
f
max
, no more than one output edge in 10
12
output edges will deviate by more than the
specified amount.
5
Precision EdgeTM
SY89808L
Micrel
TIMING DIAGRAMS
t
S
t
H
CLK
OE
Q0 - Q8
Assert Latency
De-assert Latency
HSTL_CLK, LVPECL_CLK
/HSTL_CLK, /LVPECL_CLK
Q0 - Q8
/Q0 - /Q8
t
PD
t
PD
CLK_SEL
Q0 - Q8
/Q0 - /Q8
t
PD
Note 1.
The OE input signal must be a minimum of 3 clock periods with width.
Note 2.
The internal enable is asserted and de-asserted on the falling edge of clock.
Note 3.
The internal enable occurs 2.5 clock cycles (plus the set-up time of OE with the rising edge of clock) after the rising edge of the external OE.
Note 4.
If OE does not meet the t
S
of t
H
specifications as in asynchronous applications, OE must be a minimum of 4 clock periods in width.
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