SY89538L

3.3V Precision LVPECL and LVDS

Programmable Multiple Output Bank Clock

Synthesizer and Fanout Buffer with Zero Delay

Precision Edge is a registered trademark of Micrel, Inc.
MLF and

Micro

LeadFrame are trademarks of Amkor Technology, Inc.

Micrel Inc. · 2180 Fortune Drive · San Jose, CA 95131 · USA · tel +1 (408) 944-0800 · fax + 1 (408) 474-1000 · http://www.micrel.com

October 2005

M9999-101105-B

hbwhelp@micrel.com

or (408) 955-1690

General Description

The SY89538L integrated programmable clock
synthesizer and fanout is part of a precision PLL-
based clock generation family optimized for
enterprise switch, router, and multiprocessor server
applications. This family is ideal for generating
internal system timing requirements up to 750MHz for
multiple ASICs, FPGAs, and NPUs. These devices
integrate the following blocks into a single monolithic
IC:

· PLL (Phase-Lock-Loop) based synthesizer
· Zero-delay MUX and feedback capability
· 1:4 LVPECL fanout
· 1:3 LVDS fanout
· Clock generator (dividers)
· Logic translation (LVPECL, LVDS)
· Five-independently programmable output

banks

This level of integration minimizes additive jitter and
part-to-part skew associated with discrete
alternatives, resulting in superior system-level timing
with reduced board space and power. For
applications that do not require a zero-delay function,
see the SY89537L.
All support documentation can be found on
Micrel's web site at:

www.micrel.com.

Applications

· Enterprise routers, switches, servers and

workstations

· Parallel processor-based systems
· Internal system clock generation for ASICs, NPUs

and FPGAs

Markets

· LAN/WAN
· Enterprise servers
· Test and measurement

Precision Edge

Features

· Integrated programmable

synthesizer with multiple

output dividers, fanout buffers, and clock drivers

· Zero-delay capability: 29.375MHz to 756MHz
· Reference clock input: 9.325MHz to 756MHz
· Input MUX accepts a reference and a crystal

(XTAL) source

Ideal for reference backup clock source or

system test frequency source

Patent-pending unique input MUX isolates XTAL

and reference inputs which minimizes crosstalk

· Guaranteed

performance:

Output frequency range: 29.375MHz to 756MHz

<150ps

total jitter

<6ps

RMS

cycle-to-cycle jitter (XTAL Input)

<8ps

deterministic jitter

<0.7ps

RMS

crosstalk induced jitter

<75ps output-to-output skew
· TTL/CMOS-compatible control logic
· Five-independently programmable output

frequency banks:

Four differential LVPECL output banks
One differential LVDS output bank with three

output pairs

· Output bank synchronization control pin
· Output enable
· 3.3V ±10% power supply (2.5V output capable)
· Guaranteed over the industrial temperature range

(-40°C to +85°C)

· Available in a 64-pin EPAD-TQFP

Micrel, Inc.

SY89538L

October 2005

M9999-101105-B

hbwhelp@micrel.com

or (408) 955-1690

Pin Description

Power

Pin Number

Pin Name

Pin Function

1 VCCA

Analog PLL Power Pin. Connects to "quiet" 3.3V supply. 3.3V power pins must be
connected together on the PCB. Bypass with 0.1µF//0.01µF low ESR capacitors and
place them as close to the VCCA pin as possible.

6, 56

VCCD

Digital Logic Core Power Pin. VCCD connects to a 3.3V supply. All power pins must
be connected together on the PCB. Bypass with 0.1µF//0.01µF low ESR capacitors
and place them as close to the VCCD pin as possible.

19, 40, 43, 51

VCCO

LVDS and LVPECL Output Driver Power Pins. These outputs can be powered from a
2.5V or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or
2.5V ±5%. All power pins must be connected together on the PCB. Bypass with
0.1µF//0.01µF low ESR capacitor and place them as close to the VCCO pin as
possible.

15 GNDA

Analog PLL Ground. Connect to "quiet" ground. GNDA and GND must be connected
together on the PCB.

16, 30, 31,

47, 55

GND,

Exposed Pad

Ground: GND pins and exposed pad must both be connected to the same ground
plane.

Control and Configuration

Pin Number

Pin Name

Pin Function

62 LR

Analog Input/Output. Provides the reference voltage for the PLL loop filter and is
used with the LF pin. See "External Loop Filter Considerations" for recommended
loop filter values.

63 LF

Analog Input/Output. Provides the loop filter node for the PLL. See "External Loop
Filter Considerations" for recommended loop filter values.

2, 7

RSEL1, RSEL0

TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inputs.
The two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8.
RSEL0 is the LSB bit. See "Reference Input Divider and Zero Delay MUX Divider
Select Table" for proper decoding. The threshold voltage V

= V

/2. Internal 25k

pull-up. The default logic is HIGH.

10 INSEL

TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input.
Internal 25k pull-up. The default is logic HIGH, and selects the XTAL input. The
threshold voltage V

= V

/2.

Logic HIGH: XTAL Select
Logic LOW: Reference Input Select

36 LSEL

TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL,
DSEL, and LEN are used together to decode the selection and post divider of the
LVDS outputs. Internal 25k pull-up. See "LVDS Output Post-Divider and Frequency
Select Table" for proper decoding. The threshold voltage V

= V

/2. The default

logic is HIGH.

37 LEN

TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as
a frequency select pin. LEN, DSEL, and LSEL are used together to decode the
selection and post divide of the LVDS output bank, see the "LVDS Output Post-
Divider and Frequency Select Table" for proper decoding. Internal 25k pull-up.
When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are
HIGH. The threshold voltage V

= V

/2. The default logic is HIGH.

23
25
57
59

PSEL0
PSEL1
PSEL2
PSEL3

TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx,
DSEL and PENx are used together to decode the selection and post divider of the
PECL outputs. PSELx pins include an internal 25k pull-up. The threshold voltage
V

= V

/2. See "LVPECL Output Post-Divider and Frequency Select Table" for

proper decoding.

Micrel, Inc.

SY89538L

October 2005

M9999-101105-B

hbwhelp@micrel.com

or (408) 955-1690

Pin Description

Control and Configuration

(continued)

Pin Number

Pin Name

Pin Function

24
26
58
60

PEN0
PEN1
PEN2
PEN3

TTL/CMOS input enable pin. Used to control the PECL POUT0-POUT3 outputs and
as a frequency select pins. PENx, PSELx, and DSEL are used together; see the
"LVPECL Output Post-Divider and Frequency Select Table" for proper decoding.
PENx contains internal 25k pull-up. When disabled, PECL0-PECL3 outputs are a
logic LOW. The threshold voltage V

= V

/2.

46 SYNC

TTL/CMOS Output Bank Synchronization Control. Internal 25k pull-down. The
default state is HIGH. After any bank has been programmed, all PECL and LVDS
outputs are synchronized when the SYNC control pin is toggled with a HIGH-LOW-
HIGH transition. See "Synchronization" section for details. The threshold voltage V

= V

/2.

5 FBSEL

TTL/CMOS Input Select Control. Selects either internal or external feedback (zero-delay
function). Internal 25k pull-up. The threshold voltage V

= V

/2. Default is logic

HIGH, and selects internal feedback.
Logic HIGH: Internal feedback (from the Programmable Divider)
Logic Low: External feedback (from the FBIN inputs)

28
33
35

PD_4
PD_2
PD_0

TTL/CMOS Programmable Divider-Select Control. Internal 25k pull-down. Default is
logic LOW. The threshold voltage V

= V

/2. See "Programmable-Divider Select Table"

for proper decoding.

27
29
34

PD_5
PD_3
PD_1

TTL/CMOS Programmable Divider-Select Control. Internal 25k pull-up. Default is logic
HIGH. The threshold voltage V

= V

/2. See "Programmable-Divider Select Table" for

proper decoding.

13, 14

PDSEL1,

PDSEL0

TTL/CMOS Pre-Divider Select Input. Internal 25k pull-up. This two-bit input divider
scales the VCO/2 frequency. See "Pre-Divider Frequency Select Table" for proper
decoding. The threshold voltage V

= V

/2.

22 DSEL

TTL/CMOS Post-Divider Option Control. Internal 25k pull-up. Default is logic HIGH.
The threshold voltage V

= V

/2.

Logic HIGH: All LVPECL and LVDS outputs operate with their respective output
frequency control (PSELx, PENx, LSEL, LEN).
Logic LOW: Internal PLL is disabled, reference and XTAL signals by-passes the PLL
through a /1, /4, and /16 Post-Divider.
See "LVPECL and LVDS Output Post-Divider and Frequency Select Table" for proper
decoding.

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