1
Precision EdgeTM
SY89534/35L
Micrel
Input
Output
Device
Crystal
Reference
BankA
BankB
BankC
SY89532L*
X
LVPECL LVPECL LVPECL
SY89533L*
X
LVPECL
LVDS
LVPECL
SY89534L
X
LVPECL LVPECL LVPECL
SY89535L
X
LVPECL
LVDS
LVPECL
FEATURES
s
Integrated synthesizer plus fanout buffers, clock
dividers, and translator in a single 64-pin package
s
Accepts any reference input between 14MHz to
160MHz (single-ended or differential)
s
33MHz to 500MHz output frequency range
s
LVPECL outputs (SY89534L)
LVPECL and LVDS outputs (SY89535L)
s
3.3V
10% power supply
s
Low jitter: <50ps cycle-to-cycle
s
Low pin-to-pin skew: <50ps
s
TTL/CMOS compatible control logic
s
3 independently programmable output frequency
banks:
9 differential output pairs @BankB (LVPECL/LVDS)
2 differential output pairs @BankA (LVPECL)
2 differential output pairs @BankC (LVPECL)
s
Available in 64-pin EPAD-TQFP
The SY89534L and SY89535L programmable clock
synthesizers are a 3.3V, high-frequency, precision PLL-based
family optimized for multi-frequency, large clock-tree
applications that require the highest precision. These devices
integrate the following blocks into a single monolithic IC:
PLL (Phase-Lock-Loop)-based synthesizer
Fanout buffer
Clock generator (divider)
Logic translation (LVPECL, LVDS)
The SY89534L and SY89535L includes a flexible input
design that accepts any reference input; single-ended LVTTL/
CMOS, SSTL and differential LVPECL, LVDS, HSTL and
CML.
This level of integration minimizes the additive jitter and
part-to-part skew associated with the discrete alternative,
resulting in superior system-level timing as well as reduced
board space and power. For applications that must interface
to a crystal oscillator, see the SY89532/33.
Data sheets and support documentation can be found on
Micrel's web site at www.micrel.com.
DESCRIPTION
APPLICATIONS
s
Servers
s
Workstations
s
Parallel processor-based systems
s
Other high-performance computing
s
Communications
Rev.: B
Amendment: /0
Issue Date:
July 2003
PRODUCT SELECTION GUIDE
*Refer to SY89532/33L data sheet for details.
Precision EdgeTM
Precision Edge is a trademark of Micrel, Inc.
3.3V, PRECISION, 33MHz to 500MHz
PROGRAMMABLE LVPECL AND
LVDS BUS CLOCK SYNTHESIZER
Precision EdgeTM
SY89534L
SY89535L
2
Precision EdgeTM
SY89534/35L
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY89534LHC
H64-1
Commercial
SY89534LHC
SY89535LHC
H64-1
Commercial
SY89535LHC
VCC_LOGIC
QB0
VCCOB
/QA1
QA1
/QA0
QA0
VCCOA
FSEL_A2
FSEL_A1
FSEL_A0
OUT_SYNC
VCC_LOGIC
VCCA
GND
NC*
NC*
NC*
NC*
VCO_SEL
PSEL1
PSEL0
LOOP_REF
LOOP_FILTER
GND
REFCLK
/REFCLK
VBB_REF
M(3)
M(2)
M(1)
M(0)
/QB0
QB1
/QB1
QB2
/QB2
QB3
/QB3
QB4
/QB4
QB5
/QB5
QB6
/QB6
QB7
/QB7
QB8
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-pin
EPAD-TQFP
QC0
/QB8
VCCOB
VCCOB
GND
FSEL_B0
FSEL_B1
FSEL_B2
GND
FSEL_C0
FSEL_C1
FSEL_C2
VCCOC
/QC0
QC1
/QC1
64-Pin EPAD-TQFP (H64-1)
*NC: Do not connect, leave floating.
FUNCTIONAL BLOCK DIAGRAM
Pre
Divider
1, 2, 4, 8
4
5
6
7
8
V
CC
--1.3V
Reference
Charge
Pump
Phase
Detector
12
13
14
62
61
64
63
2
3
1
60
58
57
56
54
53
52
51
3-Bit
Divider A
2, 4, 6, 8,
10, 12,18
PSEL0
VCO_SEL
PESL1
LOOPREF
LOOPFILTER
VBB_REF
(MSB) M3
3
2x
9x
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
29
28
27
26
25
24
23
22
21
20
19
18
3
VCO
(600MHz to
1000MHz)
14MHz to
20MHz
14MHz to 20MHz
/QA1
V
CCO
B
QB0
/QB0
QB1
/QB1
QB2
/QB2
QB3
/QB3
QB4
/QB4
QB5
/QB5
QB6
/QB6
QB7
/QB7
QB8
/QB8
59
31
30
V
CCO
B
V
CCO
B
QA1
/QA0
QA0
55
V
CCO
A
A
EN
B
EN
3-Bit
Divider B
2, 4, 6, 8,
10, 12,18
3-Bit
Divider C
2, 4, 6, 8,
10, 12,18
C
EN
FSEL_A2
FSEL_A1
FSEL_A0 (LSB)
OUT_SYNC
M-Divide
30, 32, 34, 36, 38,
40, 42, 44, 48, 50,
52, 54, 56, 60, 62, 66
V
CC
_LOGIC
V
CC
_LOGIC
V
CC
A
GND
NC
NC
NC
NC
9
GND
10
REFCLK
11
/REFCLK
Mux 1
Clock
GND
FSEL_B0 (LSB)
FSEL_B1
FSEL_B2
GND
FSEL_C0 (LSB)
FSEL_C1
FSEL_C2
17
V
CCO
C
QC0
/QC0
QC1
/QC1
3
Buf
5
4
0 = Use Internal PLL
1 = Bypass Internal PLL (default)
600MHz to
1000MHz
2x
M2
15
16
M1
(LSB) M0
3
Precision EdgeTM
SY89534/35L
Micrel
PIN DESCRIPTION
Pin Number
Pin Name
Functional Description
4
VCO_SEL
LVTTL/CMOS Compatible Input: Selects between internal or external VCO. When
tied LOW (GND) internal VCO is selected. For external VCO, leave floating (default
condition is logic HIGH). Internal 25k
pull-up.
5, 6
PSEL(1:0)
LVTTL/CMOS Compatible Input: Controls input frequency pre divider. Internal 25k
pull-up. Default is logic HIGH. See
"Pre-Divide Frequency Select"
table.
7
LOOP REF
Analog Input/Output: Provides the reference voltage for PLL loop filter.
8
LOOP FILTER
Analog Input/Output: Provides the loop filter for PLL. See
"External Loop Filter
Considerations"
for loop filter values.
13,14,15,16
M (3:0)
LVTTL/CMOS Compatible Input: Used to change the PLL (Phase-Lock Loop)
feedback divider. Internal 25k
pull-up. (M0 = LSB). Default is logic HIGH.
See
"Feedback Divide Select"
table.
22, 23, 24
FSEL_C (2:0)
LVTTL/CMOS Compatible Input: Bank C post divide select. Internal 25k
pull-up.
Default is logic HIGH. See
"Post-Divide Frequency Select"
table.
26, 27, 28
FSEL_B (2:0)
LVTTL/CMOS Compatible Input: Bank B post divide select. Internal 25k
pull-up.
Default is logic HIGH. See
"Post-Divide Frequency Select"
table.
56, 57, 58
FSEL_A (2:0)
LVTTL/CMOS Compatible Input: Bank A post divide select. Internal 25k
pull-up.
Default is logic HIGH. See
"Post-Divide Frequency Select."
FSEL_A0 = LSB.
59
OUT_SYNC
Banks A,B,C output synchronous control: (LVTTL/CMOS compatible).
Internal 25k
pull-up. After any bank has been programmed, toggle with a
HIGH-LOW-HIGH pulse to resynchronize all output banks.
Configuration
Pin Number
Pin Name
Functional Description
60, 61
V
CC_Logic
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
62
V
CCA
Power for PLL: Connect to "quiet" 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
55
V
CCO
A
Power for Output Drivers: Connect all V
CCO
pins to 3.3V supply. V
CCO
pins are not
30, 31, 50
V
CCO
B
connected internally on the die.
21
V
CCO
C
4, 9, 25, 63, 29
GND
Ground. All GND pins must be tied together on the PCB. Exposed pad must be
(exposed pad)
soldered to a ground plane.
Power
Pin Number
Pin Name
Functional Description
1, 2, 3
NC
No Connect: Leave floating.
10, 11
REFCLK, /REFCLK
Reference Input: This flexible input accepts any input TTL/CMOS, LVPECL, LVDS,
HSTL, SSTL. See
"Input Interface"
section.
12
VBB_REF
Reference Output Voltage. Used for single-ended input. Maximum sink/source
current = 0.5mA.
51, 52, 53, 54
QA1 to QA0
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A
(0:2). Terminate outputs with 50
to V
CC
2V. See
"Output Termination
Recommendations"
section for termination detail.
3249
QB8 to QB0
Bank B Output Drivers: SY89534: 100k LVPECL output drivers.
SY89535: Differential LVDS outputs. See
"Output Termination Recommendations"
section for termination detail. Output frequency is controlled by FSEL_B (0:2).
17, 18, 19, 20
QC1 to QC0
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by
FSEL_C (0:2). Terminate outputs with 50
to V
CC
2V. See
"Output Termination
Recommendations"
section.
64
NC
No Connect: Leave floating.
Input/Output
4
Precision EdgeTM
SY89534/35L
Micrel
Symbol
Rating
Value
Unit
All V
CC
V
CC
Pin Potential to Ground Pin
0.5 to +4.0
V
V
IN
Input Voltage
0.5 to V
CCI
V
I
OUT
DC Output Current
LVPECL outputs
50
mA
LVDS outputs
10
mA
T
store
Storage Temperature
65 to +150
C
JA
Package Thermal Resistance (Junction-to-Ambient)
With Die attach soldered to GND:
Still-Air (TQFP)
23
C/W
200lfpm (TQFP)
18
C/W
500lfpm (TQFP)
15
C/W
With Die attach NOT soldered to GND:
(2)
Still-Air (TQFP)
44
C/W
200lfpm (TQFP)
36
C/W
500lfpm (TQFP)
30
C/W
JC
Package Thermal Resistance
4.4
C/W
(Junction-to-Case)
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
2. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation.
3. V
CCA
, V
CC_LOGIC
, V
CCO
A/C. V
CCO
B are
not
internally connected together inside the device. They must be connected together on the PCB.
4. No load. Outputs floating, Banks A, B, and C enabled.
ABSOLUTE MAXIMUM RATINGS
(1)
DC ELECTRICAL CHARACTERISTICS
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
V
CCA
(3)
PLL and Logic Supply Voltage
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
3.6
V
V
CC_LOGIC
V
CCO
A/C
Bank A and C V
CC
Output
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
3.6
V
V
CCO
B
Bank B V
CC
Output
LVPECL/LVDS
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
3.6
V
I
CC
Total Supply Current
(4)
SY89534L PECL
--
--
260
--
--
260
--
--
260
mA
SY89535L LVDS
--
275
330
--
285
330
--
300
330
mA
Power Supply
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage
2.0
--
--
2.0
--
--
2.0
--
--
V
V
IL
Input LOW Voltage
--
--
0.8
--
--
0.8
--
--
0.8
V
I
IH
Input HIGH Current
--
--
--
--
--
150
--
--
--
A
I
IL
Input LOW Current
--
--
--
300
--
--
--
--
--
A
LVCMOS/LVTTL Input Control Logic (All V
CC
pins = +3.3V
10%)
5
Precision EdgeTM
SY89534/35L
Micrel
DC ELECTRICAL CHARACTERISTICS
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
V
OD
Output Voltage Swing
(9, 10)
250
--
450
250
--
450
250
--
450
mV
V
OH
Output HIGH Voltage
--
--
1.475
--
--
1.475
--
--
1.475
V
V
OL
Output LOW Voltage
0.925
--
--
0.925
--
--
0.925
--
--
V
V
OCM
Output Common Mode Voltage
(9)
1.125
--
1.375
1.125
--
1.375
1.125
--
1.375
V
V
OCM
Change in Common Mode
50
--
50
50
--
50
50
--
50
mV
Voltage
(9)
LVDS Outputs (SY89535L) Bank B QB0:8
(9)
(All V
CC
pins = +3.3V
10%)
NOTES:
5. V
IN
< 2.4V
6. V
IN
< V
CC
+0.3V
7. 50
to V
CC
2V. Banks A, B, and C enabled.
8. V
CC
= 3.0V to 3.6V.
9. 100
termination across differential pair.
10.
V
OD
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
V
OH
Output HIGH Voltage
(7)
V
CC
1.075
--
V
CC
0.830 V
CC
1.075
--
V
CC
0.830 V
CC
1.075
--
V
CC
0.830
V
V
OL
Output LOW Voltage
(7)
V
CC
1.860
--
V
CC
1.570 V
CC
1.860
--
V
CC
1.570 V
CC
1.860
--
V
CC
1.570
V
V
ID
Differential Input Voltage
(8)
100
(3)
--
--
100
(3)
--
--
100
(3)
--
--
mV
200
(4)
--
--
200
(4)
--
--
200
(4)
--
--
mV
V
IH
Input HIGH Voltage
(8)
--
--
V
CC
+0.3
--
--
V
CC
+0.3
--
--
V
CC
+0.3
V
V
IL
Input LOW Voltage
(8)
0.3
--
--
0.3
--
--
0.3
--
--
V
I
IH
Input HIGH Current
600
--
300
600
--
300
600
--
300
A
I
IL
Input LOW Current
1200
--
700
1200
--
700
1200
--
700
A
V
BB
Output Reference Voltage
V
CC
1.26 V
CC
1.32 V
CC
1.38
V
CC
1.26 V
CC
1.32 V
CC
1.38
V
CC
1.26 V
CC
1.32 V
CC
1.38
V
100K LVPECL Outputs (All V
CC
pins = +3.3V
10%)
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
V
ID
Differential Input Voltage
100
(5)
--
--
100
(5)
--
--
100
(5)
--
--
mV
200
(6)
--
--
200
(6)
--
--
200
(6)
--
--
mV
V
IH
Input HIGH Voltage
--
--
V
CC
+0.3
--
--
V
CC
+0.3
--
--
V
CC
+0.3
V
V
IL
Input LOW Voltage
0.3
--
--
0.3
--
--
0.3
--
--
V
REFCLK (pins 10, 11) INPUT (All V
CC
pins = +3.3V
10%)
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