Single chip source for 622.08MHz and 155.52MHz
clocks

622.08MHz output is differential PECL, 155.52MHz
output is single-ended PECL

TTL/CMOS compatible inputs and reference output

SONET compliant jitter performance (

0.01UI)

Choice of three reference frequencies

Only 395mW (typ)

Complies with Bellcore, CCITT and ANSI standards

Single +5 volt power supply

Fully compatible with industry standard 10KH I/O
levels

Available in 28-pin PLCC package

Rev.: F

Amendment: /0

Issue Date:

July, 1999

TYPICAL APPLICATION

ClockWorksTM

SY89426

FEATURES

DESCRIPTION

Micrel-Synergy's SY89426 Multi-Output Phase Locked

Loop (PLL) is a SONET compliant clock generator providing
622.08MHz, 155.52MHz and retimed reference clock
outputs. The PLL produces low jitter OC-12/STS-12 and
OC-3/STS-3 rate clocks from an input reference clock of
38.88, 51.84, or 77.76MHz. Additionally, the input reference
clock is retimed and provided as a TTL/CMOS compatible
output, which may be disabled to minimize switching noise.
The SY89426 operates from a single +5 volt supply, and
requires only a simple series RC loop filter.

Coupling Micrel-Synergy's advanced PLL technology

with our proprietary ASSETTM bipolar process has produced
a clock generator IC which exceeds applicable Bellcore
and ANSI specifications, while setting a new standard for
performance and flexibility.

PIN CONFIGURATION

SONET OC-12/OC-3
CLOCK SYNTHESIZER

25 24

21 20

GND

FLTRP

RST

RETRFCK

DISC

FLTRN

PLCC

TOP VIEW

J28-1

CK622P

CK622N

CCO

CK155

GND

SEL39

RFCK

SEL78

0.1uF

FLTRN

RFCK
(TTL)

SEL39
(TTL)

SEL78
(TTL)

CK622P

(PECL)

1000

RETRFCK

(TTL)

155.52MHz
CLOCK OUT

SY89426

VCC

VCCO

CLOCK

FLTRP

GND

RST

(TTL)

DISC
(TTL)

RETIMED
REFOUT

CK155

(PECL)

CK622N

622.08MHz
CLOCK OUT

+3V

2X 50

+3V

+5V

ClockWorksTM

SY89426

Micrel

FUNCTIONAL BLOCK DIAGRAM

INPUTS

RFCK [Reference Clock] TTL

Reference clock IN. (38.88, 51.84 or 77.76MHz).

SEL39 [38.88MHz Select] TTL

Logic HIGH on this pin denotes a 38.88MHz input reference
clock. Tie to logic LOW if input is not 38.88MHz.

SEL78 [77.76MHz Select] TTL

Logic HIGH on this pin denotes a 77.76MHz input reference
clock. Tie to logic LOW if input is not 77.76MHz.

RST [Reset] TTL

Tie to logic LOW for normal operation; logic HIGH forces reset
of internal Phase Detector & feedback dividers.

FLTRP, FLTRN [Loop Filter, Pos & Neg] Analog

Connect a series RC loop filter between these pins. The
suggested RC values are 500

and 0.1

�

F, as shown in the

Typical Application.

DISC [Disable Clock] TTL

Logic HIGH on this pin disables the Retimed Reference Clock
output RETRFCK); if this output is not required, it is
recommended that it be disabled to reduce switching noise. A
logic LOW enables the output.

PIN DESCRIPTION

OUTPUTS

CK622P, CK622N [622 Clock Output] Differential PECL.
622.08MHz output clock from PLL B.

CK155 [155 Clock Out] Single-ended PECL

155.52MHz output clock.

RETRFCK [Retimed Reference Clock Out] TTL

An output clock with the same frequency as the input Reference
Clock (RFCK) and a 45-55% duty cycle. This output is derived
by dividing the 622.08MHz output by the appropriate factor
(e.g., divide by 16 for a 38.88MHz inout reference; divide by
12 for 51.84Mhz in; or divide by 8 for 77.76MHz in).

POWER & GROUND

+5V for internal circuits.

CCO

+5V for PECL outputs.

GND

Ground (0 volts).

FLTRP/N

CCO

RFCK

(TTL)

SEL39

(TTL)

SEL78

(TTL)

RST
(TTL)

CK622P
(PECL)

CK622N

CK155
(PECL)

RETRFCK
(TTL)

DISC
(TTL)

CHG

PUMP

622MHz

VCO

FEEDBACK

� 2/3/4

DIVIDER

� 4

CCA

GND

ClockWorksTM

SY89426

Micrel

SEL39

SEL78

fRFCK

51.84

77.76

38.88

77.76

REFERENCE FREQUENCY SELECTION

(1)

NOTE:

1. Airflow greater than 500lfpm is maintained.

= V

CCO

= +5V

�

5%; GND = 0V; T

= �40

�

C to 85

�

Symbol

Parameter

Min.

Max.

Unit

Condition

Output HIGH Voltage

2.4

= �2mA

Output LOW Voltage

0.5

= 4mA

Output Short Circuit Current

�150

�60

OUT

= 0

Input HIGH Voltage

2.0

Input LOW Voltage

0.8

TTL DC ELECTRICAL CHARACTERISTICS

(1)

NOTE:

1. Airflow greater than 500lfpm is maintained.

Symbol

Parameter

Rating

Unit

Power Supply

0 to +7

Input Voltage

0 to V

OUT

Output Current

�Continuous

�Surge

100

Operating Temperature Range

�40 to +85

�

store

Storage Temperature Range

�65 to +150

�

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.

2. Airflow greater than 500lfpm is maintained.

ABSOLUTE MAXIMUM RATINGS

(1), (2)

PECL DC ELECTRICAL CHARACTERISTIC

(1), (2)

= �40

�

= 0

�

= +25

�

= +85

�

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Output HIGH Voltage

-1130

-840

-1070

-790

-1030

-760

-960

-670

Output LOW Voltage

-2000

-1600

-2000

-1580

-2000

-1580

-2000

-1545

Input HIGH Voltage

(1)

-1230

-890

-1170

-840

-1130

-810

-1060

-720

Input LOW Voltage

(1)

-1950

-1500

-1950

-1480

-1950

-1480

-1950

-1445

Input LOW Current

0.5

0.3

�

= V

CCO

= +5V

�

5%; GND = 0V; T

= �40

�

C to 85

�

NOTES:

1. Forcing one input at a time. Apply V

(Max) or V

(Min) to all other inputs.

2. Airflow greater than 500lfpm is maintained.

ClockWorksTM

SY89426

Micrel

DC ELECTRICAL CHARACTERISTICS -- TTL

TIMING WAVEFORM

RFCK

Input

CK622

Output

tp REF

tp 622

tp 155

(1)

RETRFCK

Output

CK155

Output

NOTE:
1.

Does not apply to 52MHz reference

Parameter

Min.

Typ.

Max.

Units

Condition

VCO Center Frequency

622.08

�

MHz

Nominal

�

ppm

77.76MHz

�

ppm

51.84MHz

�

ppm

38.88MHz

Reference Clock (RFCK) Input Duty Cycle

% of UI

Reference Clock (RETRFCK) Output Duty Cycle

% of UI

15pF load

Acquisition Lock Time

�

sec

TTL Output Rise/Fall Time

10% to 90% of amplitude, 15pF load

PECL Output Rise/Fall Time

500

10% to 90%, 50

load, 5pF cap

CK622 Output Duty Cycle

% of UI

CK155 Output Duty Cycle

% of UI

tRST � RST pulse width

�

sec

tp622 Static Phase Offset of CK622

190

400

600

tp155 Static Phase Offset of CK155

�250

�400

�750

tpREF Static Phase Offset of RETRFCK

+3.5

AC ELECTRICAL CHARACTERISTICS

(1)

= V

CCO

= +5V

�

5%; GND = 0V; T

= �40

�

C to 85

�

Reference Clock (RFCK)
Frequency Tolerance

NOTE:

1. Airflow greater than 500lfpm is maintained.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

Internal Operating Current

120

OUT

Termination Output Current

to Vcc -2, 50% duty cycle

DC ELECTRICAL CHARACTERISTICS -- TTL

= V

CCO

= +5V

�

5%; GND = 0V; T

= �40

�

C to 85

�

DC ELECTRICAL CHARACTERISTICS

(1)

NOTE:

1. Airflow greater than 500lfpm is maintained.

ClockWorksTM

SY89426

Micrel

JITTER GENERATION

Jitter Generation Definition

Bellcore TR-NWT-000499 (Issue 4), section 7.3.3 "Jitter
generation is the process whereby jitter appears at the output
port of an individual unit of digital equipment in the absence of
applied input jitter."

Jitter Generation Requirement

Bellcore TA-NWT-000253 (Issue 2), section 5.6.5.2 "For

Category II interfaces, jitter generation shall not exceed 0.01
UI rms. For OC-N and STSX-N interfaces, a high-pass
measurement filter with a 12kHz cutoff frequency shall be
used." The low-pass cutoff frequency of the measurement
filter shall be higher than 5MHz.

The characteristic of the measurement filter is shown

below.

SONET OC-12 Category II Jitter Generation Measurement Filter Characteristics

Figure 1

Ordering

Package

Operating

Code

Type

Range

SY89426JC

J28-1

Commercial

SY89426JCTR

J28-1

Commercial

SY89426JI

J28-1

Industrial

SY89426JITR

J28-1

Industrial

PRODUCT ORDERING CODE

+20dB/decade

UI (rms)

0.01

12kHz

Frequency

5MHz

(minimum)

Электронный компонент: SY89426JCTR