1
SY88793V
Micrel
3.3V/5V 622Mbps PECL LOW-POWER
LIMITING POST AMPLIFIER w/TTL
SIGNAL DETECT
SY88793V
Rev.: A
Amendment: /0
Issue Date:
March 2003
TYPICAL APPLICATIONS CIRCUIT
APPLICATIONS
s
622Mbps SONET/SDH
s
Small form factor transceivers
s
High-gain line driver and line receiver
s
Single 3.3V or 5V power supply
s
Up to 622Mbps operation
s
Low noise PECL data outputs
s
Chatter-free TTL Signal Detect (SD) output
s
TTL EN input
s
Programmable SD level set (SD
LVL
)
s
Available in a tiny 10-pin MSOP (3mm) package
FEATURES
DESCRIPTION
The SY88793V low-power limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88793V
quantizes these signals and outputs PECL level waveforms.
The SY88793V operates from a single +3.3V or +5V
power supply, over temperatures ranging from 40
C to
+85
C. With its wide bandwidth and high gain, signals with
data rates up to 622Mbps and as small as 5mVp-p can be
amplified to drive devices with PECL inputs.
The SY88793V generates a TTL SD output. A
programmable signal-detect level set pin (SD
LVL
) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SD
LVL
and deasserts low otherwise. EN deasserts the true output
signal without removing the input signal. Typically 6dB SD
hysteresis is provided to prevent chattering.
V
CC
EN
GND
GND
To
CDR
SY88793V
100k
0.1
F
From
Transimpedance
Amp.
D
OUT
/D
OUT
V
REF
V
CC
SD
LVL
D
IN
/D
IN
0.1
F
0.1
F
0.1
F
0.1
F
SD
50
50
R
pd
R
pd
For 3.3V, R
pd
= 120
For 5V, R
pd
= 220
2
SY88793V
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY88793VKC
K10-1
Commercial
793V
SY88793VKCTR*
K10-1
Commercial
793V
SY88793VKI
K10-1
Industrial
793V
SY88793VKITR*
K10-1
Industrial
793V
*Tape and Reel
PIN DESCRIPTION
Pin Number
Pin Name
Type
Pin Function
1
EN
TTL Input:
Enable: Deasserts true data output when high.
Default is high.
2
DIN
Data Input
True data input.
3
/DIN
Data Input
Complementary data input.
4
VREF
Reference voltage.
5
SDLVL
Input
Signal-Detect Level Set: A resistor from this pin to V
CC
sets the
threshold for the data input amplitude at which SD will be asserted.
6
GND
Ground
Device ground.
7
SD
Open-collector
Signal-Detect: Asserts high when the data input amplitude rises above
TTL output w/
the threshold set by SD
LVL
.
internal 6.75k
pullup resistor
8
/DOUT
PECL Output
Complementary data output.
9
DOUT
PECL Output
True data output.
10
VCC
Power Supply
Positive power supply.
SDLVL
GND
6
5
1
EN
DIN
/DIN
VREF
10 VCC
DOUT
/DOUT
SD
9
8
7
2
3
4
10-Pin MSOP
(K10-1)
3
SY88793V
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) ....................................... 0V to +7.0V
Input Voltage (D
IN
,
/D
IN
) ......................................... 0 to V
CC
Output Current (I
OUT
)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
EN Voltage ............................................................. 0 to V
CC
V
REF
Current ......................................... 800
A to +500
A
SD
LVL
Voltage ................................................. V
REF
to V
CC
Storage Temperature (T
S
) ....................... 55
C to +125
C
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) .............................. +3.0V to +3.6V or
............................................................ +4.5V to +5.5V
Ambient Temperature (T
A
), Note 3 ............ 40
C to +85
C
Junction Temperature (T
J
), Note 3 .......... 40
C to +120
C
Package Thermal Resistance
MSOP
(
JA
) Still-Air .................................................. 113
C/W
(
JB
) Still-Air .................................................... 74
C/W
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
2V; T
A
= 40
C to +85
C; typical values at V
CC
= 3.3V, T
A
= 25
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
CC
Power Supply Current
no output load
25
42
mA
SD
LVL
SD
LVL
Voltage
V
REF
V
CC
V
V
IH
EN Input HIGH Voltage
2.0
V
V
IL
EN Input LOW Voltage
0.8
V
I
IH
EN Input HIGH Current
V
IN
= 2.7V
20
A
V
IN
= V
CC
100
A
I
IL
EN Input LOW Current
V
IN
= 0.5V
0.3
mA
V
OH
SD Output HIGH Level
V
CC
> 3.3V
2.4
V
V
CC
< 3.3V
2.0
V
V
OL
SD Output LOW Level
I
OL
= +2mA
0.5
V
V
OH
PECL Output HIGH Voltage
50
to V
CC
2V output load
V
CC
1.085 V
CC
0.955 V
CC
0.880
V
V
OL
PECL Output LOW Voltage
50
to V
CC
2V output load
V
CC
1.830 V
CC
1.705 V
CC
1.555
V
V
OFFSET
Differential Output Offset
100
mV
V
IHCMR
Common Mode Range
Note 2
GND +1.7
V
CC
V
V
REF
Reference Voltage
Note 3
V
CC
1.38
V
CC
1.32
V
CC
1.26
V
Note 1.
Specification for packaged product only.
Note 2.
The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Note 3.
The current provided into or from V
REF
must be limited to 800
A source and 500
A sink.
DC ELECTRICAL CHARACTERISTICS
(Note 1)
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3.
Commercial devices are guaranteed from 0
C to +85
C ambient temperature.
4
SY88793V
Micrel
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
2V; T
A
= 40
C to +85
C; typical values at V
CC
= 3.3V, T
A
= 25
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
HYS
SD Hysteresis
electrical signal
2
4.6
8
dB
t
OFF
SD Release Time
0.1
0.5
s
t
ON
SD Assert Time
0.2
0.5
s
t
r
,t
f
Differential Output Rise/Fall Time
400
ps
(20% to 80%)
V
ID
Differential Input Voltage Swing
5
1800
mVp-p
V
OD
Differential Output Voltage Swing
V
ID
18mVp-p
1500
mVp-p
V
ID
= 5mVp-p
400
mVp-p
V
SR
SD Sensitivity Range
5
50
mVp-p
A
V(Diff)
Differential Voltage Gain
38
dB
B
3dB
3dB Bandwidth
700
MHz
S
21
Single-Ended Small-Signal Gain
26
32
dB
Note 1.
Specification for packaged product only.
AC ELECTRICAL CHARACTERISTICS
(Note 1)
TYPICAL OPERATING CHARACTERISTICS
0
20
40
60
80
100
120
140
1
10
100
1000
10000
100000
V
ID
(mVp-p)
R
SDLVL
(
)
V
SUP
= 3.3V
T
A
= 25
C
622Mbps
Pattern 2
23
1
ASSERT
DEASSERT
SD Assert and Deassert
Levels vs. R
SDLVL
0
20
40
60
80
100
120
0
0.2 0.4 0.6 0.8
1
1.2 1.4
V
ID
(mVp-p)
SD
LVL
(referenced to V
CC
) (V)
V
SUP
= 3.3V
T
A
= 25
C
622Mbps
Pattern 2
23
1
ASSERT
DEASSERT
SD Assert and Deassert
Levels vs. SD
LVL
5
SY88793V
Micrel
DETAILED DESCRIPTION
The SY88793V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from 40
C to +85
C. Signals with data rates up to 622Mbps
and as small as 5mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88793V generates
an SD output. SD
LVL
sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the SY88793V's
input stage. The high-sensitivity of the input amplifier allows
signals as small as 5mVp-p to be detected and amplified.
The input amplifier allows input signals as large as
1800mVp-p. Input signals are linearly amplified with a
typically 38dB differential voltage gain. Since it is a limiting
amplifier, the SY88793V outputs typically 1500mVp-p
voltage-limited waveforms for input signals that are greater
than 18mVp-p. Applications requiring the SY88793V to
operate with high-gain should have the upstream TIA placed
as close as possible to the SY88793V's input pins to ensure
the best performance of the device.
Output Buffer
The SY88793V's PECL output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC
2V
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
Signal-Detect
The SY88793V generates a chatter-free SD open-collector
TTL output with internal 6.75k
pullup resistor as shown in
Figure 4. SD is used to determine that the input amplitude
is large enough to be considered a valid input. SD asserts
high if the input amplitude rises above the threshold set by
SD
LVL
and deasserts low otherwise. SD can be fed back to
the enable (EN) input to maintain output stability under a
loss of signal condition. EN deasserts the true output signal
without removing the input signals. Typically 6dB SD
hysteresis is provided to prevent chattering.
Signal-Detect Level Set
A programmable SD level set pin (SD
LVL
) sets the
threshold of the input amplitude detection. Connecting an
external resistor between V
CC
and SD
LVL
sets the voltage
at SD
LVL
. This voltages ranges from V
CC
to V
REF
. The
external resistor creates a voltage divider between V
CC
and
V
REF
as shown in Figure 5. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL
to V
CC
, the smaller the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
"Typical Operating Characteristics"
shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL
voltage.
Hysteresis
The SY88793V provides typically 6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
2
IN
/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88793V provides typically 3dB SD
optical hysteresis. As the SY88793V is an electrical device,
this datasheet refers to hysteresis in electrical terms. With
6dB SD hysteresis, a voltage factor of two is required to
assert or deassert SD.
PDF 
ZIP